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1. 发明授权

US08791545B2 Interconnect structures and design structures for a radiofrequency integrated circuit 有权
标题翻译：射频集成电路的互连结构和设计结构
公开(公告)号：US08791545B2
公开(公告)日：2014-07-29
申请号：US13560446
申请日：2012-07-27
申请人： Timothy J. Dalton , Ebenezer E. Eshun , Sarah L. Grunow , Zhong-Xiang He , Anthony K. Stamper
发明人： Timothy J. Dalton , Ebenezer E. Eshun , Sarah L. Grunow , Zhong-Xiang He , Anthony K. Stamper
IPC分类号： H01L21/02
CPC分类号： H01L21/76885 , H01L21/76816 , H01L21/76832 , H01L21/76834 , H01L27/016 , H01L28/20 , H01L28/40
摘要： Interconnect structures that include a passive element, such as a thin film resistor or a metal-insulator-metal (MIM) capacitor, methods for fabricating an interconnect structure that includes a passive element, and design structures embodied in a machine readable medium for designing, manufacturing, or testing an integrated circuit, such as a radiofrequency integrated circuit. A top surface of a dielectric layer is recessed relative to a top surface of a conductive feature in the dielectric layer. The passive element is formed on the recessed top surface of the dielectric layer and includes a layer of a conductive material that is coplanar with, or below, the top surface of the conductive feature.
摘要翻译：包括诸如薄膜电阻器或金属 - 绝缘体 - 金属（MIM）电容器的无源元件的互连结构，用于制造包括无源元件的互连结构的方法，以及体现在机器可读介质中的设计结构，用于设计，制造或测试诸如射频集成电路的集成电路。电介质层的顶表面相对于电介质层中导电特征的顶表面凹陷。无源元件形成在介电层的凹入的顶表面上，并且包括与导电特征的顶表面共面或低于导电特征的顶表面的导电材料层。

2. 发明授权

US08486511B2 Pattern formation employing self-assembled material 有权
标题翻译：采用自组装材料的图案形成
公开(公告)号：US08486511B2
公开(公告)日：2013-07-16
申请号：US13430177
申请日：2012-03-26
申请人： Charles T. Black , Timothy J. Dalton , Bruce B. Doris , Carl J. Radens
发明人： Charles T. Black , Timothy J. Dalton , Bruce B. Doris , Carl J. Radens
IPC分类号： B32B3/00
CPC分类号： H01L21/0338 , B81B2203/0369 , B81C1/00031 , B81C2201/0149 , B81C2201/0198 , B82Y30/00 , H01L21/0337 , H01L51/0017 , Y10S977/882 , Y10S977/887 , Y10S977/888 , Y10T428/24479 , Y10T428/2457 , Y10T428/24612 , Y10T428/24736 , Y10T428/24802
摘要： In one embodiment, Hexagonal tiles encompassing a large are divided into three groups, each containing ⅓ of all hexagonal tiles that are disjoined among one another. Openings for the hexagonal tiles in each group are formed in a template layer, and a set of self-assembling block copolymers is applied and patterned within each opening. This process is repeated three times to encompass all three groups, resulting in a self-aligned pattern extending over a wide area. In another embodiment, the large area is divided into rectangular tiles of two non-overlapping and complementary groups. Each rectangular area has a width less than the range of order of self-assembling block copolymers. Self-assembled self-aligned line and space structures are formed in each group in a sequential manner so that a line and space pattern is formed over a large area extending beyond the range of order.
摘要翻译：在一个实施例中，包括大的六边形瓦片被分成三组，每组包含彼此分离的所有六边形瓦片的1/3。每个组中的六边形瓦片的开口形成在模板层中，并且在每个开口内施加并组合一组自组装嵌段共聚物。该过程重复三次以包含所有三组，导致在大面积上延伸的自对准图案。在另一个实施例中，大面积被分成两个不重叠和互补组的矩形瓦片。每个矩形区域的宽度小于自组装嵌段共聚物的顺序范围。在每组中以顺序的方式形成自组装的自对准线和空间结构，使得在超过有序范围的大面积上形成线和空间图案。

3. 发明授权

US08343868B2 Device and methodology for reducing effective dielectric constant in semiconductor devices 有权
标题翻译：用于降低半导体器件中有效介电常数的器件和方法
公开(公告)号：US08343868B2
公开(公告)日：2013-01-01
申请号：US13005201
申请日：2011-01-12
申请人： Daniel C. Edelstein , Matthew E. Colburn , Edward C. Cooney, III , Timothy J. Dalton , John A. Fitzsimmons , Jeffrey P. Gambino , Elbert E. Huang , Michael W. Lane , Vincent J. McGahay , Lee M. Nicholson , Satyanarayana V. Nitta , Sampath Purushothaman , Sujatha Sankaran , Thomas M. Shaw , Andrew H. Simon , Anthony K. Stamper
发明人： Daniel C. Edelstein , Matthew E. Colburn , Edward C. Cooney, III , Timothy J. Dalton , John A. Fitzsimmons , Jeffrey P. Gambino , Elbert E. Huang , Michael W. Lane , Vincent J. McGahay , Lee M. Nicholson , Satyanarayana V. Nitta , Sampath Purushothaman , Sujatha Sankaran , Thomas M. Shaw , Andrew H. Simon , Anthony K. Stamper
IPC分类号： H01L21/00
CPC分类号： B82Y30/00 , H01L21/0332 , H01L21/31111 , H01L21/31144 , H01L21/7682 , H01L21/76829 , H01L23/5222 , H01L23/53295 , H01L2924/0002 , Y10S438/947 , H01L2924/00
摘要： Method of manufacturing a structure which includes the steps of providing a structure having an insulator layer with at least one interconnect, forming a sub lithographic template mask over the insulator layer, and selectively etching the insulator layer through the sub lithographic template mask to form sub lithographic features spanning to a sidewall of the plurality of interconnects.
摘要翻译：一种制造结构的方法，包括以下步骤：提供具有至少一个互连的绝缘体层的结构，在绝缘体层上形成次级光刻模板掩模，以及通过次级光刻模板掩模选择性地蚀刻绝缘体层以形成次光刻特征跨越到多个互连的侧壁。

4. 发明授权

US07888729B2 Flash memory gate structure for widened lithography window 失效
标题翻译：用于加宽光刻窗的闪存门结构
公开(公告)号：US07888729B2
公开(公告)日：2011-02-15
申请号：US12198345
申请日：2008-08-26
申请人： Kangguo Cheng , Lawrence A. Clevenger , Timothy J. Dalton , Louis L. Hsu
发明人： Kangguo Cheng , Lawrence A. Clevenger , Timothy J. Dalton , Louis L. Hsu
IPC分类号： H01L21/336
CPC分类号： H01L29/7881 , H01L29/66825
摘要： A first portion of a semiconductor substrate belonging to a flash memory device region is recessed to a recess depth to form a recessed region, while a second portion of the semiconductor substrate belonging to a logic device region is protected with a masking layer. A first gate dielectric layer and a first gate conductor layer formed within the recessed region such that the first gate conductive layer is substantially coplanar with the top surfaces of the shallow trench isolation structures. A second gate dielectric layer, a second gate conductor layer, and a gate cap hard mask layer, each having a planar top surface, is subsequently patterned. The pattern of the gate structure in the flash memory device region is transferred into the first gate conductor layer and the first gate dielectric layer to form a floating gate and a first gate dielectric, respectively.
摘要翻译：属于闪存器件区域的半导体衬底的第一部分凹陷到凹陷深度以形成凹陷区域，而属于逻辑器件区域的半导体衬底的第二部分被掩蔽层保护。形成在凹陷区域内的第一栅介质层和第一栅极导体层，使得第一栅极导电层与浅沟槽隔离结构的顶表面基本共面。随后对第二栅介质层，第二栅极导体层和栅帽硬掩模层进行构图，每个具有平坦的顶表面。闪存器件区域中的栅极结构的图案被转移到第一栅极导体层和第一栅极介电层中，以分别形成浮置栅极和第一栅极电介质。

5. 发明授权

US07767587B2 Method of forming an interconnection structure in a organosilicate glass having a porous layer with higher carbon content located between two lower carbon content non-porous layers 失效
标题翻译：在具有位于两个低碳含量无孔层之间的具有较高碳含量的多孔层的有机硅酸盐玻璃中形成互连结构的方法
公开(公告)号：US07767587B2
公开(公告)日：2010-08-03
申请号：US12034692
申请日：2008-02-21
申请人： Nicholas C. M. Fuller , Timothy J. Dalton
发明人： Nicholas C. M. Fuller , Timothy J. Dalton
IPC分类号： H01L21/28 , H01L21/47
CPC分类号： H01L21/76835 , H01L21/76807 , H01L21/76808 , H01L21/76829 , H01L21/76834 , H01L23/5329 , H01L23/53295 , H01L2924/0002 , H01L2924/00
摘要： Interconnect structures possessing a non-porous (dense) low-k organosilicate glass (OSG) film utilizing a porous low-k OSG film as an etch stop layer or a porous low-k OSG film using a non-porous OSG film as a hardmask for use in semiconductor devices are provided herein. The novel interconnect structures are capable of delivering improved device performance, functionality and reliability owing to the reduced effective dielectric constant of the stack compared with that of those conventionally employed and also because of the relatively uniform line heights made feasible by these unique and seemingly counterintuitive features. The present invention also provides a fluorocarbon-based dual damascene etch process that achieves selective etching of a dense low-k OSG films relative to that of a porous low-k OSG film owing to the tunability of the gas-phase fluorine:carbon ratio (gas dissociation) and ion current below a critical threshold and given the larger carbon content of the porous film relative to that of the dense film.
摘要翻译：具有使用多孔低k OSG膜作为蚀刻停止层的无孔（致密）低k有机硅酸盐玻璃（OSG）膜的互连结构或使用无孔OSG膜作为硬掩模的多孔低k OSG膜用于半导体器件中。新颖的互连结构能够提供改进的器件性能，功能和可靠性，这是由于与传统采用的叠层相比，堆叠的有效介电常数降低，并且还因为这些独特且看似违反直觉的特征使得线的高度相对均匀。本发明还提供了一种基于碳氟化合物的双镶嵌蚀刻工艺，由于气相氟：碳比的可调性，实现了相对于多孔低k OSG膜的致密低k OSG膜的选择性蚀刻（气体离解）和离子电流低于临界阈值，并且给出多孔膜相对于致密膜的碳含量较大。

6. 发明授权

US07749778B2 Addressable hierarchical metal wire test methodology 失效
标题翻译：可寻址的分层金属线测试方法
公开(公告)号：US07749778B2
公开(公告)日：2010-07-06
申请号：US11619307
申请日：2007-01-03
申请人： Kaushik Chanda , Lawrence Clevenger , Timothy J. Dalton , Louis L. C. Hsu , Chih-Chao Yang
发明人： Kaushik Chanda , Lawrence Clevenger , Timothy J. Dalton , Louis L. C. Hsu , Chih-Chao Yang
IPC分类号： H01L21/66
CPC分类号： G01R31/2858 , H01L22/14 , H01L2924/0002 , Y10S438/927 , H01L2924/00
摘要： A method of monitoring and testing electro-migration and time dependent dielectric breakdown includes forming an addressable wiring test array, which includes a plurality or horizontally disposed metal wiring and a plurality of segmented, vertically disposed probing wiring, performing a single row continuity/resistance check to determine which row of said metal wiring is open, performing a full serpentine continuity/resistance check, and determining a position of short defects.
摘要翻译：一种监测和测试电迁移和时间依赖介电击穿的方法包括形成可寻址布线测试阵列，其包括多个或水平布置的金属布线和多个分段垂直布置的探测布线，执行单行连续性/电阻检查以确定所述金属布线的哪一行是打开的，执行完全蛇形连续性/电阻检查，以及确定短缺陷的位置。

7. 发明授权

US07528065B2 Structure and method for MOSFET gate electrode landing pad 有权
标题翻译： MOSFET栅极电极着陆焊盘的结构和方法
公开(公告)号：US07528065B2
公开(公告)日：2009-05-05
申请号：US11333068
申请日：2006-01-17
申请人： Lawrence A. Clevenger , Timothy J. Dalton , Louis C. Hsu , Carl Radens , Kwong-Hon Wong , Chih-Chao Yang
发明人： Lawrence A. Clevenger , Timothy J. Dalton , Louis C. Hsu , Carl Radens , Kwong-Hon Wong , Chih-Chao Yang
IPC分类号： H01L21/4763
CPC分类号： H01L27/1203 , H01L21/28114 , H01L21/823456 , H01L21/84 , H01L29/42376 , H01L2924/0002 , H01L2924/00
摘要： A transistor device and method of forming the same comprises a substrate; a first gate electrode over the substrate; a second gate electrode over the substrate; and a landing pad comprising a pair of flanged ends overlapping the second gate electrode, wherein the structure of the second gate electrode is discontinuous with the structure of the landing pad.
摘要翻译：晶体管器件及其形成方法包括：衬底; 衬底上的第一栅电极; 在所述衬底上方的第二栅电极; 以及着陆垫，其包括与所述第二栅电极重叠的一对凸缘端，其中所述第二栅极的结构与所述着陆焊盘的结构不连续。

8. 发明申请

US20090085152A1 THREE DIMENSIONAL VERTICAL E-FUSE STRUCTURES AND METHODS OF MANUFACTURING THE SAME 失效
标题翻译：三维垂直电子熔断器结构及其制造方法
公开(公告)号：US20090085152A1
公开(公告)日：2009-04-02
申请号：US11865079
申请日：2007-10-01
申请人： Kerry Bernstein , Timothy J. Dalton , Jeffrey P. Gambino , Mark D. Jaffe , Stephen E. Luce , Anthony K. Stamper
发明人： Kerry Bernstein , Timothy J. Dalton , Jeffrey P. Gambino , Mark D. Jaffe , Stephen E. Luce , Anthony K. Stamper
IPC分类号： H01L23/62 , H01L21/44
CPC分类号： H01L23/5256 , H01L23/62 , H01L2924/0002 , H01L2924/00
摘要： Three dimensional vertical e-fuse structures and methods of manufacturing the same are provided herein. The method of forming a fuse structure comprises providing a substrate including an insulator layer and forming an opening in the insulator layer. The method further comprises forming a conductive layer along a sidewall of the opening and filling the opening with an insulator material. The vertical e-fuse structure comprises a first contact layer and a second contact layer. The structure further includes a conductive material lined within a via and in electrical contact with the first contact layer and the second contact layer. The conductive material has an increased resistance as a current is applied thereto.
摘要翻译：本文提供三维垂直电子熔丝结构及其制造方法。形成熔丝结构的方法包括提供包括绝缘体层并在绝缘体层中形成开口的衬底。该方法还包括沿着开口的侧壁形成导电层并用绝缘体材料填充开口。垂直e熔丝结构包括第一接触层和第二接触层。该结构还包括衬里在通孔内并与第一接触层和第二接触层电接触的导电材料。当施加电流时，导电材料具有增加的电阻。

9. 发明授权

US07486845B2 Waveguide polarization beam splitters and method of fabricating a waveguide wire-grid polarization beam splitter 有权
标题翻译：波导偏振分束器及制造波导线栅偏振光束分离器的方法
公开(公告)号：US07486845B2
公开(公告)日：2009-02-03
申请号：US11870463
申请日：2007-10-11
申请人： Charles T. Black , Gian-Luca Bona , Timothy J. Dalton , Nicholas C. M. Fuller , Roland Germann , Maurice McGlashan-Powell , Chandrasekhar Narayan , Robert L. Sandstorm
发明人： Charles T. Black , Gian-Luca Bona , Timothy J. Dalton , Nicholas C. M. Fuller , Roland Germann , Maurice McGlashan-Powell , Chandrasekhar Narayan , Robert L. Sandstorm
IPC分类号： G02B6/00 , G02B6/10
CPC分类号： G02B6/126 , B29D11/00759 , G02B6/136 , G02B2006/1215
摘要： A method in effectuating the redirection of light which is propagated within a waveguide, and which eliminates the necessity for a bending of the waveguide, or the drawbacks encountered in directional changes in propagated light involving the need for sharp curves of essentially small-sized radii, which would resultingly lead to excessive losses in light. In this connection, the method relates to the fabricating and the provision of a wire-grid polarization beam splitter within an optical waveguide, which utilizes a diblock copolymer template to formulate the wire-grid.
摘要翻译：实现在波导内传播的光的重定向并且消除波导的弯曲的必要性的方法或者涉及需要基本上小的半径的尖锐曲线的传播光的方向性变化中遇到的缺点，这将导致轻微的过度损失。在这方面，该方法涉及在光波导内制造和提供线栅偏振分束器，其利用二嵌段共聚物模板来配制线栅。

10. 发明申请

US20080308801A1 STRUCTURE FOR STOCHASTIC INTEGRATED CIRCUIT PERSONALIZATION 失效
标题翻译： STOCHASTIC集成电路个性化结构
公开(公告)号：US20080308801A1
公开(公告)日：2008-12-18
申请号：US12193288
申请日：2008-08-18
申请人： Lawrence A. Clevenger , Matthew E. Colburn , Timothy J. Dalton , Michael C. Gaidis , Louis L. C. Hsu , Carl Radens , Keith Kwong Hon Wong , Chih-Chao Yang
发明人： Lawrence A. Clevenger , Matthew E. Colburn , Timothy J. Dalton , Michael C. Gaidis , Louis L. C. Hsu , Carl Radens , Keith Kwong Hon Wong , Chih-Chao Yang
IPC分类号： H01L23/58
CPC分类号： H01L23/576 , H01L21/31144 , H01L23/544 , H01L28/20 , H01L28/40 , H01L2223/54433 , H01L2223/5444 , H01L2924/0002 , H01L2924/19041 , H01L2924/19043 , H01L2924/30105 , H01L2924/00
摘要： A method of forming a stochastically based integrated circuit encryption structure includes forming a lower conductive layer over a substrate, forming a short prevention layer over the lower conductive layer, forming an intermediate layer over the short prevention layer, wherein the intermediate layer is characterized by randomly structured nanopore features. An upper conductive layer is formed over the random nanopore structured intermediate layer. The upper conductive layer is patterned into an array of individual cells, wherein a measurable electrical parameter of the individual cells has a random distribution from cell to cell with respect to a reference value of the electrical parameter.
摘要翻译：一种形成随机的集成电路加密结构的方法包括在衬底上形成下导电层，在下导电层上形成防短层，在短路防护层上形成中间层，其中中间层的特征是随机结构纳米孔特征。在无规纳米孔结构化中间层上形成上导电层。上导电层被图案化成单个单元的阵列，其中各个单元的可测量电参数相对于电参数的参考值具有从单元到单元的随机分布。

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