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1. 发明授权

US5687337A Mixed-endian computer system 失效
标题翻译：混合式计算机系统
公开(公告)号：US5687337A
公开(公告)日：1997-11-11
申请号：US394072
申请日：1995-02-24
申请人： Michael Joseph Carnevale , Martin Edward Hopkins , Larry Wayne Loen , Edward John Silha , Andrew Henry Wottreng
发明人： Michael Joseph Carnevale , Martin Edward Hopkins , Larry Wayne Loen , Edward John Silha , Andrew Henry Wottreng
IPC分类号： G06F12/04 , G06F9/34 , G06F9/38 , G06F9/46 , G06F12/08 , G06F13/40 , G06F13/00
CPC分类号： G06F9/30025 , G06F12/0802 , G06F13/4013 , G06F9/34 , G06F9/3824
摘要： A conventional bi-endian computer system is enhanced to include mixed-endian circuitry that allows the computer system to dynamically change its endian mode. The mixed-endian computer system can change endian mode on a task by task basis if necessary. The mixed-endian circuitry automatically formats the data in the form expected by the running task, regardless of whether the task expects the data to be in big endian format or in little endian format. The mixed-endian circuitry also formats big and little endian instructions such that they can execute on the same computer system.
摘要翻译：常规的双端计算机系统被增强以包括允许计算机系统动态地改变其端模式的混合端电路。如果需要，混合端计算机系统可以根据任务改变任务的端序模式。混合端序电路会以运行任务所期望的格式自动格式化数据，无论任务是期望数据是大端格式还是小端格式。混合端的电路还可以制作大而小的endian指令，使得它们可以在同一台计算机系统上执行。

2. 发明授权

US08191049B2 Method and apparatus for maintaining performance monitoring structures in a page table for use in monitoring performance of a computer program 失效
标题翻译：用于在页表中维护性能监视结构以用于监视计算机程序的性能的方法和装置
公开(公告)号：US08191049B2
公开(公告)日：2012-05-29
申请号：US12062416
申请日：2008-04-03
申请人： Frank Eliot Levine , Christopher Michael Richardson , Edward John Silha
发明人： Frank Eliot Levine , Christopher Michael Richardson , Edward John Silha
IPC分类号： G06F9/45
CPC分类号： G06F11/3636
摘要： A method and apparatus in a data processing system for measuring events associated with the execution of instructions are provided. Instructions are received at a processor in the data processing system. If a selected indicator is associated with the instruction, counting of each event associated with the execution of the instruction is enabled. In some embodiments, the performance indicators, counters, thresholds, and other performance monitoring structures may be stored in a page table that is used to translate virtual addresses into physical storage addresses. A standard page table is augmented with additional fields for storing the performance monitoring structures. These structures may be set by the performance monitoring application and may be queried and modified as events occur that require access to physical storage.
摘要翻译：提供了一种用于测量与执行指令相关的事件的数据处理系统中的方法和装置。在数据处理系统的处理器处接收指令。如果所选择的指示符与指令相关联，则启用与执行指令相关联的每个事件的计数。在一些实施例中，可以将性能指示符，计数器，阈值和其他性能监视结构存储在用于将虚拟地址转换为物理存储地址的页表中。标准页表增加了用于存储性能监视结构的附加字段。这些结构可以由性能监视应用程序设置，并且可以在需要访问物理存储的事件发生时进行查询和修改。

3. 发明申请

US20090193233A1 Mechanism for Avoiding Check Stops in Speculative Accesses While Operating in Real Mode 失效
标题翻译：在实模式下操作时避免检测停止的机制
公开(公告)号：US20090193233A1
公开(公告)日：2009-07-30
申请号：US12043747
申请日：2008-03-06
申请人： Ronald N. Kalla , Cathy May , Balaram Sinharoy , Edward John Silha , Shih-Hsiung S. Tung
发明人： Ronald N. Kalla , Cathy May , Balaram Sinharoy , Edward John Silha , Shih-Hsiung S. Tung
IPC分类号： G06F9/318
CPC分类号： G06F9/3861 , G06F9/30189 , G06F9/383 , G06F9/3842
摘要： A method and processor for avoiding check stops in speculative accesses. An execution unit, e.g., load/store unit, may be coupled to a queue configured to store instructions. A register, coupled to the execution unit, may be configured to store a value corresponding to an address in physical memory. When the processor is operating in real mode, the execution unit may retrieve the value stored in the register. Upon the execution unit receiving a speculative instruction, e.g., speculative load instruction, from the queue, a determination may be made as to whether the address of the speculative instruction is at or below the retrieved value. If the address of the speculative instruction is at or below this value, then the execution unit may safely speculatively execute this instruction while avoiding a check stop since all the addresses at or below this value are known to exist in physical memory.
摘要翻译：一种用于避免投机访问中检查停止的方法和处理器。执行单元，例如加载/存储单元，可以被耦合到被配置为存储指令的队列。耦合到执行单元的寄存器可被配置为存储对应于物理存储器中的地址的值。当处理器以实模式运行时，执行单元可以检索存储在寄存器中的值。在执行单元从队列接收诸如推测性加载指令的推测性指令之后，可以确定推测指令的地址是否在检索值以下。如果推测指令的地址处于或低于该值，则执行单元可以安全地推测性地执行该指令，同时避免检查停止，因为已知存在于该物理存储器中的所有地址或低于该值的地址。

4. 发明授权

US07370177B2 Mechanism for avoiding check stops in speculative accesses while operating in real mode 失效
标题翻译：在实模式下运行时避免检测停止的机制
公开(公告)号：US07370177B2
公开(公告)日：2008-05-06
申请号：US10424527
申请日：2003-04-25
申请人： Ronald N. Kalla , Cathy May , Balaram Sinharoy , Edward John Silha , Shih-Hsiung S. Tung
发明人： Ronald N. Kalla , Cathy May , Balaram Sinharoy , Edward John Silha , Shih-Hsiung S. Tung
IPC分类号： G06F9/30
CPC分类号： G06F9/3861 , G06F9/30189 , G06F9/383 , G06F9/3842
摘要： A method and processor for avoiding check stops in speculative accesses. An execution unit, e.g., load/store unit, may be coupled to a queue configured to store instructions. A register, coupled to the execution unit, may be configured to store a value corresponding to an address in physical memory. When the processor is operating in real mode, the execution unit may retrieve the value stored in the register. Upon the execution unit receiving a speculative instruction, e.g., speculative load instruction, from the queue, a determination may be made as to whether the address of the speculative instruction is at or below the retrieved value. If the address of the speculative instruction is at or below this value, then the execution unit may safely speculatively execute this instruction while avoiding a check stop since all the addresses at or below this value are known to exist in physical memory.
摘要翻译：一种用于避免投机访问中检查停止的方法和处理器。执行单元，例如加载/存储单元，可以被耦合到被配置为存储指令的队列。耦合到执行单元的寄存器可被配置为存储对应于物理存储器中的地址的值。当处理器以实模式运行时，执行单元可以检索存储在寄存器中的值。在执行单元从队列接收诸如推测性加载指令的推测性指令之后，可以确定推测指令的地址是否在检索值以下。如果推测指令的地址处于或低于该值，则执行单元可以安全地推测性地执行该指令，同时避免检查停止，因为已知存在于该物理存储器中的所有地址或低于该值的地址。

5. 发明授权

US06950978B2 Method and apparatus for parity error recovery 有权
标题翻译：用于奇偶校验错误恢复的方法和装置
公开(公告)号：US06950978B2
公开(公告)日：2005-09-27
申请号：US09821061
申请日：2001-03-29
申请人： Richard Louis Arndt , Alongkorn Kitamorn , Edward John Silha , Scott Douglas Walton , David R. Willoughby
发明人： Richard Louis Arndt , Alongkorn Kitamorn , Edward John Silha , Scott Douglas Walton , David R. Willoughby
IPC分类号： G06F11/00 , G06F11/07 , G06F11/10 , G11C29/00 , H03M13/00
CPC分类号： G06F11/0712 , G06F11/073 , G06F11/076 , G06F11/0793 , G06F11/1064 , G06F12/0802 , G06F12/1027 , G06F2212/1032
摘要： A method, apparatus, and computer implemented instructions for processing and recovering from soft errors in computer array with a parity error checking design in a data processing system. In response to an occurrence of a parity error, processor status information is stored to form stored processor information. A determination is made as to whether the parity error is a recoverable parity error using the stored processor information. In response to the parity error being a recoverable parity error, a recovery action is performed. The specific action taken varies depending on the type of error.
摘要翻译：一种用于在数据处理系统中具有奇偶校验错误检查设计的计算机阵列中的软错误进行处理和恢复的方法，装置和计算机实现的指令。响应于奇偶校验错误的发生，存储处理器状态信息以形成存储的处理器信息。使用存储的处理器信息确定奇偶校验错误是否是可恢复的奇偶校验错误。响应于奇偶校验错误是可恢复奇偶校验错误，执行恢复动作。所采取的具体措施取决于错误的类型。

6. 发明授权

US5802378A Performance monitoring in multiprocessor system with interrupt masking 失效
标题翻译：具有中断屏蔽功能的多处理器系统中的性能监控
公开(公告)号：US5802378A
公开(公告)日：1998-09-01
申请号：US675427
申请日：1996-06-26
申请人： Richard Louis Arndt , Frank Eliot Levine , Edward John Silha , Edward Hugh Welbon
发明人： Richard Louis Arndt , Frank Eliot Levine , Edward John Silha , Edward Hugh Welbon
IPC分类号： G06F9/48 , G06F9/46 , G06F11/30 , G06F11/34 , G06F15/78 , G06F7/00
CPC分类号： G06F11/3495
摘要： The present invention provides a system and method which ensures that machine state data, for each CPU in an MP system, corresponding to a specific point in time will always be saved, regardless of whether the system interrupt handler is enabled or disabled. A series of special purpose registers (SPR) are included, which are associated with the performance monitoring mechanism in each processor in the MP system. A time base mechanism in each CPU is used and synchronized across the entire MP system. When the time base mechanism requests that the machine state be recorded, the performance monitor then immediately stores the machine state values in the special purpose registers. Thus, the state of the each CPU in the MP system is saved at the identical point in time. The performance monitor issues an interrupt request to the interrupt handler and, if interrupts are enabled, the machine state data is stored for post-processing, or the like. However, if the interrupt handler has disabled interrupts, then the machine state data remains in the SPRs until interrupts are enabled and the data (corresponding to the same point in time) is then read from the special purpose registers into memory, or the like, for post-processing.
摘要翻译：本发明提供一种系统和方法，其确保对于MP系统中的每个CPU对应于特定时间点的机器状态数据将始终被保存，而不管系统中断处理程序是启用还是禁用。包括一系列专用寄存器（SPR），与MP系统中每个处理器的性能监视机制相关联。每个CPU中的时基机制在整个MP系统中被使用和同步。当时基机制请求记录机器状态时，性能监视器立即将机器状态值存储在专用寄存器中。因此，MP系统中的每个CPU的状态保存在相同的时间点。性能监视器向中断处理程序发出中断请求，并且如果允许中断，则存储机器状态数据用于后处理等。然而，如果中断处理程序禁止中断，则机器状态数据保留在SPR中，直到中断被使能，然后将数据（对应于同一时间点）从专用寄存器读取到存储器等中，用于后期处理。

7. 发明授权

US5673399A System and method for enhancement of system bus to mezzanine bus transactions 失效
标题翻译：将系统总线增强到夹层总线交易的系统和方法
公开(公告)号：US5673399A
公开(公告)日：1997-09-30
申请号：US552034
申请日：1995-11-02
申请人： Guy Lynn Guthrie , Danny Marvin Neal , Edward John Silha , Steven Mark Thurber
发明人： Guy Lynn Guthrie , Danny Marvin Neal , Edward John Silha , Steven Mark Thurber
IPC分类号： G06F13/36 , G06F13/40 , G06F13/00
CPC分类号： G06F13/4027
摘要： A data processing system includes a host processor, a number of peripheral devices, and one or more bridges which may connect between the host, peripheral devices and other hosts or peripheral devices such as in a network. Each bridge, such as a PCI host bridge, connects between a primary bus (e.g system bus) and a secondary bus wherein for the purpose of clarity, the primary bus will be considered as the source for outbound transactions and the destination for inbound transactions and the secondary bus would be considered the destination for outbound transactions and the source for inbound transactions. The host bridge includes an outbound data path, an inbound data path, and a control mechanism. The outbound data path includes a queued buffer for storing transactions in order of receipt from the primary bus where the requests in the queued buffer may be mixed as between read requests and write transactions, the outbound path also includes a number of parallel buffers for storing read reply data and address information. The inbound path is a mirror image of the outbound path with read requests and write requests being stored in a sequential buffer and read replies being stored in a number of parallel buffers. Both the inbound path and the outbound path in the host bridge are controlled by a state machine which takes into consideration activity in both directions and permits or inhibits bypass transactions based on the protocol of the buses being interconnected through the bridge.
摘要翻译：数据处理系统包括主处理器，多个外围设备以及可以在主机，外围设备和其他主机或诸如网络中的外围设备之间连接的一个或多个网桥。每个桥梁（如PCI主机桥）连接在主总线（例如系统总线）和辅助总线之间，为了清楚起见，主总线将被视为出站事务的来源和入站事务的目的地，辅助总线将被视为出站交易的目的地和入站交易的来源。主桥包括出站数据路径，入站数据路径和控制机制。出站数据路径包括排队缓冲器，用于按照从主总线接收的顺序存储事务，其中排队缓冲器中的请求可以在读请求和写事务之间混合，出站路径还包括多个用于存储读取的并行缓冲器回复数据和地址信息。入站路径是出站路径的镜像，读取请求和写入请求存储在顺序缓冲区中，并且读取回复存储在多个并行缓冲区中。主桥中的入站路径和出站路径都由状态机控制，该状态机考虑到两个方向的活动，并且基于通过桥互连的总线的协议允许或禁止旁路交易。

8. 发明申请

US20120066516A1 METHOD FOR FAST DECRYPTION OF PROCESSOR INSTRUCTIONS 有权
标题翻译：快速分解处理器指令的方法
公开(公告)号：US20120066516A1
公开(公告)日：2012-03-15
申请号：US13301227
申请日：2011-11-21
申请人： Gordon D. McIntosh , Edward John Silha
发明人： Gordon D. McIntosh , Edward John Silha
IPC分类号： H04L9/00 , G06F9/30
CPC分类号： G06F21/57 , G06F9/30178 , G06F9/3802 , G06F21/71 , G06F21/72 , G06F21/85
摘要： A processor, circuit and method provide for fast decryption of encrypted program instructions for execution by the processor. A programmable look-up coding is used to decode a field within the instructions. The decoded field for the instructions are recombined with the remaining portion of the same instructions to yield the decoded instructions. The programmable look-up coding can be programmed and controlled by a process executing at a higher privilege level than the program represented by the instructions, so that security against code-modifying attacks is enhanced.
摘要翻译：处理器，电路和方法提供加密程序指令的快速解密以供处理器执行。使用可编程查找编码来对指令内的字段进行解码。用于指令的解码字段与相同指令的剩余部分重组以产生解码指令。可编程查找编码可以由比由指令表示的程序更高的特权级别执行的进程来编程和控制，从而增强了针对代码修改攻击的安全性。

9. 发明授权

US07949859B2 Mechanism for avoiding check stops in speculative accesses while operating in real mode 失效
标题翻译：在实模式下运行时避免检测停止的机制
公开(公告)号：US07949859B2
公开(公告)日：2011-05-24
申请号：US12043747
申请日：2008-03-06
申请人： Ronald N. Kalla , Cathy May , Balaram Sinharoy , Edward John Silha , Shih-Hsiung S. Tung
发明人： Ronald N. Kalla , Cathy May , Balaram Sinharoy , Edward John Silha , Shih-Hsiung S. Tung
IPC分类号： G06F9/00
CPC分类号： G06F9/3861 , G06F9/30189 , G06F9/383 , G06F9/3842
摘要： A method and processor for avoiding check stops in speculative accesses. An execution unit, e.g., load/store unit, may be coupled to a queue configured to store instructions. A register, coupled to the execution unit, may be configured to store a value corresponding to an address in physical memory. When the processor is operating in real mode, the execution unit may retrieve the value stored in the register. Upon the execution unit receiving a speculative instruction, e.g., speculative load instruction, from the queue, a determination may be made as to whether the address of the speculative instruction is at or below the retrieved value. If the address of the speculative instruction is at or below this value, then the execution unit may safely speculatively execute this instruction while avoiding a check stop since all the addresses at or below this value are known to exist in physical memory.
摘要翻译：一种用于避免投机访问中检查停止的方法和处理器。执行单元，例如加载/存储单元，可以被耦合到被配置为存储指令的队列。耦合到执行单元的寄存器可被配置为存储对应于物理存储器中的地址的值。当处理器以实模式运行时，执行单元可以检索存储在寄存器中的值。在执行单元从队列接收诸如推测性加载指令的推测性指令之后，可以确定推测指令的地址是否在检索值以下。如果推测指令的地址处于或低于该值，则执行单元可以安全地推测性地执行该指令，同时避免检查停止，因为已知存在于该物理存储器中的所有地址或低于该值的地址。

10. 发明授权

US07904661B2 Data stream prefetching in a microprocessor 失效
标题翻译：数据流在微处理器中预取
公开(公告)号：US07904661B2
公开(公告)日：2011-03-08
申请号：US11953637
申请日：2007-12-10
申请人： Eric Jason Fluhr , Bradly George Frey , John Barry Griswell, Jr. , Hung Qui Le , Cathy May , Francis Patrick O'Connell , Edward John Silha , Albert Thomas Williams
发明人： Eric Jason Fluhr , Bradly George Frey , John Barry Griswell, Jr. , Hung Qui Le , Cathy May , Francis Patrick O'Connell , Edward John Silha , Albert Thomas Williams
IPC分类号： G06F12/00 , G06F13/00
CPC分类号： G06F12/0862 , G06F2212/6028
摘要： A method of prefetching data in a microprocessor includes identifying a data stream associated with a process and determining a depth associated with the data stream based upon prefetch factors including the number of currently concurrent data streams and data consumption rates associated with the concurrent data streams. Data prefetch requests are allocated with the data stream to reflect the determined depth of the data stream. Allocating data prefetch requests may include allocating prefetch requests for a number of cache lines away from the cache line currently being referenced, wherein the number of cache lines is equal to the determined depth. The method may include, responsive to determining the depth associated with a data stream, configuring prefetch hardware to reflect the determined depth for the identified data stream. Prefetch control bits in an instruction executed by the processor control the prefetch hardware configuration.
摘要翻译：在微处理器中预取数据的方法包括基于包括当前并发数据流的数量和与并发数据流相关联的数据消耗速率的预取因子来识别与进程相关联的数据流并确定与数据流相关联的深度。数据预取请求被分配与数据流以反映确定的数据流的深度。分配数据预取请求可以包括为当前被引用的高速缓存行分配多个高速缓存行的预取请求，其中高速缓存行的数量等于所确定的深度。该方法可以响应于确定与数据流相关联的深度，配置预取硬件以反映所识别的数据流的确定的深度。由处理器执行的指令中的预取控制位控制预取硬件配置。

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