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1. 发明授权

US07549090B2 Autonomic recovery from hardware errors in an input/output fabric 有权
标题翻译：从输入/输出结构中的硬件错误自动恢复
公开(公告)号：US07549090B2
公开(公告)日：2009-06-16
申请号：US11466290
申请日：2006-08-22
申请人： David Alan Bailey , Trung Ngoc Nguyen , Gregory Michael Nordstrom , Kanisha Patel , Steven Mark Thurber
发明人： David Alan Bailey , Trung Ngoc Nguyen , Gregory Michael Nordstrom , Kanisha Patel , Steven Mark Thurber
IPC分类号： G06F11/00
CPC分类号： G06F11/0793 , G06F11/0712 , G06F11/0745
摘要： An apparatus, program product and method propagate errors detected in an IO fabric element from an IO fabric that is used to couple a plurality of endpoint IO resources to processing elements in a computer. In particular, such errors are propagated to the endpoint IO resources affected by the IO fabric element in connection with recovering from the errors in the IO fabric element. By doing so, a device driver or other program code used to access each affected IO resources may be permitted to asynchronously recover from the propagated error in its associated IO resource, and often without requiring the recovery from the error in the IO fabric element to wait for recovery to be completed for each of the affected IO resources. In addition, an IO fabric may be dynamically configured to support both recoverable and non-recoverable endpoint IO resources. In particular, IO fabric elements within an IO fabric may be dynamically configured to enable machine check signaling in such IO fabric elements in response to detection that an endpoint IO resource is non-recoverable in nature. The IO fabric elements that are dynamically configured as such are disposed within a hardware path that is defined between the non-recoverable resource and a processor that accesses the non-recoverable resource.
摘要翻译：装置，程序产品和方法将用于将多个端点IO资源耦合到计算机中的处理元件的IO架构在IO结构元素中检测到的错误传播。特别地，这些错误被传播到由IO结构元素影响的端点IO资源以及从IO结构元素中的错误的恢复。通过这样做，可以允许用于访问每个受影响的IO资源的设备驱动程序或其他程序代码从其关联的IO资源中的传播错误异步恢复，并且通常不需要从IO架构元素中的错误中恢复以等待以便为每个受影响的IO资源完成恢复。此外，IO结构可以动态配置为支持可恢复和不可恢复的端点IO资源。特别地，IO结构中的IO结构元素可以被动态地配置成使得在这种IO结构元素中的机器检查信令能够响应于端点IO资源在本质上是不可恢复的检测。被动态地配置的IO结构元素被布置在在不可恢复资源和访问不可恢复资源的处理器之间定义的硬件路径中。

2. 发明授权

US07266631B2 Isolation of input/output adapter traffic class/virtual channel and input/output ordering domains 失效
标题翻译：输入/输出适配器流量类/虚拟通道和输入/输出排序域的隔离
公开(公告)号：US07266631B2
公开(公告)日：2007-09-04
申请号：US10902611
申请日：2004-07-29
申请人： Richard Louis Arndt , Patrick Allen Buckland , Gregory Michael Nordstrom , Steven Mark Thurber
发明人： Richard Louis Arndt , Patrick Allen Buckland , Gregory Michael Nordstrom , Steven Mark Thurber
IPC分类号： G06F13/20 , G06F13/36 , G06F13/40 , G06F13/10
CPC分类号： G06F13/126
摘要： Method, apparatus and system for controlling input/output adapter data flow operations in a data processing system that includes at least one of a traffic class mechanism in conjunction with virtual channel resources so as to be able to associate Load/Store and DMA flows to/from an input/output adapter, and a relaxed ordering mechanism for associating a relaxed ordering bit to Load/Store operations to an input/output adapter. Functionality for controlling the input/output adapter data flow is provided in a host bridge that connects the input/output adapter to a system bus of the data processing system.
摘要翻译：用于控制数据处理系统中的输入/输出适配器数据流操作的方法，装置和系统，该数据处理系统包括结合虚拟信道资源的业务类机制中的至少一个，以便能够将加载/存储和DMA流关联到/ 以及用于将放松的排序位与加载/存储操作相关联的输入/输出适配器的放松排序机制。用于控制输入/输出适配器数据流的功能在将输入/输出适配器连接到数据处理系统的系统总线的主机桥中提供。

3. 发明授权

US07113995B1 Method and apparatus for reporting unauthorized attempts to access nodes in a network computing system 有权
标题翻译：用于报告未经授权的访问网络计算系统中的节点的尝试的方法和装置
公开(公告)号：US07113995B1
公开(公告)日：2006-09-26
申请号：US09692348
申请日：2000-10-19
申请人： Bruce Leroy Beukema , Danny Marvin Neal , Gregory Francis Pfister , Renato John Recio , Steven Mark Thurber
发明人： Bruce Leroy Beukema , Danny Marvin Neal , Gregory Francis Pfister , Renato John Recio , Steven Mark Thurber
IPC分类号： G06F15/16
CPC分类号： H04L63/10 , H04L63/08
摘要： A method in a node for managing authorized attempts to access the node. A packet is received from a source, wherein the packet includes a first key. A determination is made as to whether the first key matches a second key for the node. The packet is dropped without a response to the source if the first key does not match the second key. Information from the packet is stored in response to this absence of a match. The information is sent to a selected recipient in response to a selected event, which may be, for example, either immediately or in response to polling to see if the information is present.
摘要翻译：用于管理访问节点的授权尝试的节点中的方法。从源接收分组，其中分组包括第一密钥。确定第一个密钥是否与节点的第二个密钥相匹配。如果第一个密钥与第二个密钥不匹配，数据包将被丢弃而不对源进行响应。来自数据包的信息被存储以响应于缺少匹配。响应于所选择的事件将信息发送到所选择的接收者，所选择的事件可以是例如立即地或响应于轮询来查看信息是否存在。

4. 发明授权

US07099955B1 End node partitioning using LMC for a system area network 有权
标题翻译：对于系统区域网络，使用LMC的端节点分区
公开(公告)号：US07099955B1
公开(公告)日：2006-08-29
申请号：US09692351
申请日：2000-10-19
申请人： Thomas Anthony Gregg , Gregory Francis Pfister , Renato John Recio , Steven Mark Thurber
发明人： Thomas Anthony Gregg , Gregory Francis Pfister , Renato John Recio , Steven Mark Thurber
IPC分类号： G06F15/173
CPC分类号： H04L29/12254 , H04L29/12783 , H04L61/2038 , H04L61/35 , H04L67/1097 , Y10S707/99932
摘要： A method for routing System Area Network (SAN) packets to multiple partitions within a single end node is provided. A range of Local Identification addresses (LIDs) are assigned to a channel adapter port within the SAN. Lower order bits within the LID are then assigned to select the particular partition in the end node. The Local ID Mask Control (LMC) field is used to assign multiple LIDs to a single port, using those low order bits to then route the message to the appropriate partition in the end node.
摘要翻译：提供了将系统区域网（SAN）数据包路由到单个端节点内的多个分区的方法。本地标识地址（LID）的范围被分配给SAN中的通道适配器端口。然后分配LID中的低位位以选择端节点中的特定分区。本地ID掩码控制（LMC）字段用于将多个LID分配给单个端口，使用这些低位位置将消息路由到最终节点中的相应分区。

5. 发明授权

US06941350B1 Method and apparatus for reliably choosing a master network manager during initialization of a network computing system 有权
标题翻译：在网络计算系统的初始化期间可靠地选择主网络管理器的方法和装置
公开(公告)号：US06941350B1
公开(公告)日：2005-09-06
申请号：US09692346
申请日：2000-10-19
申请人： Giles Roger Frazier , Gregory Francis Pfister , Steven Mark Thurber , Dono Van-Mierop
发明人： Giles Roger Frazier , Gregory Francis Pfister , Steven Mark Thurber , Dono Van-Mierop
IPC分类号： G06F15/16 , G06F15/173
CPC分类号： G06F15/17375 , H04L63/061
摘要： A method in a node within network computing system for selecting a master network manager, wherein the first node is associated with a first priority. Requests are sent to the network computing system to discover other nodes within the network computing system. A second priority from the request is identified in response to receiving a response to one of the requests from another node within the network computing system. The first node shifts to a standby mode if it discovers a master subnet manager or the second priority is higher than the first priority. The first node shifts to a master mode if a response containing a priority higher than the first priority is absent in responses received by the first node and the first node has completed checking all other nodes in the network computing system. In the case where the priority received is equal, the comparison is further made on the globally unique identifier which is received from the same node, in which case the node with the lowest globally unique identifier wins the arbitration.
摘要翻译：网络计算系统内用于选择主网络管理器的节点中的方法，其中所述第一节点与第一优先级相关联。将请求发送到网络计算系统以发现网络计算系统内的其他节点。响应于响应于来自网络计算系统内的另一个节点的一个请求的响应来识别来自请求的第二优先级。如果发现主子网管理器或第二优先级高于第一优先级，则第一节点转移到待机模式。如果在由第一节点接收的响应中缺少包含高于第一优先级的优先级的响应，则第一节点转移到主模式，并且第一节点已经完成了对网络计算系统中的所有其他节点的检查。在接收到的优先级相等的情况下，进一步对从同一节点接收到的全局唯一标识符进行比较，在这种情况下，具有最低全局唯一标识符的节点赢得仲裁。

6. 发明授权

US06823404B2 DMA windowing in an LPAR environment using device arbitration level to allow multiple IOAs per terminal bridge 有权
标题翻译：使用设备仲裁级别在LPAR环境中DMA窗口，以允许每个终端桥接多个IOA
公开(公告)号：US06823404B2
公开(公告)日：2004-11-23
申请号：US09766764
申请日：2001-01-23
申请人： Richard Louis Arndt , Danny Marvin Neal , Steven Mark Thurber
发明人： Richard Louis Arndt , Danny Marvin Neal , Steven Mark Thurber
IPC分类号： G06F300
CPC分类号： G06F13/28
摘要： A method, system, and apparatus for preventing input/output (I/O) adapters used by an operating system (OS) image, in a logically partitioned data processing system, from fetching or corrupting data from a memory location allocated to another OS image within the data processing system is provided. A hypervisor prevents transmission of data between an input/output adapter in one of the logical partitions and memory locations assigned to other logical partitions during a direct memory access (DMA) operation by assigning each of the input/output adapters a range of I/O bus DMA addresses. The I/O adapters (IOAs) are connected to PCI host bridges via terminal bridges. A single terminal bridge may support multiple IOAs, in which case every terminal bridge has a plurality of sets of range registers, each associated with a respective one of the IOAs to which it is connected. An arbiter is provided which selects one of the input/output adapters to use the PCI bus. The terminal bridge can examine the grant signals from the arbiter to the IOAs, to determine which set of range registers is to be used.
摘要翻译：用于防止在逻辑分区的数据处理系统中由操作系统（OS）映像使用的输入/输出（I / O）适配器的方法，系统和装置从分配给另一个OS映像的存储器位置获取或破坏数据在数据处理系统内提供。虚拟机管理程序防止在直接存储器访问（DMA）操作期间通过分配每个输入/输出适配器一个I / O范围的逻辑分区之一和分配给其他逻辑分区的存储器位置之间的输入/输出适配器之间的数据传输总线DMA地址。 I / O适配器（IOA）通过终端桥连接到PCI主机桥。单个终端桥可以支持多个IOA，在这种情况下，每个终端桥具有多组范围寄存器，每个范围寄存器与其所连接的IOA中的相应一个相关联。提供了一个仲裁器，其选择一个输入/输出适配器来使用PCI总线。终端桥可以检查从仲裁器到IOA的授权信号，以确定要使用哪个范围寄存器组。

7. 发明授权

US06643727B1 Isolation of I/O bus errors to a single partition in an LPAR environment 有权
标题翻译：在LPAR环境中将I / O总线错误隔离到单个分区
公开(公告)号：US06643727B1
公开(公告)日：2003-11-04
申请号：US09589664
申请日：2000-06-08
申请人： Richard Louis Arndt , Steven Mark Thurber
发明人： Richard Louis Arndt , Steven Mark Thurber
IPC分类号： G06F1336
CPC分类号： H04L1/00
摘要： A method, system, and apparatus for isolating an input/output (I/O) bus error, received from an I/O adapter, from the other I/O adapters that may be in different partitions within a logically partitioned data process system is provided. In one embodiment, the logically partitioned data processing system includes a system bus, a processing unit, a memory unit, a host bridge, a plurality of terminal bridges, and a plurality of input/output adapters. The processing unit, memory unit, and the host bridge are all coupled to each other through the system bus. Each of the plurality of terminal bridges is coupled to the host bridge through a first bus. Each of the input/output adapters is coupled to one of the plurality of terminal bridges through a one of a plurality of second buses, such that each input/output adapter corresponds to a single terminal bridge. Each of the input/output adapters are assigned to one of a plurality of logical partitions within the data processing system. Each of the terminal bridges isolates errors received from a respective one of the input/output adapters from other input/output adapters, some of which may be within a different one of the plurality of logical partitions.
摘要翻译：用于将从I / O适配器接收的输入/输出（I / O）总线错误与可能在逻辑分区数据处理系统中的不同分区中的其他I / O适配器隔离的方法，系统和装置是提供。在一个实施例中，逻辑分区数据处理系统包括系统总线，处理单元，存储单元，主桥，多个终端桥以及多个输入/输出适配器。处理单元，存储单元和主桥都通过系统总线相互耦合。多个终端桥中的每一个通过第一总线耦合到主桥。每个输入/输出适配器通过多个第二总线中的一个耦合到多个终端桥中的一个，使得每个输入/输出适配器对应于单个终端桥。每个输入/输出适配器被分配给数据处理系统内的多个逻辑分区中的一个。每个终端桥将从相应的一个输入/输出适配器接收的错误与其他输入/输出适配器隔离，其中一些输入/输出适配器中的一些可能在多个逻辑分区中的不同的一个之内。

8. 发明授权

US06636947B1 Coherency for DMA read cached data 有权
标题翻译： DMA读取缓存数据的一致性
公开(公告)号：US06636947B1
公开(公告)日：2003-10-21
申请号：US09645177
申请日：2000-08-24
申请人： Danny Marvin Neal , Steven Mark Thurber
发明人： Danny Marvin Neal , Steven Mark Thurber
IPC分类号： G06F1212
CPC分类号： G06F12/0817 , G06F2212/621
摘要： A method and implementing computer system are provided which enable a process for implementing a coherency system for bridge-cached data which is accessed by adapters and adapter bridge circuits which are normally outside of the system coherency domain. An extended architecture includes one or more host bridges. At least one of the host bridges is coupled to I/O adapter devices through a lower-level bus-to-bus bridge and one or more I/O busses. The host bridge maintains a buffer coherency directory and when Invalidate commands are received by the host bridge, the bridge buffers containing the referenced data are identified and the indicated data are invalidated.
摘要翻译：提供了一种方法和实现的计算机系统，其使得能够实现用于桥接缓存数据的一致性系统的过程，所述数据由通常在系统一致性域外的适配器和适配器桥接电路访问。扩展架构包括一个或多个主机桥。主桥中的至少一个通过下层总线到总线桥和一个或多个I / O总线耦合到I / O适配器设备。主机桥保持缓冲区一致性目录，当Host Bridge接收到Invalidate命令时，将标识包含引用数据的桥接缓冲区，并指示数据无效。

9. 发明授权

US06581129B1 Intelligent PCI/PCI-X host bridge 失效
标题翻译：智能PCI / PCI-X主机桥
公开(公告)号：US06581129B1
公开(公告)日：2003-06-17
申请号：US09414339
申请日：1999-10-07
申请人： Pat Allen Buckland , Daniel Frank Moertl , Danny Marvin Neal , Steven Mark Thurber , Scott Michael Willenborg , Curtis Carl Wollbrink , Adalberto Guillermo Yanes
发明人： Pat Allen Buckland , Daniel Frank Moertl , Danny Marvin Neal , Steven Mark Thurber , Scott Michael Willenborg , Curtis Carl Wollbrink , Adalberto Guillermo Yanes
IPC分类号： G06F1336
CPC分类号： G06F13/4027
摘要： A PCI host bridge and an associated method of use are disclosed. The PCI host bridge includes a host bus interface, an I/O bus interface, and a PCI operation detection circuit. The host bus interface is suitable for communicating with a host bus of a data processing system and the I/O bus interface is suitable for communicating with a primary PCI bus operating in PCI-X mode. The PCI operation detection circuit is adapted to detect a PCI-X operation from the primary PCI bus that may have issued from a PCI mode adapter coupled to a secondary PCI bus. The detection circuit is further adapted to generate a modified operation for forwarding to the host bus in response to determining that the PCI-X operation may have originated from a PCI. mode adapter.
摘要翻译：公开了PCI主机桥和相关联的使用方法。 PCI主机桥包括主机总线接口，I / O总线接口和PCI操作检测电路。主机总线接口适用于与数据处理系统的主机总线进行通信，I / O总线接口适用于与PCI-X模式下工作的主PCI总线进行通信。 PCI操作检测电路适于检测可能从耦合到辅助PCI总线的PCI模式适配器发出的主PCI总线的PCI-X操作。检测电路还适于响应于确定PCI-X操作可能源自于PCI而产生用于转发到主机总线的修改操作。模式适配器。

10. 发明授权

US06457077B1 System for executing a current information transfer request even when current information transfer request exceeds current available capacity of a transit buffer 有权
标题翻译：即使当前信息传送请求超过传送缓冲器的当前可用容量时，也执行当前信息传送请求的系统
公开(公告)号：US06457077B1
公开(公告)日：2002-09-24
申请号：US09329459
申请日：1999-06-10
申请人： Richard A. Kelley , Danny Marvin Neal , Steven Mark Thurber , Adalberto Guillermo Yanes
发明人： Richard A. Kelley , Danny Marvin Neal , Steven Mark Thurber , Adalberto Guillermo Yanes
IPC分类号： G06F1314
CPC分类号： G06F13/4059
摘要： A method and implementing system is provided in which system bridge circuits are enabled to execute, or over-commit to, transaction requests from system devices for information transfers which exceed the bridge circuit's current capacity to receive the requested information on its return from a designated target device such as system memory or another system device. The transaction request is moved along the data path to the designated target device and the requested information is returned, in an example, to the requesting device. By the time the requested information is returned to the requesting bridge circuit, a number of the holding buffers usually have been freed-up and are available to accept and pass the information to the requesting device. In an illustrated embodiment, the amount of over-commitment is programmable and the amount of over-commitment to transaction requests may be automatically adjusted to optimize the information transfer in accordance with the particular system demands and current data transfer traffic levels.
摘要翻译：提供了一种方法和实现系统，其中系统桥电路能够执行或过度提交来自用于信息传输的系统设备的事务请求，该信息传输超过桥电路的当前容量，以便在从指定目标返回时接收所请求的信息设备如系统内存或其他系统设备。交易请求沿着数据路径移动到指定的目标设备，并且所请求的信息在示例中返回到请求设备。当所请求的信息被返回到请求桥接电路时，多个保持缓冲器通常已经被释放并且可用于接受并将该信息传递给请求设备。在所示实施例中，过度承诺的量是可编程的，并且可以自动调整对交易请求的过度承诺的量，以根据特定系统需求和当前数据传输流量水平优化信息传递。

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