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1. 发明授权

US08912626B2 eFuse and method of fabrication 有权
标题翻译： eFuse和制造方法
公开(公告)号：US08912626B2
公开(公告)日：2014-12-16
申请号：US13013055
申请日：2011-01-25
申请人： Edward P. Maciejewski , Dustin Kenneth Slisher , Stefan Zollner
发明人： Edward P. Maciejewski , Dustin Kenneth Slisher , Stefan Zollner
IPC分类号： H01L23/525
CPC分类号： H01L23/5256 , H01L21/3065 , H01L21/31116 , H01L21/32053 , H01L2924/0002 , H01L2924/00
摘要： An improved eFuse and method of fabrication is disclosed. A cavity is formed in a substrate, which results in a polysilicon line having an increased depth in the area of the fuse, while having a reduced depth in areas outside of the fuse. The increased depth reduces the chance of the polysilicon line entering the fully silicided state. The cavity may be formed with a wet or dry etch.
摘要翻译：公开了改进的eFuse和制造方法。在衬底中形成腔，这导致多晶硅线在熔丝的面积上具有增加的深度，同时在熔丝外部的区域具有减小的深度。增加的深度降低了多晶硅线路进入完全硅化状态的机会。空腔可以用湿或干蚀刻形成。

2. 发明授权

US08513085B2 Structure and method to improve threshold voltage of MOSFETs including a high k dielectric 有权
标题翻译：提高包括高k电介质的MOSFET的阈值电压的结构和方法
公开(公告)号：US08513085B2
公开(公告)日：2013-08-20
申请号：US13409693
申请日：2012-03-01
申请人： Sunfei Fang , Brian J. Greene , Effendi Leobandung , Qingqing Liang , Edward P. Maciejewski , Yanfeng Wang
发明人： Sunfei Fang , Brian J. Greene , Effendi Leobandung , Qingqing Liang , Edward P. Maciejewski , Yanfeng Wang
IPC分类号： H01L21/8238
CPC分类号： H01L21/823857 , H01L21/28247 , H01L21/823842 , H01L21/823864 , H01L29/517 , H01L29/6659 , H01L29/66636
摘要： Threshold voltage controlled semiconductor structures are provided in which a conformal nitride-containing liner is located on at least exposed sidewalls of a patterned gate dielectric material having a dielectric constant of greater than silicon oxide. The conformal nitride-containing liner is a thin layer that is formed using a low temperature (less than 500° C.) nitridation process.
摘要翻译：提供了阈值电压控制的半导体结构，其中共形含氮化物的衬垫位于具有大于氧化硅的介电常数的图案化栅极电介质材料的至少暴露的侧壁上。含氮氮化物的内衬是使用低温（小于500℃）的氮化工艺形成的薄层。

3. 发明申请

US20110031554A1 STRUCTURE AND METHOD TO IMPROVE THRESHOLD VOLTAGE OF MOSFETS INCLUDING A HIGH K DIELECTRIC 有权
标题翻译：提高包括高K电介质的MOSFET的阈值电压的结构和方法
公开(公告)号：US20110031554A1
公开(公告)日：2011-02-10
申请号：US12535183
申请日：2009-08-04
申请人： Sunfei Fang , Brian J. Greene , Effendi Leobandung , Qingqing Liang , Edward P. Maciejewski , Yanfeng Wang
发明人： Sunfei Fang , Brian J. Greene , Effendi Leobandung , Qingqing Liang , Edward P. Maciejewski , Yanfeng Wang
IPC分类号： H01L27/092 , H01L21/336 , H01L29/78
CPC分类号： H01L21/823857 , H01L21/28247 , H01L21/823842 , H01L21/823864 , H01L29/517 , H01L29/6659 , H01L29/66636
摘要： A method of forming threshold voltage controlled semiconductor structures is provided in which a conformal nitride-containing liner is formed on at least exposed sidewalls of a patterned gate dielectric material having a dielectric constant of greater than silicon oxide. The conformal nitride-containing liner is a thin layer that is formed using a low temperature (less than 500° C.) nitridation process.
摘要翻译：提供了形成阈值电压控制的半导体结构的方法，其中在至少暴露的具有大于氧化硅的介电常数的栅极介电材料的侧壁上形成共形氮化物衬里。含氮氮化物的内衬是使用低温（小于500℃）的氮化工艺形成的薄层。

4. 发明授权

US07504875B2 Methods and apparatus for characterizing electronic fuses used to personalize an integrated circuit 失效
标题翻译：用于表征用于个性化集成电路的电子保险丝的方法和装置
公开(公告)号：US07504875B2
公开(公告)日：2009-03-17
申请号：US11923932
申请日：2007-10-25
申请人： Manjul Bhushan , Mark B. Ketchen , Chandrasekharan Kothandaraman , Edward P. Maciejewski
发明人： Manjul Bhushan , Mark B. Ketchen , Chandrasekharan Kothandaraman , Edward P. Maciejewski
IPC分类号： H01H37/76
CPC分类号： G01R31/31853 , G01R31/30 , G01R31/3004
摘要： An integrated circuit device having at least one fuse capable of being blown in order to provide measurements of fuse current-voltage characteristics is provided. The integrated circuit device also provides at least one pulse generation circuit associated with the fuse and capable of generating a pulse to blow the fuse through one or more DC input signals.
摘要翻译：提供一种具有至少一个能够被熔断以便提供熔丝电流 - 电压特性测量的熔断器的集成电路器件。集成电路装置还提供与熔丝相关联的至少一个脉冲发生电路，并且能够产生脉冲以通过一个或多个DC输入信号来熔断熔丝。

5. 发明授权

US08456169B2 High speed measurement of random variation/yield in integrated circuit device testing 失效
标题翻译：集成电路设备测试中随机变化/产量的高速测量
公开(公告)号：US08456169B2
公开(公告)日：2013-06-04
申请号：US12686476
申请日：2010-01-13
申请人： Manjul Bhushan , Mark B. Ketchen , Qingqing Liang , Edward P. Maciejewski
发明人： Manjul Bhushan , Mark B. Ketchen , Qingqing Liang , Edward P. Maciejewski
IPC分类号： G01R31/02
CPC分类号： G01R31/2856 , G01R31/2894
摘要： A test structure is provided that utilizes a time division sampling technique along with a statistical modeling technique that uses metal-oxide-semiconductor field effect transistor (MOSFET) saturation and linear characteristics to measure the mean (average) and sigma (statistical characterization of the variation) of a large population of electrical characteristics of electrical devices (e.g., integrated circuits) at high speed. Such electrical characteristics or sampling parameters include drive currents, leakage, resistances, etc.
摘要翻译：提供了一种测试结构，其利用时分采样技术以及使用金属氧化物半导体场效应晶体管（MOSFET）饱和度和线性特性的统计建模技术来测量平均值（平均）和σ（变化的统计特征））高速电气设备（如集成电路）的大量电气特性。这种电气特性或采样参数包括驱动电流，泄漏，电阻等

6. 发明申请

US20120168874A1 STRUCTURE AND METHOD TO IMPROVE THRESHOLD VOLTAGE OF MOSFETS INCLUDING A HIGH K DIELECTRIC 有权
标题翻译：提高包括高K电介质的MOSFET的阈值电压的结构和方法
公开(公告)号：US20120168874A1
公开(公告)日：2012-07-05
申请号：US13409693
申请日：2012-03-01
申请人： Sunfei Fang , Brian J. Greene , Effendi Leobandung , Qingqing Liang , Edward P. Maciejewski , Yanfeng Wang
发明人： Sunfei Fang , Brian J. Greene , Effendi Leobandung , Qingqing Liang , Edward P. Maciejewski , Yanfeng Wang
IPC分类号： H01L27/092 , H01L29/78
CPC分类号： H01L21/823857 , H01L21/28247 , H01L21/823842 , H01L21/823864 , H01L29/517 , H01L29/6659 , H01L29/66636
摘要： Threshold voltage controlled semiconductor structures are provided in which a conformal nitride-containing liner is located on at least exposed sidewalls of a patterned gate dielectric material having a dielectric constant of greater than silicon oxide. The conformal nitride-containing liner is a thin layer that is formed using a low temperature (less than 500° C.) nitridation process.
摘要翻译：提供了阈值电压控制的半导体结构，其中共形含氮化物的衬垫位于具有大于氧化硅的介电常数的图案化栅极电介质材料的至少暴露的侧壁上。含氮氮化物的内衬是使用低温（小于500℃）的氮化工艺形成的薄层。

7. 发明授权

US07408421B2 Determining thermal absorption using ring oscillator 有权
标题翻译：使用环形振荡器确定热吸收
公开(公告)号：US07408421B2
公开(公告)日：2008-08-05
申请号：US11428622
申请日：2006-07-05
申请人： Ishtiaq Ahsan , Edward P. Maciejewski , Noah D. Zamdmer
发明人： Ishtiaq Ahsan , Edward P. Maciejewski , Noah D. Zamdmer
IPC分类号： H03B27/00
CPC分类号： H03K3/0315 , G01K7/32
摘要： A device and method for determining a thermal absorption of a part of an integrated circuit (IC) are provided. A specially designed ring oscillator including a non-silicided poly-silicon resistor is used for the determination. The parameters of the ring oscillator are designed/tuned so that a delay of the ring oscillator varies predominantly with a variation in a resistance of the non-silicided poly-silicon resistor. The dimensions of the non-silicided poly-silicon resistor are large enough so that the resistance of the non-silicided poly-silicon resistor is immune to the small process variations of the poly-silicon length and width. The resistance of the non-silicided poly-silicon resistor varies with the thermal absorption of the part of the IC. As such, the thermal absorption of the part of the IC may be determined based on the delay of the ring oscillator.
摘要翻译：提供了一种用于确定集成电路（IC）的一部分的热吸收的装置和方法。使用特殊设计的环形振荡器，其包括非硅化多晶硅电阻器用于测定。环形振荡器的参数被设计/调谐，使得环形振荡器的延迟主要由非硅化多晶硅电阻器的电阻变化而变化。非硅化多晶硅电阻器的尺寸足够大，使得非硅化多晶硅电阻器的电阻不受多硅长度和宽度的小工艺变化的影响。非硅化多晶硅电阻的电阻随着IC部分的热吸收而变化。因此，IC的一部分的热吸收可以基于环形振荡器的延迟来确定。

8. 发明授权

US07396694B2 Structure for monitoring semiconductor polysilicon gate profile 有权
标题翻译：用于监测半导体多晶硅栅极分布的结构
公开(公告)号：US07396694B2
公开(公告)日：2008-07-08
申请号：US11539231
申请日：2006-10-06
申请人： Ishtiaq Ahsan , Edward P. Maciejewski
发明人： Ishtiaq Ahsan , Edward P. Maciejewski
IPC分类号： H01L21/66
CPC分类号： H01L22/34
摘要： Detection of a profile drift of a polysilicon line is enhanced by a test structure that (1) measures a bottom width and an average width of a cross sectional area of the same polysilicon line (2) correlates the two measurements, and (3) compares such correlation with a previous correlation of bottom width to average width of cross sectional area of the same polysilicon line.
摘要翻译：通过测试结构（1）测量相同多晶硅线（2）的横截面积的底部宽度和平均宽度与两个测量值相关联的测试结构来增强多晶硅线的轮廓漂移的检测，并且（3）比较这与以前的相同多晶硅线的横截面积的底宽与平均宽度的相关性的相关性。

9. 发明申请

US20080007354A1 DETERMINING THERMAL ABSORPTION USING RING OSCILLATOR 有权
标题翻译：使用振荡器确定热吸收
公开(公告)号：US20080007354A1
公开(公告)日：2008-01-10
申请号：US11428622
申请日：2006-07-05
申请人： Ishtiaq Ahsan , Edward P. Maciejewski , Noah D. Zamdmer
发明人： Ishtiaq Ahsan , Edward P. Maciejewski , Noah D. Zamdmer
IPC分类号： H03K3/03
CPC分类号： H03K3/0315 , G01K7/32
摘要： A device and method for determining a thermal absorption of a part of an integrated circuit (IC) are provided. A specially designed ring oscillator including an un-silicided poly-silicon resistor is used for the determination. The parameters of the ring oscillator are designed/tuned so that a delay of the ring oscillator varies predominantly with a variation in a resistance of the un-silicided poly-silicon resistor. The dimensions of the un-silicided poly-silicon resistor are large enough so that the resistance of the un-silicided poly-silicon resistor is immune to the small process variations of the poly-silicon length and width. The resistance of the un-silicided poly-silicon resistor varies with the thermal absorption of the part of the IC. As such, the thermal absorption of the part of the IC may be determined based on the delay of the ring oscillator.
摘要翻译：提供了一种用于确定集成电路（IC）的一部分的热吸收的装置和方法。使用特殊设计的环形振荡器，其包括非硅化多晶硅电阻器用于测定。环形振荡器的参数被设计/调谐，使得环形振荡器的延迟主要随着未硅化多晶硅电阻器的电阻的变化而变化。未硅化多晶硅电阻器的尺寸足够大，使得未硅化的多晶硅电阻器的电阻不受多硅长度和宽度的小工艺变化的影响。未硅化的多晶硅电阻器的电阻随着IC部分的热吸收而变化。因此，IC的一部分的热吸收可以基于环形振荡器的延迟来确定。

10. 发明授权

US07135346B2 Structure for monitoring semiconductor polysilicon gate profile 失效
公开(公告)号：US07135346B2
公开(公告)日：2006-11-14
申请号：US10901870
申请日：2004-07-29
申请人： Ishtiaq Ahsan , Edward P. Maciejewski
发明人： Ishtiaq Ahsan , Edward P. Maciejewski
IPC分类号： H01L21/26 , H01L21/66
CPC分类号： H01L22/34
摘要： Detection of a profile drift of a polysilicon line is enhanced by a test structure that (1) measures a bottom width and an average width of a cross sectional area of the same polysilicon line (2) correlates the two measurements, and (3) compares such correlation with a previous correlation of bottom width to average width of cross sectional area of the same polysilicon line.

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