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1. 发明申请

US20180364302A1 SYSTEM AND METHOD FOR ADAPTIVE TESTING OF SEMICONDUCTOR PRODUCT 审中-公开
公开(公告)号：US20180364302A1
公开(公告)日：2018-12-20
申请号：US15623366
申请日：2017-06-14
申请人： Nuvoton Technology Corporation
发明人： Long Chieu
IPC分类号： G01R31/28 , G01R31/317
CPC分类号： G01R31/2894 , G01R31/287 , G01R31/31707 , G01R31/31718
摘要： A method for testing a plurality of electronic devices includes performing tests of up to m devices at a time to measure device parameters on a device tester configured to test up to m devices at a time, where m is an integer. After each test, the method includes performing statistical analysis of the measured device parameters for all tested devices to determine statistical data, including updated mean and standard deviation for each parameter, and storing only the statistical data, and not the measured device parameters. The method further includes determining new pass/fail limits for each device parameter based on the updated mean and standard deviation, and determining pass or fail of each device based on the new pass/fail limits for each device parameter.

2. 发明申请

US20180224499A1 RELIABILITY MANAGEMENT SYSTEM AND OPERATION THEREOF 审中-公开
公开(公告)号：US20180224499A1
公开(公告)日：2018-08-09
申请号：US15888503
申请日：2018-02-05
申请人： Semiconductor Manufacturing International (Beijing) Corporation , Semiconductor Manufacturing International (Shanghai) Corporation
发明人： Gang NIU , Xiaodong ZHAO , Jianshu YU
IPC分类号： G01R31/28 , G01R31/26 , H01L21/67 , H01L21/66
CPC分类号： G01R31/2855 , G01R31/2601 , G01R31/2894 , G05B19/41875 , H01L21/67288 , H01L22/14 , H01L22/20 , Y02P90/30
摘要： A reliability management system and its operation method is presented. The reliability management system comprises instructions stored in a computer-readable non-transitory storage medium, with said instructions executable by one or more hardware processors communicating with the storage medium, the system comprises a reliability manager and a Reliability Test Requestor (RTR). The reliability manager receives a test equipment request from the RTR and sends corresponding test equipment information to the RTR. The RTR sends a test equipment request to the reliability manager based on product information of a test product it receives, and receives test data from a corresponding test equipment according to the test equipment information received from the reliability manager. The RTR also processes the test data to generate a test report, and determines whether the test product passed a reliability test based on the test report. This inventive concept realizes an automatic management on reliability tests.

3. 发明授权

US10018668B2 Kill die subroutine at probe for reducing parametric failing devices at package test 有权
公开(公告)号：US10018668B2
公开(公告)日：2018-07-10
申请号：US15713111
申请日：2017-09-22
申请人： Texas Instruments Incorporated
发明人： Hoi Hin Loo , Soh Ying Seah
IPC分类号： G01R31/28
CPC分类号： G01R31/2851 , G01R31/2853 , G01R31/287 , G01R31/2894
摘要： A method of testing semiconductor devices includes contacting bond pads coupled to integrated circuitry on a first die of a plurality of interconnected die on a substrate using a probe system having probes and probe tests including parametric tests, continuity tests, and a kill die subroutine. Probe tests using the probe program are performed. Die are binned into a first bin (Bin 1 die) for being a good die for all probe tests, or a second bin (Bin 2 die) for failing at least one of continuity tests and parametric tests. The Bin 2 die are divided into a first sub-group that failed the continuity tests and a second sub-group that do not fail the continuity tests. A kill die subroutine is triggered including applying power sufficient to selectively cause damage to the second sub-group of Bin 2 die to generate a continuity failure and thus generate kill die.

4. 发明授权

US09891275B2 Integrated circuit chip reliability qualification using a sample-specific expected fail rate 有权
公开(公告)号：US09891275B2
公开(公告)日：2018-02-13
申请号：US14748704
申请日：2015-06-24
申请人： International Business Machines Corporation
发明人： Jeanne P. Bickford , Nazmul Habib , Baozhen Li , Tad J. Wilder
IPC分类号： G01R31/28 , G05B19/418 , G01R31/26
CPC分类号： G01R31/2894 , G01R31/2642 , G05B19/4188 , G05B2219/45031 , G05B2219/49034 , Y02P90/14 , Y02P90/18
摘要： Disclosed is a method for performing reliability qualification of manufactured integrated circuit (IC) chips. In the method, IC chips are manufactured according to a design and sorted into groups, which correspond to different process windows within a process distribution for the design. Group fail rates are determined for the groups. Reliability qualification of the manufactured IC chips is performed. Specifically, a sample of the IC chips is stress tested and the manufactured IC chips are qualified if the actual fail rate of the sample is no greater than an expected fail rate. The expected fail rate used is not, however, the expected overall fail rate for all the manufactured IC chips. Instead it is a unique expected fail rate for the specific sample itself and it is determined considering fail rate contributions from only those specific groups of IC chips from which the IC chips in the sample were selected.

5. 发明申请

US20180017614A1 Configurable Vertical Integration 审中-公开
公开(公告)号：US20180017614A1
公开(公告)日：2018-01-18
申请号：US15716701
申请日：2017-09-27
申请人： Glenn J Leedy
发明人： Glenn J Leedy
IPC分类号： G01R31/28 , G01R31/3185 , H01L21/66 , G11C29/18 , H01L25/065
CPC分类号： G01R31/2851 , G01R31/2894 , G01R31/2898 , G01R31/318513 , G11C29/18 , H01L22/14 , H01L22/20 , H01L22/22 , H01L25/0657 , H01L2924/0002 , H01L2924/00
摘要： The Configurable Vertical Integration [CVI] invention pertains to methods and apparatus for the enhancement of yields of 3D or stacked integrated circuits and herein referred to as a CVI Integrated Circuit [CVI IC]. The CVI methods require no testing of circuit layer components prior to their fabrication as part of a 3D integrated circuit. The CVI invention uses active circuitry to configure the CVI IC as a means to isolate or prevent the use of defective circuitry. CVI circuit configuration method can be predominately described as a large grain method.

6. 发明授权

US09797993B2 Advance manufacturing monitoring and diagnostic tool 有权
公开(公告)号：US09797993B2
公开(公告)日：2017-10-24
申请号：US14141653
申请日：2013-12-27
申请人： Gerald W. Pauly , Walter J. Keller, III
发明人： Gerald W. Pauly , Walter J. Keller, III
IPC分类号： G01S7/41 , G01R31/01 , G01R31/26 , G01R31/317 , G01R29/08 , G01R31/28 , G01R31/265 , G01R31/302
CPC分类号： G01S7/41 , G01R29/0871 , G01R31/01 , G01R31/26 , G01R31/2642 , G01R31/265 , G01R31/2851 , G01R31/2894 , G01R31/302 , G01R31/31703
摘要： A device and a method for monitoring and analysis utilize unintended electromagnetic emissions of electrically powered components, devices or systems. The emissions are received at the antenna and a receiver. A processor processes and measures change or changes in a signature of the unintended electromagnetic emissions. The measurement are analyzed to both record a baseline score for future measurements and to be used in determining status and/or health of the analyzed system or component.

7. 发明授权

US09759767B2 Pre-test power-optimized bin reassignment following selective voltage binning 有权
公开(公告)号：US09759767B2
公开(公告)日：2017-09-12
申请号：US14695112
申请日：2015-04-24
申请人： GLOBALFOUNDRIES INC.
发明人： Igor Arsovski , Jeanne P. Bickford , Paul J. Grzymkowski , Susan K. Lichtensteiger , Robert J. McMahon , Troy J. Perry , David M. Picozzi , Thomas G. Sopchak
IPC分类号： G01R31/00 , G01R31/28 , G01R21/133 , G06F17/50 , G01R31/317
CPC分类号： G01R31/2894 , G01R21/133 , G01R31/31718 , G06F17/5045 , G06F2217/78
摘要： Disclosed is a method wherein selective voltage binning and leakage power screening of integrated circuit (IC) chips are performed. Additionally, pre-test power-optimized bin reassignments are made on a chip-by-chip basis. Specifically, a leakage power measurement of an IC chip selected from a voltage bin can is compared to a bin-specific leakage power screen value of the next slower voltage bin. If the leakage power measurement is higher, the IC chip will be left in the voltage bin to which it is currently assigned. If the leakage power measurement is lower, the IC chip will be reassigned to that next slower voltage bin. These processes can be iteratively repeated until no slower voltage bins are available or the IC chip cannot be reassigned. IC chips can subsequently be tested according to testing parameters, including the minimum test voltages, associated with the voltage bins to which they are finally assigned.

8. 发明授权

US09625524B2 Efficient method of retesting integrated circuits 有权
公开(公告)号：US09625524B2
公开(公告)日：2017-04-18
申请号：US14837402
申请日：2015-08-27
申请人： International Business Machines Corporation
发明人： Teck Seng Eng , Michael Russell Uy Gonzales , Louie Que Hermosura
IPC分类号： G01R31/317 , G01R31/28 , G01R31/3177
CPC分类号： G01R31/3177 , G01R31/2832 , G01R31/2894 , G01R31/31718
摘要： Efficient production testing of integrated circuits. A first production test is implemented on a group of integrated circuits and failures among the test group are assessed. Specifically, the results of the first test are analyzed such that integrated circuits having a recoverable fail and integrated circuits having a non-recoverable fail are differentiated. The integrated circuits are integrated based on the analyzed results and a second production test is implemented. The second production test tests the integrated circuits responsive to the segregation, such that the second production test is limited only to integrated circuits with a recoverable fail. The next succeeding production test will then use the new test program in the second production test with the handler bin designated as having integrated circuits not to be re-tested.

9. 发明授权

US09618575B2 Semiconductor device having plural data input/output terminals configured for write test and read test operations 有权
公开(公告)号：US09618575B2
公开(公告)日：2017-04-11
申请号：US13828711
申请日：2013-03-14
申请人： PS4 Luxco S.a.r.l.
发明人： Teppei Miyaji , Yoshinori Matsui
IPC分类号： G11C29/32 , G11C11/401 , G01R31/28 , G11C7/10 , G11C29/00 , G11C29/12 , G11C29/56
CPC分类号： G01R31/2894 , G11C7/10 , G11C11/401 , G11C29/006 , G11C29/1201 , G11C29/32 , G11C2029/5602
摘要： Disclosed herein is a device that includes a plurality of first terminals; a first circuit including a plurality of first nodes; a buffer circuit including a plurality of second nodes connected to the first terminals through a plurality of first interconnection lines, respectively, and a plurality of third nodes connected to the first nodes of the first circuit through a plurality of second interconnection lines, respectively; and a second circuit configured to perform at least one of first and second operations. The first operation is such that a plurality of first signals, that appear respectively on the first interconnection lines, are outputted in series, and the second operation is such that a plurality of second signals, that are supplied in series, are transferred respectively to the first interconnection lines.

10. 发明申请

US20170003340A1 NON-INVASIVE PRE-BOND TSV USING RING OSCILLATORS AND MULTIPLE VOLTAGE LEVELS 审中-公开
标题翻译：使用环形振荡器和多个电压等级的非入门式前缀TSV
公开(公告)号：US20170003340A1
公开(公告)日：2017-01-05
申请号：US15266744
申请日：2016-09-15
申请人： DUKE UNIVERSITY
发明人： KRISHNENDU CHAKRABARTY , SERGEJ DEUTSCH
IPC分类号： G01R31/28
CPC分类号： G01R31/2853 , G01R31/2601 , G01R31/2894 , G01R31/318558
摘要： A design for test (DfT) architecture is provided that enables pre-bond parametric testing of through-silicon vias (TSVs). A grouping of N number of input/output (I/O) segments are configured to receive a test signal in a feedback loop, where each I/O segment includes one or more buffers (or inverters) and a TSV connected at one end to the one or more buffers. The TSV acts as a shunt-connected capacitor—when defect free—and includes a load resistance when the TSV contains a defect. Each I/O segment can also include one or two multiplexers to control whether the I/O segment receives a test or functional signal and, optionally, whether the I/O segment is bypassed or included in the ring oscillator. The varying loads caused by the defects cause variations in the delay across the buffers (or inverters) of an I/O segment that can be detected in the output signal.
摘要翻译：提供了一种用于测试（DfT）架构的设计，可以实现通硅通孔（TSV）的预键参数测试。 N个输入/输出（I / O）段的分组被配置为在反馈回路中接收测试信号，其中每个I / O段包括一个或多个缓冲器（或反相器）和一端连接到一个TSV 一个或多个缓冲区。当TSV包含缺陷时，TSV充当分流连接的电容器 - 当缺陷自由时包含负载电阻。每个I / O段还可以包括一个或两个多路复用器，以控制I / O段是否接收到测试或功能信号，以及可选地，该I / O段是否被绕过或包含在环形振荡器中。由缺陷引起的变化的负载导致可在输出信号中检测到的I / O段的缓冲器（或反相器）之间的延迟变化。

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