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1. 发明申请

US20230047371A1 PICKLEBALL PADDLE 有权
公开(公告)号：US20230047371A1
公开(公告)日：2023-02-16
申请号：US17975620
申请日：2022-10-28
申请人： Feng-Yu Lee
发明人： Feng-Yu Lee
IPC分类号： A63B59/42 , A63B60/00
摘要： A pickleball paddle includes a paddle body and a handle connected to the paddle body. The paddle body has at least one hollow cylindrical space therein. An angle is formed between an axis of the hollow cylindrical space and front and back face-plates of the paddle body. The hollow cylindrical space has an axial length and a radial length. The axial length is greater than the radial length. At least one rolling member that can roll back and forth along an axial direction of the hollow cylindrical space is disposed in the hollow cylindrical space. The pickleball paddle can enhance an explosive force for hitting a ball.

2. 发明申请

US20210252357A1 PICKLEBALL PADDLE 有权
公开(公告)号：US20210252357A1
公开(公告)日：2021-08-19
申请号：US17306958
申请日：2021-05-04
申请人： Feng-Yu Lee
发明人： Feng-Yu Lee
IPC分类号： A63B59/42 , A63B60/54
摘要： A pickleball paddle includes a paddle body and a handle. The paddle body includes a substrate and two face plates on front and rear sides thereof. An elastic member is provided between the substrate and each of the two face plates. The elastic member between the substrate and the face plate is configured to reduce the reaction force generated by the ball hitting the face plate and prolong the time that the ball stays on the face plate. The user can control the trajectory of the ball better. It enhances entertainment fun.

3. 发明申请

US20130157459A1 METHOD FOR FABRICATING INTERCONNECTING LINES INSIDE VIA HOLES OF SEMICONDUCTOR DEVICE 有权
标题翻译：用于在半导体器件的内部制造互连线的方法
公开(公告)号：US20130157459A1
公开(公告)日：2013-06-20
申请号：US13416627
申请日：2012-03-09
申请人： Wei-leun FANG , Chia Han Lin , Feng Yu Lee
发明人： Wei-leun FANG , Chia Han Lin , Feng Yu Lee
IPC分类号： H01L21/768
CPC分类号： H01L21/76898
摘要： A method for fabricating interconnecting lines inside via holes of a semiconductor device comprises steps of providing a template having a receiving trench and a connection surface both on the same side of the template; filling an electric-conduction material into the receiving trench; connecting a substrate having at least one via hole with the connection surface to interconnect the via hole with the receiving trench; heating the electric-conduction material to a working temperature to liquefy a portion of the electric-conduction material and make it flows from the receiving trench into the via hole; and cooling the electric-conduction material to form an interconnecting line inside the via hole. The present invention fabricates interconnecting lines by a heat-forming method, which features simple steps and has advantages of shorter fabrication time, lower fabrication complexity, higher fabrication efficiency, higher yield and lower fabrication cost.
摘要翻译：一种用于在半导体器件的通孔内部制造互连线的方法包括以下步骤：在模板的同一侧提供具有接收沟槽和连接表面的模板; 将导电材料填充到所述接收沟槽中; 将具有至少一个通孔的基板与所述连接表面连接，以将所述通孔与所述接收沟槽相互连接; 将导电材料加热到工作温度以液化导电材料的一部分并使其从接收槽流入通孔; 并且冷却所述导电材料以在所述通孔内部形成互连线。本发明通过热成型方法制造互连线，其特征在于简单的步骤，并且具有制造时间缩短，制造复杂性更低，制造效率更高，成品率更高，制造成本更低的优点。

4. 发明授权

US08780958B2 Hybrid bit extraction for global position receiver 失效
标题翻译：全局位置接收机的混合位提取
公开(公告)号：US08780958B2
公开(公告)日：2014-07-15
申请号：US12870577
申请日：2010-08-27
申请人： Haojen Cheng , Feng-Yu Lee , Qinfang Sun
发明人： Haojen Cheng , Feng-Yu Lee , Qinfang Sun
IPC分类号： H04B1/00
CPC分类号： G01S19/243
摘要： A hybrid bit detection circuit for receiving bits from different global positioning systems, e.g. GPS and GLONASS, can include a frequency lock loop (FLL) for receiving the global positioning bits and removing Doppler frequency error and an integrate and dump (I&D) block coupled to an output of the FLL. A coherent detection circuit can be coupled to an output of the FLL and an output of the integrated and dump block. A differential detection circuit can be coupled to an output of the I&D block. Two parity check blocks can be coupled to outputs of the coherent and differential detection circuits.
摘要翻译：一种用于从不同的全球定位系统接收比特的混合比特检测电路， GPS和GLONASS可以包括用于接收全球定位位和消除多普勒频率误差的频率锁定环（FLL），以及耦合到FLL的输出的积分和转储（I＆D）块。相干检测电路可以耦合到FLL的输出和集成和转储块的输出。差分检测电路可以耦合到I＆D块的输出。两个奇偶校验块可以耦合到相干和差分检测电路的输出。

5. 发明授权

US08679974B2 Method for fabricating interconnecting lines inside via holes of semiconductor device 有权
标题翻译：在半导体器件的通孔内部形成互连线的方法
公开(公告)号：US08679974B2
公开(公告)日：2014-03-25
申请号：US13416627
申请日：2012-03-09
申请人： Wei-leun Fang , Chia Han Lin , Feng Yu Lee
发明人： Wei-leun Fang , Chia Han Lin , Feng Yu Lee
IPC分类号： H01L21/44
CPC分类号： H01L21/76898
摘要： A method for fabricating interconnecting lines inside via holes of a semiconductor device comprises steps of providing a template having a receiving trench and a connection surface both on the same side of the template; filling an electric-conduction material into the receiving trench; connecting a substrate having at least one via hole with the connection surface to interconnect the via hole with the receiving trench; heating the electric-conduction material to a working temperature to liquefy a portion of the electric-conduction material and make it flows from the receiving trench into the via hole; and cooling the electric-conduction material to form an interconnecting line inside the via hole. The present invention fabricates interconnecting lines by a heat-forming method, which features simple steps and has advantages of shorter fabrication time, lower fabrication complexity, higher fabrication efficiency, higher yield and lower fabrication cost.
摘要翻译：一种用于在半导体器件的通孔内部制造互连线的方法包括以下步骤：在模板的同一侧提供具有接收沟槽和连接表面的模板; 将导电材料填充到所述接收沟槽中; 将具有至少一个通孔的基板与所述连接表面连接，以将所述通孔与所述接收沟槽相互连接; 将导电材料加热到工作温度以液化导电材料的一部分并使其从接收槽流入通孔; 并且冷却所述导电材料以在所述通孔内部形成互连线。本发明通过热成型方法制造互连线，其特征在于简单的步骤，并且具有制造时间缩短，制造复杂性更低，制造效率更高，成品率更高，制造成本更低的优点。

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