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1. 发明授权

US08780958B2 Hybrid bit extraction for global position receiver 失效
标题翻译：全局位置接收机的混合位提取
公开(公告)号：US08780958B2
公开(公告)日：2014-07-15
申请号：US12870577
申请日：2010-08-27
申请人： Haojen Cheng , Feng-Yu Lee , Qinfang Sun
发明人： Haojen Cheng , Feng-Yu Lee , Qinfang Sun
IPC分类号： H04B1/00
CPC分类号： G01S19/243
摘要： A hybrid bit detection circuit for receiving bits from different global positioning systems, e.g. GPS and GLONASS, can include a frequency lock loop (FLL) for receiving the global positioning bits and removing Doppler frequency error and an integrate and dump (I&D) block coupled to an output of the FLL. A coherent detection circuit can be coupled to an output of the FLL and an output of the integrated and dump block. A differential detection circuit can be coupled to an output of the I&D block. Two parity check blocks can be coupled to outputs of the coherent and differential detection circuits.
摘要翻译：一种用于从不同的全球定位系统接收比特的混合比特检测电路， GPS和GLONASS可以包括用于接收全球定位位和消除多普勒频率误差的频率锁定环（FLL），以及耦合到FLL的输出的积分和转储（I＆D）块。相干检测电路可以耦合到FLL的输出和集成和转储块的输出。差分检测电路可以耦合到I＆D块的输出。两个奇偶校验块可以耦合到相干和差分检测电路的输出。

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