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1. 发明授权

US07966432B2 Data processing device adaptable to variable external memory size and endianess 有权
标题翻译：数据处理设备适应可变外部存储器大小和端性
公开(公告)号：US07966432B2
公开(公告)日：2011-06-21
申请号：US11572909
申请日：2005-07-19
申请人： Patrick Fulcheri , Francois Chancel
发明人： Patrick Fulcheri , Francois Chancel
IPC分类号： G06F3/00 , G06F12/00
CPC分类号： G06F13/4013 , G06F13/4018
摘要： A data processing device (D) comprises an external memory (EM) for storing data defining at least part of a program in an Endian form, and an integrated circuit (IC), connected to the external memory (EM), via a memory bus (MB) having an N-bit width, and comprising i) an embedded processor (EP) adapted to run the program, ii) an internal memory (IM) for storing at least a bootstrap code of this program, iii) an external memory interface (EMI) connected to the memory bus (MB), and iv) a processor bus (PB) connecting the internal memory (IM) and the external memory interface (EMI) to the embedded processor (EP). The external memory (EM) also stores, at a chosen address, an N-bit data word (C) having a value representative of its size (equal to N/8 bits) and of the Endian form of the stored program data. The data processing device (D) also comprises a configuration means (CM) coupled to the embedded processor (EP) and to the external memory interface (EMI) and arranged to deduce from at least one part of 8 bits of this N-bit data word (C), read by the external memory interface at the chosen address of the external memory (EM), the size and the Endian form of storage of the external memory, and to set the width of the external memory interface (EMI) according to the deduced external memory size and the data processing mode of the embedded processor (EP) according to the deduced Endian form of storage.
摘要翻译：数据处理装置（D）包括外部存储器（EM），用于存储以端部形式定义程序的至少一部分的数据，以及通过存储器总线连接到外部存储器（EM）的集成电路（IC）（MB），并且包括i）适于运行该程序的嵌入式处理器（EP），ii）用于存储该程序的至少一个引导代码的内部存储器（IM），iii）外部存储器接口（EMI）连接到存储器总线（MB），以及iv）将内部存储器（IM）和外部存储器接口（EMI）连接到嵌入式处理器（EP）的处理器总线（PB）。外部存储器（EM）还在所选择的地址处存储具有表示其大小（等于N / 8位）的值的N位数据字（C）和所存储的节目数据的尾数形式。数据处理设备（D）还包括耦合到嵌入式处理器（EP）和外部存储器接口（EMI）的配置装置（CM），并且被配置为从该N位数据的8位的至少一部分推导出字（C），由外部存储器接口在外部存储器（EM）的选定地址读取，外部存储器的大小和端部存储形式，以及根据外部存储器接口（EMI）的宽度设置根据推断的Endian形式的存储器，推断出嵌入式处理器（EP）的外部存储器尺寸和数据处理模式。

2. 发明授权

US08635382B2 Processing architecture 有权
标题翻译：处理架构
公开(公告)号：US08635382B2
公开(公告)日：2014-01-21
申请号：US12747474
申请日：2008-12-11
申请人： Francois Chancel , Jean-Marc Grimaud
发明人： Francois Chancel , Jean-Marc Grimaud
IPC分类号： G06F3/00 , G06F13/28 , G06F5/00
CPC分类号： G06F15/7842 , G06F1/3203 , G06F1/3293 , G06F9/544 , Y02D10/122
摘要： The invention is directed towards a processing apparatus for a portable communication device. The apparatus includes: a central processing unit, first and second digital signal processing units, a first dual port memory unit adapted to store data shared between the central processing unit and the first digital signal processing unit, and a second dual port memory unit adapted to store data shared between the central processing unit and the second digital signal processing unit. The first dual port memory unit is adapted to store data shared between the first and second digital signal processing units without using the central processing unit.
摘要翻译：本发明涉及一种用于便携式通信设备的处理设备。该装置包括：中央处理单元，第一和第二数字信号处理单元，适于存储在中央处理单元和第一数字信号处理单元之间共享的数据的第一双端口存储单元，以及适于存储在中央处理单元和第二数字信号处理单元之间共享的数据。第一双端口存储器单元适于在不使用中央处理单元的情况下存储在第一和第二数字信号处理单元之间共享的数据。

3. 发明申请

US20090119438A1 Data Processing Device Adaptable to Variable External Memory Size and Endianess 有权
标题翻译：数据处理设备可适应变量外部存储器大小和端点
公开(公告)号：US20090119438A1
公开(公告)日：2009-05-07
申请号：US11572909
申请日：2005-07-19
申请人： Patrick Fulcheri , Francois Chancel
发明人： Patrick Fulcheri , Francois Chancel
IPC分类号： G06F13/16 , G06F13/40 , G06F12/06
CPC分类号： G06F13/4013 , G06F13/4018
摘要： A data processing device (D) comprises an external memory (EM) for storing data defining at least part of a program in an Endian form, and an integrated circuit (IC), connected to the external memory (EM), via a memory bus (MB) having an N-bit width, and comprising i) an embedded processor (EP) adapted to run the program, ii) an internal memory (IM) for storing at least a bootstrap code of this program, iii) an external memory interface (EMI) connected to the memory bus (MB), and iv) a processor bus (PB) connecting the internal memory (IM) and the external memory interface (EMI) to the embedded processor (EP). The external memory (EM) also stores, at a chosen address, an N-bit data word (C) having a value representative of its size (equal to N/8 bits) and of the Endian form of the stored program data. The data processing device (D) also comprises a configuration means (CM) coupled to the embedded processor (EP) and to the external memory interface (EMI) and arranged to deduce from at least one part of 8 bits of this N-bit data word (C), read by the external memory interface at the chosen address of the external memory (EM), the size and the Endian form of storage of the external memory, and to set the width of the external memory interface (EMI) according to the deduced external memory size and the data processing mode of the embedded processor (EP) according to the deduced Endian form of storage.
摘要翻译：数据处理装置（D）包括外部存储器（EM），用于存储以端部形式定义程序的至少一部分的数据，以及通过存储器总线连接到外部存储器（EM）的集成电路（IC）（MB），其包括i）适于运行该程序的嵌入式处理器（EP），ii）用于存储该程序的至少一个引导代码的内部存储器（IM），iii）外部存储器接口（EMI）连接到存储器总线（MB），以及iv）将内部存储器（IM）和外部存储器接口（EMI）连接到嵌入式处理器（EP）的处理器总线（PB）。外部存储器（EM）还在所选择的地址处存储具有表示其大小（等于N / 8位）的值的N位数据字（C）和所存储的节目数据的尾数形式。数据处理设备（D）还包括耦合到嵌入式处理器（EP）和外部存储器接口（EMI）的配置装置（CM），并且被配置为从该N位数据的8位的至少一部分推导出字（C），由外部存储器接口在外部存储器（EM）的选定地址读取，外部存储器的大小和端部存储形式，以及根据外部存储器接口（EMI）的宽度设置根据推断的Endian形式的存储器，推断出嵌入式处理器（EP）的外部存储器尺寸和数据处理模式。

4. 发明申请

US20070165560A1 Baseband processor and a method of transmitting commands to a radio-frequency subsystem and radio telecommunication apparatus incorporating the baseband processor 有权
标题翻译：基带处理器以及将命令发送到并入基带处理器的射频子系统和无线电电信设备的方法
公开(公告)号：US20070165560A1
公开(公告)日：2007-07-19
申请号：US10591544
申请日：2005-02-21
申请人： Jean-Claude Bini , Francois Chancel
发明人： Jean-Claude Bini , Francois Chancel
IPC分类号： H04Q7/00
CPC分类号： H04B7/2687
摘要： The baseband processor (18) comprises: a storage unit (72) storing: a descriptor table comprising for each descriptor: a pointer field designed to point to a definition of an operation, an absolute operation time field indicating at which time from the beginning of a frame processing the corresponding operation should be carried out, an operation definition table comprising for each operation a definition of the operation, each definition having a sequence of events, each event of the definition table being associated with a relative event time field indicating at which time from the beginning of the operation the corresponding event should be executed, and a calculator (70) to automatically compute a list of events from the description and operation tables.
摘要翻译：基带处理器（18）包括：存储单元（72），存储：描述符表，其包括用于每个描述符的：指定操作定义的指针字段，表示从应执行处理相应操作的帧，操作定义表包括每个操作的操作定义，每个定义具有事件序列，定义表的每个事件与相对事件时间字段相关联，相对事件时间字段指示在哪个从操作开始起的时间应该执行相应的事件;以及计算器（70），用于根据描述和操作表自动计算事件列表。

5. 发明授权

US07890736B2 Control device with flag registers for synchronization of communications between cores 有权
标题翻译：具有标志寄存器的控制设备，用于核心之间的通信同步
公开(公告)号：US07890736B2
公开(公告)日：2011-02-15
申请号：US12092615
申请日：2006-11-03
申请人： Francois Chancel , Patrick Fulcheri
发明人： Francois Chancel , Patrick Fulcheri
IPC分类号： G06F7/38 , G06F9/00 , G06F9/44 , G06F15/00
CPC分类号： G06F15/167
摘要： A control device (D) is a part of an integrated circuit (IC) comprising at least two cores (C1, C2) coupled, via buses (BC1, BC2), to a memory (M) arranged to store data to be transferred between these cores (C1, C2). This control device (D) comprises at least one flag register (FR1, FR2) coupled to the cores (C1, C2) via the buses (BC1, BC2) and arranged to store, at Ni addresses, Ni flag values associated to data stored into the memory (M) by one of the cores and ready to be transferred towards the other core, each flag value stored at a first address being able to be set or reset by one of the cores (C1, C2) by means of a command designating the first address, thus authorizing another flag value stored at a second address to be simultaneously set or reset by the other core (C2, C1) by means of a command designating the second address.
摘要翻译：控制装置（D）是集成电路（IC）的一部分，其包括经由总线（BC1，BC2）耦合到存储器（M）的至少两个磁芯（C1，C2），存储器（M）被布置为存储要在这些芯（C1，C2）。该控制装置（D）包括经由总线（BC1，BC2）耦合到核心（C1，C2）的至少一个标志寄存器（FR1，FR2），并且被布置为在Ni地址处存储与存储的数据相关联的Ni标志值通过其中一个核心进入存储器（M）并且准备向另一个核心转移，存储在第一地址处的每个标志值能够由一个核心（C1，C2）通过一个核心（C1，C2）设置或复位指定第一地址的命令，从而授权存储在第二地址处的另一个标志值由另一个核心（C2，C1）通过指定第二地址的命令同时设置或复位。

6. 发明申请

US20080294876A1 Control Device with Flag Registers for Synchronization of Communications Between Cores 有权
标题翻译：具有标志寄存器的控制装置，用于同步核心之间的通信
公开(公告)号：US20080294876A1
公开(公告)日：2008-11-27
申请号：US12092615
申请日：2006-11-03
申请人： Francois Chancel , Patrick Fulcheri
发明人： Francois Chancel , Patrick Fulcheri
IPC分类号： G06F15/76 , G06F9/30
CPC分类号： G06F15/167
摘要： A control device (D) is a part of an integrated circuit (IC) comprising at least two cores (C1,C2) coupled, via buses (BC1, BC2), to a memory (M) arranged to store data to be transferred between these cores (C1, C2). This control device (D) comprises at least one flag register (FR1, FR2) coupled to the cores (C1,C2) via the buses (BC1, BC2) and arranged to store, at Ni addresses, Ni flag values associated to data stored into the memory (M) by one of the cores and ready to be transferred towards the other core, each flag value stored at a first address being able to be set or reset by one of the cores (C1, C2) by means of a command designating the first address, thus authorizing another flag value stored at a second address to be simultaneously set or reset by the other core (C2,C1) by means of a command designating the second address.
摘要翻译：控制装置（D）是集成电路（IC）的一部分，其包括经由总线（BC1，BC2）耦合到存储器（M）的至少两个磁芯（C1，C2），存储器（M）被布置为存储要在这些芯（C1，C2）。该控制装置（D）包括经由总线（BC1，BC2）耦合到核心（C1，C2）的至少一个标志寄存器（FR1，FR2），并且被布置为在Ni地址处存储与存储的数据相关联的Ni标志值通过其中一个核心进入存储器（M）并且准备向另一个核心转移，存储在第一地址处的每个标志值能够由一个核心（C1，C2）通过一个核心（C1，C2）设置或复位指定第一地址的命令，从而授权存储在第二地址处的另一个标志值由另一个核心（C2，C1）通过指定第二地址的命令同时设置或复位。

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