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1. 发明申请

US20220037519A1 TRANSISTOR STRUCTURES AND ASSOCIATED PROCESSES 有权
公开(公告)号：US20220037519A1
公开(公告)日：2022-02-03
申请号：US17389241
申请日：2021-07-29
申请人： Fu-Chang Hsu
发明人： Fu-Chang Hsu
IPC分类号： H01L29/78 , H01L29/08 , H01L29/06
摘要： Transistor structures and associated processes are disclosed. In an exemplary embodiment, a transistor structure is provided that includes a conductor layer divided into a plurality of separate conductor regions and a plurality of lateral transistors formed on top of the plurality of separate conductor regions, respectively. Each lateral transistor comprises a source, a drain, and a gate region, and at least one of the source, drain, and gate regions of each lateral transistor is conductively coupled underneath to its respective conductor region.

2. 发明申请

US20210296556A1 QUANTUM BIT ARRAY 有权
公开(公告)号：US20210296556A1
公开(公告)日：2021-09-23
申请号：US17209107
申请日：2021-03-22
申请人： Fu-Chang Hsu , Kevin Hsu
发明人： Fu-Chang Hsu , Kevin Hsu
IPC分类号： H01L39/22 , H01L27/18 , H03K3/38 , G06N10/00
摘要： A quantum bit array is disclosed. In an embodiment, the quantum bit array includes a control gate coupled to a qubit and at least one pass gate coupled between the qubit and an adjacent qubit to control operation of the qubit of the quantum bit array, a bit line, and a first transistor channel that connects the bit line to the control gate. The array further comprises at least one word line coupled to the first transistor channel. The at least one word line selectively controls charge flow through the first transistor channel. The array further comprises a capacitor coupled to selectively store charge in the first transistor channel.

3. 发明申请

US20190108437A1 TWO AND THREE-DIMENSIONAL NEURAL NETWORK ARRAYS 审中-公开
公开(公告)号：US20190108437A1
公开(公告)日：2019-04-11
申请号：US16006730
申请日：2018-06-12
申请人： Fu-Chang Hsu , Kevin Hsu
发明人： Fu-Chang Hsu , Kevin Hsu
IPC分类号： G06N3/063 , G06N3/04
摘要： Two and three-dimensional neural network arrays. In an exemplary embodiment, a two-dimensional (2D) neural network array includes a plurality of input neurons connected to a plurality of input lines, and a plurality of output neurons connected to a plurality of output lines. The 2D neural network array also includes synapse elements connected between the input lines and the output lines. Each synapse element includes a programmable resistive element. A three-dimensional (3D) neural network array includes a plurality of stacked two-dimensional (2D) neural network arrays each having a plurality of input neurons connected to a plurality of input layers and a plurality of output neurons connected to a plurality of output layers. The output layers intersect with the input layers and include synapse elements formed between intersecting regions of the input layers and the output layers. Each synapse element includes a programmable resistive element.

4. 发明申请

US20180165573A1 THREE-DIMENSIONAL NEURAL NETWORK ARRAY 审中-公开
公开(公告)号：US20180165573A1
公开(公告)日：2018-06-14
申请号：US15835375
申请日：2017-12-07
申请人： Fu-Chang Hsu , Kevin Hsu
发明人： Fu-Chang Hsu , Kevin Hsu
IPC分类号： G06N3/063 , G06N3/04
CPC分类号： G06N3/063 , G06N3/04 , G06N3/0454
摘要： Three-dimensional neural network array. In an exemplary embodiment, a three-dimensional (3D) neural network includes a plurality of input conductors forming a plurality of stacked input layers having a first orientation, and at least one output conductor forming an output layer having the first orientation. The three-dimensional (3D) neural network also includes a plurality of hidden conductors having a second orientation. Each hidden conductor includes an in-line threshold element. The three-dimensional (3D) neural network also includes synapse elements coupled between the hidden conductors and the input conductors and between the hidden conductors and the output conductor. Each synapse element includes a programmable resistive element.

5. 发明申请

US20170148812A1 METHODS AND APPARATUS FOR A 3D ARRAY INSIDE A SUBSTRATE TRENCH 审中-公开
公开(公告)号：US20170148812A1
公开(公告)日：2017-05-25
申请号：US15355733
申请日：2016-11-18
申请人： Fu-Chang Hsu
发明人： Fu-Chang Hsu
IPC分类号： H01L27/115 , H01L21/768 , H01L21/306 , H01L23/528
CPC分类号： H01L27/11582 , H01L21/30604 , H01L21/743 , H01L21/76877 , H01L23/528 , H01L23/535 , H01L27/11568 , H01L27/11573 , H01L27/11575
摘要： A 3D array inside a substrate trench. In one aspect, an apparatus includes a substrate, a trench region in the substrate that is defined by a trench wall, and a 3D array having stacked word line layers formed in the trench region that follow a contour of the trench wall. In one aspect, a method includes forming a trench region in a substrate that has a top surface, the trench region is defined by a trench wall, and forming a 3D array having stacked word line layers in the trench region so that the stacked word line layers follow a contour of the trench wall and have exposed ends substantially at a level of the top surface.

6. 发明授权

US09063849B2 Different types of memory integrated in one chip by using a novel protocol 有权
标题翻译：通过使用新颖的协议集成在一个芯片中的不同类型的存储器
公开(公告)号：US09063849B2
公开(公告)日：2015-06-23
申请号：US13200141
申请日：2011-09-19
申请人： Peter Wung Lee , Fu-Chang Hsu
发明人： Peter Wung Lee , Fu-Chang Hsu
IPC分类号： G06F12/00 , H05K3/00 , G06F12/06 , G06F12/02 , G11C5/06 , G11C7/10 , G11C11/00 , G11C16/32
CPC分类号： G06F12/0638 , G06F12/0246 , G06F2212/7208 , G11C5/066 , G11C7/10 , G11C7/1006 , G11C7/1039 , G11C7/1045 , G11C11/005 , G11C16/32 , G11C2216/30 , Y02D10/13 , Y10T29/49124
摘要： A semiconductor chip contains four different memory types, EEPROM, NAND Flash, NOR Flash and SRAM, and a plurality of major serial/parallel interfaces such as I2C, SPI, SDI and SQI in one memory chip. The memory chip features write-while-write and read-while-write operations as well as read-while-transfer and write-while-transfer operations. The memory chip provides for eight pins of which two are for power and up to four pins have no connection for specific interfaces and uses a novel unified nonvolatile memory design that allow the integration together of the aforementioned memory types integrated together into the same semiconductor memory chip.
摘要翻译：半导体芯片在一个存储器芯片中包含四种不同的存储器类型，EEPROM，NAND闪存，NOR闪存和SRAM以及多个主要的串行/并行接口，例如I2C，SPI，SDI和SQI。内存芯片具有写时同时写入和读写操作以及读写同时传输和写时同时传输操作。存储器芯片提供八个引脚，其中两个用于供电，最多四个引脚没有连接用于特定接口，并且使用新颖的统一的非易失性存储器设计，允许集成在一起的上述存储器类型集成在同一半导体存储器芯片。

7. 发明授权

US08773903B2 High speed high density nand-based 2T-NOR flash memory design 失效
标题翻译：高速高密度基于nand的2T-NOR闪存设计
公开(公告)号：US08773903B2
公开(公告)日：2014-07-08
申请号：US13535681
申请日：2012-06-28
申请人： Peter Wung Lee , Fu-Chang Hsu
发明人： Peter Wung Lee , Fu-Chang Hsu
IPC分类号： G11C16/10
CPC分类号： G11C16/10 , G11C16/0425 , H01L27/11519 , H01L27/11521
摘要： A two transistor NOR flash memory cell has symmetrical source and drain structure manufactured by a NAND-based manufacturing process. The flash cell comprises a storage transistor made of a double-poly NMOS floating gate transistor and an access transistor made of a double-poly NMOS floating gate transistor, a poly1 NMOS transistor with poly1 and poly2 being shorted or a single-poly poly1 or poly2 NMOS transistor. The flash cell is programmed and erased by using a Fowler-Nordheim channel tunneling scheme. A NAND-based flash memory device includes an array of the flash cells arranged with parallel bit lines and source lines that are perpendicular to word lines. Write-row-decoder and read-row-decoder are designed for the flash memory device to provide appropriate voltages for the flash memory array in pre-program with verify, erase with verify, program and read operations in the unit of page, block, sector or chip.
摘要翻译：双晶体管NOR闪存单元具有由基于NAND的制造工艺制造的对称的源极和漏极结构。闪存单元包括由双多晶硅NMOS浮栅晶体管构成的存储晶体管和由双多晶硅NMOS浮栅晶体管构成的存取晶体管，poly1和poly2短路的poly1NMOS晶体管或单聚poly1或poly2 NMOS晶体管。使用Fowler-Nordheim通道隧道方案对闪存单元进行编程和擦除。基于NAND的闪速存储器件包括与并行位线排列的闪存单元的阵列和垂直于字线的源极线。写行解码器和读行解码器专为闪存器件而设计，可在预编程中为闪速存储器阵列提供适当的电压，通过验证，擦除，以页面，块为单位进行验证，编程和读取操作，部门或芯片。

8. 发明授权

US08355287B2 Method and apparatus for operation of a NAND-like dual charge retaining transistor NOR flash memory device 失效
标题翻译：用于操作NAND类双电荷保持晶体管NOR闪存器件的方法和装置
公开(公告)号：US08355287B2
公开(公告)日：2013-01-15
申请号：US12806848
申请日：2010-08-23
申请人： Fu-Chang Hsu , Peter W. Lee
发明人： Fu-Chang Hsu , Peter W. Lee
IPC分类号： G11C16/06 , G11C16/04
CPC分类号： G11C16/0458 , G11C11/5628 , G11C11/5635 , G11C16/10 , G11C16/16 , G11C16/344 , G11C16/3445 , G11C16/3454 , G11C16/3459 , G11C16/3463 , G11C16/3477 , G11C2211/5621
摘要： A method and apparatus for operation for the NAND-like dual charge retaining transistor NOR flash memory cells begins by erasing, verifying over-erasing the threshold voltage level of the erased charge retaining transistors to an erased threshold voltage level. Then method progresses by programming one of two charge retaining transistors of the NAND-like dual charge retaining transistor NOR flash memory cells to a first programmed threshold voltage level, and programming the other of the two charge retaining transistors of the NAND-like dual charge retaining transistor NOR flash memory cells to the first programmed threshold voltage level or to a second programmed threshold voltage level. Combinations of the erased threshold voltage level and the first and second programmed threshold voltage levels determine an internal data state of the NAND-like dual charge retaining transistor NOR flash memory cells which are then decoded to ascertain the external data logical state.
摘要翻译：用于NAND类型的双电荷保持晶体管NOR闪存单元的操作的方法和装置开始于擦除，验证将擦除的电荷保持晶体管的阈值电压电平擦除为已擦除的阈值电压电平。然后，通过将NAND类双电荷保持晶体管NOR闪存单元的两个电荷保持晶体管中的一个编程为第一编程阈值电压电平，并编程NAND类似的双电荷保持的两个电荷保持晶体管中的另一个来进行方法晶体管NOR闪存单元到第一编程阈值电压电平或第二编程阈值电压电平。擦除阈值电压电平和第一和第二编程阈值电压电平的组合确定NAND类似的双电荷保持晶体管NOR闪存单元的内部数据状态，然后对其进行解码以确定外部数据逻辑状态。

9. 发明授权

US08335108B2 Bit line gate transistor structure for a multilevel, dual-sided nonvolatile memory cell NAND flash array 失效
标题翻译：位线栅晶体管结构，用于多层双面非易失性存储单元NAND闪存阵列
公开(公告)号：US08335108B2
公开(公告)日：2012-12-18
申请号：US12291913
申请日：2008-11-14
申请人： Peter Wung Lee , Fu-Chang Hsu
发明人： Peter Wung Lee , Fu-Chang Hsu
IPC分类号： G11C11/34
CPC分类号： G11C11/5621 , G11C16/0475 , G11C16/0483 , G11C16/08 , G11C16/24 , H01L29/7923
摘要： A nonvolatile memory structure with pairs of serially connected threshold voltage adjustable select transistors connected to the top and optionally to the bottom of NAND series strings of groups of the dual-sided charge-trapping nonvolatile memory cells for controlling connection of the NAND series string to an associated bit line. A first of the threshold voltage adjustable select transistors has its threshold voltage level adjusted to a first threshold voltage level and a second of the threshold voltage adjustable select transistors adjusted to a second threshold voltage level. The pair of serially connected threshold voltage adjustable select transistors is connected to a first of two associated bit lines. The NAND nonvolatile memory strings further is connected to a pair of serially connected threshold voltage adjustable bottom select transistors that is connected to the second associated bit line.
摘要翻译：连接到双极电荷捕获非易失性存储器单元的组的NAND系列的顶部和可选地连接到底部的具有串联连接的阈值电压可调选择晶体管的非易失性存储器结构，用于控制NAND系列串与关联位线。阈值电压可调选择晶体管中的第一个阈值电压电平被调整到第一阈值电压电平，而阈值电压可调选择晶体管中的第二阈值电压调整到第二阈值电压电平。一对串联连接的阈值电压可调选择晶体管连接到两个相关位线中的第一个。 NAND非易失性存储器串还连接到连接到第二关联位线的一对串联连接的阈值电压可调底部选择晶体管。

10. 发明授权

US08295087B2 Row-decoder and select gate decoder structures suitable for flashed-based EEPROM operating below +/− 10v BVDS 失效
标题翻译：行解码器和选择栅极解码器结构，适用于低于+/- 10v BVDS的基于闪存的EEPROM
公开(公告)号：US08295087B2
公开(公告)日：2012-10-23
申请号：US12456354
申请日：2009-06-16
申请人： Peter Wung Lee , Fu-Chang Hsu , Hsing-Ya Tsao
发明人： Peter Wung Lee , Fu-Chang Hsu , Hsing-Ya Tsao
IPC分类号： G11C16/04 , G11C11/4193
CPC分类号： G11C16/12 , G11C16/08 , G11C16/16 , G11C16/3445 , G11C16/3459
摘要： A nonvolatile memory device includes an array of EEPROM configured nonvolatile memory cells each having a floating gate memory transistor for storing a digital datum and a floating gate select transistor for activating the floating gate memory transistor for reading, programming, and erasing. The nonvolatile memory device has a row decoder to transfer the operational biasing voltage levels to word lines connected to the floating gate memory transistors for reading, programming, verifying, and erasing the selected nonvolatile memory cells. The nonvolatile memory device has a select gate decoder circuit transfers select gate control biasing voltages to the select gate control lines connected to the control gate of the floating gate select transistor for reading, programming, verifying, and erasing the floating gate memory transistor of the selected nonvolatile memory cells. The operational biasing voltage levels are generated to minimize operational disturbances and preventing drain to source breakdown in peripheral devices.
摘要翻译：非易失性存储器件包括EEPROM配置的非易失性存储单元的阵列，每个存储单元具有用于存储数字数据的浮动栅极存储晶体管和用于激活用于读取，编程和擦除的浮动栅极存储晶体管的浮动栅极选择晶体管。非易失性存储器件具有行解码器，用于将操作偏置电压电平传送到连接到浮置栅极存储晶体管的字线，用于读取，编程，验证和擦除所选择的非易失性存储器单元。非易失性存储器件具有选择栅极解码器电路，将选择栅极控制偏置电压传输到连接到浮置栅极选择晶体管的控制栅极的选择栅极控制线，用于读取，编程，验证和擦除所选择的浮置栅极存储晶体管非易失性存储单元。产生操作偏置电压电平以最小化操作干扰并防止外围设备中的漏极损耗。

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