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1. 发明授权

US08289775B2 Apparatus and method for inhibiting excess leakage current in unselected nonvolatile memory cells in an array 失效
标题翻译：用于抑制阵列中非选择性非易失性存储器单元中的多余泄漏电流的装置和方法
公开(公告)号：US08289775B2
公开(公告)日：2012-10-16
申请号：US12456744
申请日：2009-06-22
申请人： Peter Wung Lee , Fu-Chang Hsu , Hsing-Ya Tsao
发明人： Peter Wung Lee , Fu-Chang Hsu , Hsing-Ya Tsao
IPC分类号： G11C11/34 , G11C11/4193
CPC分类号： G11C11/5628 , G11C11/5635 , G11C11/5642 , G11C11/5671 , G11C16/0491 , G11C16/10 , G11C16/3436 , G11C2211/5621 , G11C2211/5641 , G11C2211/565
摘要： An apparatus and method for operating an array of NOR connected flash nonvolatile memory cells erases the array in increments of a page, block, sector, or the entire array while minimizing sub-threshold leakage current through unselected nonvolatile memory cells. The apparatus has a row decoder circuit and a source decoder circuit for selecting the nonvolatile memory cells for providing biasing conditions for reading, programming, verifying, and erasing the selected nonvolatile memory cells while minimizing sub-threshold leakage current through unselected nonvolatile memory cells.
摘要翻译：用于操作NOR连接的闪存非易失性存储器单元的阵列的装置和方法以页，块，扇区或整个阵列的增量擦除阵列，同时使通过未选择的非易失性存储单元的亚阈值泄漏电流最小化。该装置具有行解码器电路和源解码器电路，用于选择非易失性存储单元，以提供用于读取，编程，验证和擦除所选择的非易失性存储单元的偏置条件，同时使通过未选择的非易失性存储单元的亚阈值泄漏电流最小化。

2. 发明授权

US08072811B2 NAND based NMOS NOR flash memory cell, a NAND based NMOS NOR flash memory array, and a method of forming a NAND based NMOS NOR flash memory array 失效
标题翻译：基于NAND的NMOS NOR闪存单元，基于NAND的NMOS NOR闪存阵列，以及形成基于NAND的NMOS NOR闪存阵列的方法
公开(公告)号：US08072811B2
公开(公告)日：2011-12-06
申请号：US12387771
申请日：2009-05-07
申请人： Peter Wung Lee , Fu-Chang Hsu , Hsing-Ya Tsao
发明人： Peter Wung Lee , Fu-Chang Hsu , Hsing-Ya Tsao
IPC分类号： G11C11/34
CPC分类号： G11C16/10 , G11C11/5628 , G11C11/5642 , G11C16/0483 , G11C16/30 , G11C2211/5641 , H01L27/11519 , H01L27/11521 , H01L27/11524 , Y10T29/41
摘要： A NOR flash nonvolatile memory device provides the memory cell size and a low current program process of a NAND flash nonvolatile memory device and the fast, asynchronous random access of a NOR flash nonvolatile memory device. The NOR flash nonvolatile memory device has an array of NOR flash nonvolatile memory circuits that includes charge retaining transistors serially connected in a NAND string such that at least one of the charge retaining transistors functions as a select gate transistor to prevent leakage current through the charge retaining transistors when the charge retaining transistors is not selected for reading. The topmost charge retaining transistor's drain is connected to a bit line parallel to the charge retaining transistors and the bottommost charge retaining transistor's source is connected to a source line and is parallel to the bit line. The charge retaining transistors are programmed and erased with a Fowler-Nordheim tunneling process.
摘要翻译： NOR闪存非易失性存储器件提供NAND闪存非易失性存储器件的存储单元尺寸和低电流程序处理以及NOR非易失性存储器件的快速，异步随机存取。 NOR闪存非易失性存储器件具有NOR非易失性存储器电路阵列，其包括串联连接在NAND串中的电荷保持晶体管，使得至少一个电荷保持晶体管用作选择栅极晶体管，以防止漏电流通过电荷保持当电荷保持晶体管未被选择用于读取时，晶体管。最上面的电荷保持晶体管的漏极连接到与电荷保持晶体管平行的位线，并且最下面的电荷保持晶体管的源极连接到源极线并且平行于位线。电荷保持晶体管通过Fowler-Nordheim隧道工艺进行编程和擦除。

3. 发明申请

US20090316487A1 Apparatus and method for inhibiting excess leakage current in unselected nonvolatile memory cells in an array 失效
标题翻译：用于抑制阵列中非选择性非易失性存储器单元中的多余泄漏电流的装置和方法
公开(公告)号：US20090316487A1
公开(公告)日：2009-12-24
申请号：US12456744
申请日：2009-06-22
申请人： Peter Wung Lee , Fu-Chang Hsu , Hsing-Ya Tsao
发明人： Peter Wung Lee , Fu-Chang Hsu , Hsing-Ya Tsao
IPC分类号： G11C16/06 , G11C16/04 , G11C7/00
CPC分类号： G11C11/5628 , G11C11/5635 , G11C11/5642 , G11C11/5671 , G11C16/0491 , G11C16/10 , G11C16/3436 , G11C2211/5621 , G11C2211/5641 , G11C2211/565
摘要： An apparatus and method for operating an array of NOR connected flash nonvolatile memory cells erases the array in increments of a page, block, sector, or the entire array while minimizing sub-threshold leakage current through unselected nonvolatile memory cells. The apparatus has a row decoder circuit and a source decoder circuit for selecting the nonvolatile memory cells for providing biasing conditions for reading, programming, verifying, and erasing the selected nonvolatile memory cells while minimizing sub-threshold leakage current through unselected nonvolatile memory cells.
摘要翻译：用于操作NOR连接的闪存非易失性存储器单元的阵列的装置和方法以页，块，扇区或整个阵列的增量擦除阵列，同时使通过未选择的非易失性存储单元的亚阈值泄漏电流最小化。该装置具有行解码器电路和源解码器电路，用于选择非易失性存储单元，以提供用于读取，编程，验证和擦除所选择的非易失性存储单元的偏置条件，同时使通过未选择的非易失性存储单元的亚阈值泄漏电流最小化。

4. 发明授权

US6031765A Reversed split-gate cell array 有权
标题翻译：反向分裂栅极单元阵列
公开(公告)号：US6031765A
公开(公告)日：2000-02-29
申请号：US298032
申请日：1999-04-22
申请人： Peter Wung Lee , Fu-Chang Hsu , Hsing-Ya Tsao
发明人： Peter Wung Lee , Fu-Chang Hsu , Hsing-Ya Tsao
IPC分类号： G11C16/04 , G11C7/00
CPC分类号： G11C16/0425 , G11C16/16 , G11C16/3468
摘要： In this invention a reverse split gate device is described for creating a flash memory that avoids both programming and erase disturb conditions. The cell is designed so that the stacked gate is associated with the source and the enhancement gate is associated with the drain. This is the reverse of a conventional spit gate design and allows the drain to buffer the stacked gate from bit lines of a flash memory array. The source line now key to both program and erase operations is laid out in rows where two adjacent rows of cells share the same source line. The source line can be segmented to prevent the entire length of the pair of rows from being erased. The cell is programmed by flowing current backwards in the channel and injecting electrons in to the floating gate from an impact ionization that occurs near the source. Erasure is accomplished by Fowler-Nordheim tunneling from the floating gate to the source caused by a potential between the source and the enhancement gate.
摘要翻译：在本发明中，描述了用于创建避免编程和擦除干扰条件的闪速存储器的反向分离门装置。电池被设计成使得堆叠的栅极与源相关联，并且增强栅极与漏极相关联。这与传统的喷口设计相反，并允许漏极从闪存阵列的位线缓冲堆叠的栅极。现在，编程和擦除操作的关键是将两行的单元格共享相同的源行。可以对源极线进行分段，以防止该对行的整个长度被擦除。通过在通道中向后流动电流并将电子从在源附近发生的冲击电离注入到浮动栅极来编程单元。通过Fowler-Nordheim从源极和增强门之间的电位引起的浮动栅极到源极的擦除来完成擦除。

5. 发明授权

US5930826A Flash memory protection attribute status bits held in a flash memory array 失效
标题翻译：闪存保护属性状态位保存在闪存阵列中
公开(公告)号：US5930826A
公开(公告)日：1999-07-27
申请号：US833599
申请日：1997-04-07
申请人： Peter Wung Lee , Fu-Chang Hsu , Hsing-Ya Tsao
发明人： Peter Wung Lee , Fu-Chang Hsu , Hsing-Ya Tsao
IPC分类号： G06F12/14 , G11C16/22
CPC分类号： G06F12/1425 , G11C16/22
摘要： Flash memory circuits provide sector protection or file protection with protection attribute status bits held in a flash memory array. The sector protection protects memory data based on the physical location of the data. The flash memory array is divided into a number of memory sectors. Each memory sector can be protected independently. The size of the memory sector is flexible and may be as large as the whole memory array or as small as a single bit group. Each memory sector has protection bits stored in a protection bit array for indicating the protection state of the sector. A parallel protection structure providing both sector protection and block protection is also included. The parallel protection allows small size data protection as well as large size block protection. File protection protects memory data on a file basis regardless of the physical location of the data. Each file has protection bits stored in an attribute memory for indicating the protection state of the file. The attribute memory is made from part of the flash memory which simplifies the process of manufacturing the memory. It also reduces the area size of the attribute memory and the complexity of the control circuits.
摘要翻译：闪存电路提供扇区保护或文件保护，保护属性状态位保存在闪存阵列中。扇区保护基于数据的物理位置来保护存储器数据。闪存阵列被分成多个存储器扇区。每个内存扇区都可以独立保护。存储器扇区的大小是灵活的，并且可以与整个存储器阵列一样大，或者与单个位组一样小。每个存储器扇区具有存储在保护位阵列中的保护位，用于指示扇区的保护状态。还包括提供扇区保护和块保护的并行保护结构。并行保护允许小尺寸数据保护以及大尺寸块保护。文件保护以文件为基础保护存储器数据，而不管数据的物理位置如何。每个文件具有存储在属性存储器中的保护位，用于指示文件的保护状态。属性存储器由闪存的一部分制成，这简化了存储器的制造过程。它还减少了属性存储器的面积大小和控制电路的复杂性。

6. 发明授权

US08295087B2 Row-decoder and select gate decoder structures suitable for flashed-based EEPROM operating below +/− 10v BVDS 失效
标题翻译：行解码器和选择栅极解码器结构，适用于低于+/- 10v BVDS的基于闪存的EEPROM
公开(公告)号：US08295087B2
公开(公告)日：2012-10-23
申请号：US12456354
申请日：2009-06-16
申请人： Peter Wung Lee , Fu-Chang Hsu , Hsing-Ya Tsao
发明人： Peter Wung Lee , Fu-Chang Hsu , Hsing-Ya Tsao
IPC分类号： G11C16/04 , G11C11/4193
CPC分类号： G11C16/12 , G11C16/08 , G11C16/16 , G11C16/3445 , G11C16/3459
摘要： A nonvolatile memory device includes an array of EEPROM configured nonvolatile memory cells each having a floating gate memory transistor for storing a digital datum and a floating gate select transistor for activating the floating gate memory transistor for reading, programming, and erasing. The nonvolatile memory device has a row decoder to transfer the operational biasing voltage levels to word lines connected to the floating gate memory transistors for reading, programming, verifying, and erasing the selected nonvolatile memory cells. The nonvolatile memory device has a select gate decoder circuit transfers select gate control biasing voltages to the select gate control lines connected to the control gate of the floating gate select transistor for reading, programming, verifying, and erasing the floating gate memory transistor of the selected nonvolatile memory cells. The operational biasing voltage levels are generated to minimize operational disturbances and preventing drain to source breakdown in peripheral devices.
摘要翻译：非易失性存储器件包括EEPROM配置的非易失性存储单元的阵列，每个存储单元具有用于存储数字数据的浮动栅极存储晶体管和用于激活用于读取，编程和擦除的浮动栅极存储晶体管的浮动栅极选择晶体管。非易失性存储器件具有行解码器，用于将操作偏置电压电平传送到连接到浮置栅极存储晶体管的字线，用于读取，编程，验证和擦除所选择的非易失性存储器单元。非易失性存储器件具有选择栅极解码器电路，将选择栅极控制偏置电压传输到连接到浮置栅极选择晶体管的控制栅极的选择栅极控制线，用于读取，编程，验证和擦除所选择的浮置栅极存储晶体管非易失性存储单元。产生操作偏置电压电平以最小化操作干扰并防止外围设备中的漏极损耗。

7. 发明申请

US20090310411A1 Row-decoder and source-decoder structures suitable for erase in unit of page, sector and chip of a NOR-type flash operating below +/- 10V BVDS 失效
标题翻译：行解码器和源解码器结构适用于在+/- 10V BVDS以下操作的NOR型闪存的页面，扇区和芯片单元中的擦除
公开(公告)号：US20090310411A1
公开(公告)日：2009-12-17
申请号：US12455936
申请日：2009-06-09
申请人： Peter Wung Lee , Fu-Chang Hsu , Hsing-Ya Tsao
发明人： Peter Wung Lee , Fu-Chang Hsu , Hsing-Ya Tsao
IPC分类号： G11C16/04 , G11C7/00 , G11C16/16 , G11C16/06 , G11C8/00
CPC分类号： G11C8/12 , G11C16/0416 , G11C16/08 , G11C16/12 , G11C16/16
摘要： An apparatus and method for operating an array of NOR connected flash nonvolatile memory cells erases the array in increments of a page, block, sector, or the entire array while minimizing operational disturbances and providing bias operating conditions to prevent gate to source breakdown in peripheral devices. The apparatus has a row decoder circuit and a source decoder circuit for selecting the nonvolatile memory cells for providing biasing conditions for reading, programming, verifying, and erasing the selected nonvolatile memory cells while minimizing operational disturbances and preventing gate to source breakdown in peripheral devices.
摘要翻译：用于操作NOR连接的闪存非易失性存储器单元的阵列的装置和方法以页，块，扇区或整个阵列的增量擦除阵列，同时最小化操作干扰并提供偏置操作条件以防止外围设备中的门源故障。该装置具有行解码器电路和源解码器电路，用于选择非易失性存储单元以提供用于读取，编程，验证和擦除所选择的非易失性存储单元的偏置条件，同时最小化操作干扰并防止门外围设备中的故障。

8. 发明申请

US20090279360A1 NAND based NMOS NOR flash memory cell, a NAND based NMOS nor flash memory array, and a method of forming a NAND based NMOS NOR flash memory array 失效
标题翻译：基于NAND的NMOS NOR闪存单元，基于NAND的NMOS或闪速存储器阵列，以及形成基于NAND的NMOS NOR闪存阵列
公开(公告)号：US20090279360A1
公开(公告)日：2009-11-12
申请号：US12387771
申请日：2009-05-07
申请人： Peter Wung Lee , Fu-Chang Hsu , Hsing-Ya Tsao
发明人： Peter Wung Lee , Fu-Chang Hsu , Hsing-Ya Tsao
IPC分类号： G11C16/04 , G11C16/06 , H01L21/00
CPC分类号： G11C16/10 , G11C11/5628 , G11C11/5642 , G11C16/0483 , G11C16/30 , G11C2211/5641 , H01L27/11519 , H01L27/11521 , H01L27/11524 , Y10T29/41
摘要： A NOR flash nonvolatile memory device provides the memory cell size and a low current program process of a NAND flash nonvolatile memory device and the fast, asynchronous random access of a NOR flash nonvolatile memory device. The NOR flash nonvolatile memory device has an array of NOR flash nonvolatile memory circuits. Each NOR flash nonvolatile memory circuit includes a plurality of charge retaining transistors serially connected in a NAND string. A drain of a topmost charge retaining transistor is connected to a bit line associated with the serially connected charge retaining transistors and a source of a bottommost charge retaining transistor is connected to a source line associated with the charge retaining transistors. Each control gate of the charge retaining transistors on each row is commonly connected to a word line. The charge retaining transistors are programmed and erased with a Fowler-Nordheim tunneling process.
摘要翻译： NOR闪存非易失性存储器件提供NAND闪存非易失性存储器件的存储单元尺寸和低电流程序处理以及NOR非易失性存储器件的快速，异步随机存取。 NOR闪存非易失性存储器件具有NOR闪存非易失性存储器电路阵列。每个NOR非易失性存储器电路包括以NAND串串联连接的多个电荷保持晶体管。最高电荷保持晶体管的漏极连接到与串联连接的电荷保持晶体管相关联的位线，并且最下面的电荷保持晶体管的源极连接到与电荷保持晶体管相关联的源极线。每行上的电荷保持晶体管的每个控制栅极共同连接到字线。电荷保持晶体管通过Fowler-Nordheim隧道工艺进行编程和擦除。

9. 发明授权

US06262622B1 Breakdown-free high voltage input circuitry 失效
标题翻译：无击穿高压输入电路
公开(公告)号：US06262622B1
公开(公告)日：2001-07-17
申请号：US09479649
申请日：2000-01-08
申请人： Peter Wung Lee , Fu-Chang Hsu , Hsing-Ya Tsao , Vei-Han Chan , Hung-Sheng Chen
发明人： Peter Wung Lee , Fu-Chang Hsu , Hsing-Ya Tsao , Vei-Han Chan , Hung-Sheng Chen
IPC分类号： G05F302
CPC分类号： G05F3/242
摘要： A high voltage input circuit includes a triple-well NMOS for reducing the voltage stress across its drain junction for preventing it from breakdown. The triple-well NMOS is fabricated in a P-well formed in a deep N-well on a P-substrate. The P-well is coupled to a power supply voltage by a P-well voltage control device to reduce the voltage difference across the drain junction. A low voltage signal input circuit portion is also added to the high voltage input circuit to allow a high voltage input pin to receive other signal and reduce the total pin count of an integrated circuit. A dual-input buffer such as NAND gate instead of an inverter is used in the low voltage signal input circuit for reducing the voltage stress to the devices in the low voltage signal input circuit.
摘要翻译：高压输入电路包括三阱NMOS，用于减小跨越其漏极结的电压应力，以防止其击穿。三阱NMOS在P衬底中形成在深N阱中的P阱中制造。 P阱通过P阱电压控制装置耦合到电源电压，以减少跨越漏极结的电压差。低电压信号输入电路部分也被添加到高电压输入电路，以允许高电压输入引脚接收其它信号并减少集成电路的总引脚数。在低电压信号输入电路中使用诸如NAND门而不是反相器的双输入缓冲器，用于降低对低电压信号输入电路中的器件的电压应力。

10. 发明授权

US08634241B2 Universal timing waveforms sets to improve random access read and write speed of memories 失效
标题翻译：通用时序波形设置，以提高随机存取存储器的读写速度
公开(公告)号：US08634241B2
公开(公告)日：2014-01-21
申请号：US13323600
申请日：2011-12-12
申请人： Peter Wung Lee , Fu-Chang Hsu , Hsing-Ya Tsao
发明人： Peter Wung Lee , Fu-Chang Hsu , Hsing-Ya Tsao
IPC分类号： G11C16/06
CPC分类号： G11C16/06 , G06F2213/0038 , G11C11/40615 , G11C16/26
摘要： Methods of increasing the speed of random read and write operations of a memory device are provided for improving the performance of volatile and non-volatile memory devices. In contrast to the conventional approach that latches the current memory address right before the currently accessed memory data are outputted, the methods latch the next memory address before the currently accessed memory data are read out. The flow, timing waveforms and control sequences of applying the methods to parallel NOR flash, parallel pSRAM, serial SQI NOR flash and NAND flash are described in detail. The NOR flash device designed with the method can be integrated with a NAND flash device on a same die in a combo flash device packaged in either an ONFI compatible NAND flash package or other standard NAND flash package.
摘要翻译：为提高易失性和非易失性存储器件的性能，提供了增加存储器件的随机读和写操作速度的方法。与在当前访问的存储器数据输出之前锁存当前存储器地址的常规方法相反，该方法在读出当前访问的存储器数据之前锁存下一个存储器地址。详细描述将方法应用于并行NOR闪存，并行pSRAM，串行SQI NOR闪存和NAND闪存的流程，时序波形和控制顺序。使用该方法设计的NOR闪存器件可以与封装在ONFI兼容的NAND闪存封装或其他标准NAND闪存封装中的组合闪存器件中的NAND闪存器件集成在同一芯片上。

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