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1. 发明申请

US20070040202A1 Semiconductor memory cell array having self-aligned recessed gate MOS transistors and method for forming the same 审中-公开
标题翻译：具有自对准凹栅MOS晶体管的半导体存储单元阵列及其形成方法
公开(公告)号：US20070040202A1
公开(公告)日：2007-02-22
申请号：US11206306
申请日：2005-08-18
申请人： Gerhard Enders , Marc Strasser , Peter Voigt , Bjorn Fischer
发明人： Gerhard Enders , Marc Strasser , Peter Voigt , Bjorn Fischer
IPC分类号： H01L29/94 , H01L21/8242
CPC分类号： H01L27/10876 , H01L27/10861
摘要： In a semiconductor memory including an array of memory cells, each memory cell includes a trench capacitor, the trench capacitor including an inner electrode, an outer electrode and a dielectric layer disposed between the inner electrode and the outer electrode, and a selection transistor, the selection transistor including a first source/drain area, a second source/drain area and a channel region disposed between the first source/drain area and the second source/drain area in a recess, the trench capacitor and the selection transistor of each memory cell are disposed side by side, the first source/drain area of the selection transistor being electrically connected to the inner electrode of the trench capacitor, the recess in which the channel region of the selection transistor is formed being located self aligned between the trench capacitor of the memory cell and the trench capacitor of an adjacent memory cell.
摘要翻译：在包括存储单元阵列的半导体存储器中，每个存储单元包括沟槽电容器，所述沟槽电容器包括内电极，外电极和设置在内电极和外电极之间的电介质层，以及选择晶体管，选择晶体管，其包括第一源极/漏极区域，第二源极/漏极区域和设置在凹部中的第一源极/漏极区域和第二源极/漏极区域之间的沟道区域，每个存储器单元的沟槽电容器和选择晶体管并排配置，选择晶体管的第一源极/漏极区域电连接到沟槽电容器的内部电极，形成选择晶体管的沟道区域的凹槽位于沟槽电容器的沟槽电容器之间，存储单元和相邻存储单元的沟槽电容器。

2. 发明授权

US07081392B2 Method for fabricating a gate structure of a FET and gate structure of a FET 失效
标题翻译：用于制造FET的栅极结构和FET的栅极结构的方法
公开(公告)号：US07081392B2
公开(公告)日：2006-07-25
申请号：US10897403
申请日：2004-07-23
申请人： Gerhard Enders , Peter Voigt
发明人： Gerhard Enders , Peter Voigt
IPC分类号： H01L21/336
CPC分类号： H01L29/6659 , H01L29/4966 , H01L29/66492 , H01L29/6653 , H01L29/66545 , H01L29/7833
摘要： A method for fabricating a gate structure of a FET, having: (a) deposition and patterning of a sacrificial layer sequence on a semiconductor substrate and uncovering of a gate section; (b) implantation of a channel doping into the gate section; (c) deposition and patterning of spacers at the sidewalls of the sacrificial layer sequence with the formation of a gate section that is not covered by the spacers; (d) introduction of a mask material into the gate section that is not covered by the spacers; (e) removal of the spacers selectively with respect to the sacrificial layer sequence and mask material); (f) implantation of a halo doping in regions uncovered by the removed spacers; (g) removal of the mask material; (h) formation of a gate on the gate section; and (j) removal of the sacrificial layer sequence selectively with respect to the gate.
摘要翻译：一种用于制造FET的栅极结构的方法，具有：（a）在半导体衬底上沉积和图案化牺牲层序列并露出栅极部分; （b）将沟道掺杂注入到栅极部分中; （c）在牺牲层序列的侧壁处沉积和图案化间隔物，形成未被间隔物覆盖的栅极部分; （d）将掩模材料引入未被间隔物覆盖的栅极部分; （e）相对于牺牲层序列和掩模材料选择性去除间隔物）; （f）在被去除的间隔物覆盖的区域内注入晕圈; （g）去除掩模材料; （h）在栅极部分上形成栅极; 和（j）相对于栅极选择性地去除牺牲层序列。

3. 发明授权

US07009263B2 Field-effect transistor 失效
标题翻译：场效应晶体管
公开(公告)号：US07009263B2
公开(公告)日：2006-03-07
申请号：US10830675
申请日：2004-04-23
申请人： Gerhard Enders , Bjoern Fischer , Helmut Schneider , Peter Voigt
发明人： Gerhard Enders , Bjoern Fischer , Helmut Schneider , Peter Voigt
IPC分类号： H01L29/76
CPC分类号： H01L29/0649 , H01L29/1033
摘要： A field-effect transistor includes a semiconductor substrate, a source region formed in the semiconductor substrate, a drain region formed in the semiconductor substrate, a channel region formed in the semiconductor substrate, wherein the source region is connected to a source terminal electrode and the drain region is connected to a drain terminal electrode, wherein the channel region comprises a first narrow width channel region and a second narrow width channel region connected in parallel regarding the source terminal electrode and the drain terminal electrode, and wherein the first narrow width channel region and/or the second narrow width channel region comprise lateral edges narrowing the width of the narrow width channel region is such a way that a channel formation in the narrow width channel region is influenced by a mutually influencing effect of the lateral edges, and a gate electrode arranged above the first and second narrow width channel regions.
摘要翻译：场效应晶体管包括半导体衬底，形成在半导体衬底中的源极区域，形成在半导体衬底中的漏极区域，形成在半导体衬底中的沟道区域，其中源极区域连接到源极端子电极，漏极区域连接到漏极端子电极，其中沟道区域包括关于源极端子电极和漏极端子电极并联连接的第一窄宽度沟道区域和第二窄度沟道区域，并且其中第一窄宽度沟道区域和/或第二窄宽度沟道区域包括使窄宽度沟道区域的宽度变窄的横向边缘，使得窄宽度沟道区域中的沟道形成受到横向边缘的相互影响的影响，电极，布置在第一和第二窄宽度通道区域的上方。

4. 发明授权

US06503784B1 Double gated transistor 有权
标题翻译：双门控晶体管
公开(公告)号：US06503784B1
公开(公告)日：2003-01-07
申请号：US09670742
申请日：2000-09-27
申请人： Gerhard Enders , Thomas Schulz , Dietrich Widmann , Lothar Risch
发明人： Gerhard Enders , Thomas Schulz , Dietrich Widmann , Lothar Risch
IPC分类号： H01L218238
CPC分类号： H01L27/11 , H01L21/823885 , H01L27/092 , H01L27/1104 , H01L27/1203
摘要： A semiconductor body-having a pair of vertical, double-gated CMOS transistors. An insulating layer extending horizontally beneath the surface of the semiconductor body such insulating layer being disposed beneath the pair of transistors. The transistors, together with additional such transistors, are arranged to form a Synchronous Dynamic Random Access Memory (SRAM) array. The array includes a plurality of SRAM cells arranged in rows and columns, each one of the cells having a WORDLINE connected to a WORLDINE CONTACT. The WORDLINE CONTACT is common to four contiguous one of the cells. One of the cells having a plurality of electrically interconnected MOS transistors arranged to provide an SRAM circuit. Each one of the cells has a VDD CONTACT and a VSS CONTACT. One of such CONTACTs is disposed centrally within each one of the cells and the other one of the CONTACTs being common to four contiguous ones of the cells. Each one of the cells has the common one of the CONTACTs and the WORDLINE CONTACT disposed at peripheral, corner regions of the cell.
摘要翻译：一种具有一对垂直双门控CMOS晶体管的半导体体。在半导体本体的表面下水平延伸的绝缘层，该绝缘层设置在该对晶体管的下方。晶体管与附加的这种晶体管一起被布置成形成同步动态随机存取存储器（SRAM）阵列。阵列包括以行和列排列的多个SRAM单元，每个单元都具有连接到WORLDINE CONTACT的WORDLINE。 WORDLINE CONTACT是四个连续的一个单元格共同的。具有多个电互连的MOS晶体管的单元之一被布置成提供SRAM电路。每个单元都有一个VDD CONTACT和一个VSS CONTACT。这种CONTACT之一被布置在每个单元格的中心并且另一个CONTACT被四个相邻的单元共同。每个单元格具有共同的一个CONTACT和WORDLINE CONTACT放置在单元的外围角区域。

5. 发明授权

US06472767B1 Static random access memory (SRAM) 有权
标题翻译：静态随机存取存储器（SRAM）
公开(公告)号：US06472767B1
公开(公告)日：2002-10-29
申请号：US09302757
申请日：1999-04-30
申请人： Gerhard Enders , Thomas Schulz , Dietrich Widmann , Lothar Risch
发明人： Gerhard Enders , Thomas Schulz , Dietrich Widmann , Lothar Risch
IPC分类号： H01L2711
CPC分类号： H01L27/11 , H01L27/1104
摘要： A semiconductor body having a pair of vertical, double-gated CMOS transistors. An insulating layer extending horizontally beneath the surface of the semiconductor body such insulating layer being disposed beneath the pair of transistors. The transistors, together with additional such transistors, are arranged to form a Synchronous Dynamic Random Access Memory (SRAM) array. The array includes a plurality of SRAM cells arranged in rows and columns, each one of the cells having a WORDLINE connected to a WORLDINE CONTACT. The WORDLINE CONTACT is common to four contiguous one of the cells. One of the cells having a plurality of electrically interconnected MOS transistors arranged to provide an SRAM circuit. Each one of the cells has a VDD CONTACT and a VSS CONTACT. One of such CONTACTs is disposed centrally within each one of the cells and the other one of the CONTACTs being common to four contiguous ones of the cells. Each one of the cells has the common one of the CONTACTs and the WORDLINE CONTACT disposed at peripheral, corner regions of the cell.
摘要翻译：具有一对垂直双门控CMOS晶体管的半导体本体。在半导体本体的表面下水平延伸的绝缘层，该绝缘层设置在该对晶体管的下方。晶体管与附加的这种晶体管一起被布置成形成同步动态随机存取存储器（SRAM）阵列。阵列包括以行和列排列的多个SRAM单元，每个单元都具有连接到WORLDINE CONTACT的WORDLINE。 WORDLINE CONTACT是四个连续的一个单元格共同的。具有多个电互连的MOS晶体管的单元之一被布置成提供SRAM电路。每个单元都有一个VDD CONTACT和一个VSS CONTACT。这种CONTACT之一被布置在每个单元格的中心并且另一个CONTACT被四个相邻的单元共同。每个单元格具有共同的一个CONTACT和WORDLINE CONTACT放置在单元的外围角区域。

6. 发明申请

US20120181609A1 FULLY DEPLETED SOI DEVICE WITH BURIED DOPED LAYER 有权
标题翻译：完全覆盖的SOI器件与BEDIED DOPED层
公开(公告)号：US20120181609A1
公开(公告)日：2012-07-19
申请号：US13305206
申请日：2011-11-28
申请人： Gerhard Enders , Wolfgang Hoenlein , Franz Hofman , Carlos Mazure
发明人： Gerhard Enders , Wolfgang Hoenlein , Franz Hofman , Carlos Mazure
IPC分类号： H01L27/088 , H01L29/36 , H01L21/8238
CPC分类号： H01L27/10894 , H01L21/84 , H01L27/10876 , H01L27/1207 , H01L29/4236 , H01L29/66621
摘要： The present invention relates to a method for the manufacture of a semiconductor device by providing a first substrate; providing a doped layer in a surface region of the first substrate; providing a buried oxide layer on the doped layer; providing a semiconductor layer on the buried oxide layer to obtain a semiconductor-on-insulator (SeOI) wafer; removing the buried oxide layer and the semiconductor layer from a first region of the SeOI wafer while maintaining the buried oxide layer and the semiconductor layer in a second region of the SeOI water; providing an upper transistor in the second region by forming a back gate in or by the doped layer; and providing a lower transistor in the first region by forming source and drain regions in or by the doped layer.
摘要翻译：本发明涉及通过提供第一基板来制造半导体器件的方法; 在所述第一衬底的表面区域中提供掺杂层; 在所述掺杂层上提供掩埋氧化物层; 在掩埋氧化物层上提供半导体层以获得绝缘体上半导体（SeOI）晶片; 从所述SeOI晶片的第一区域去除所述掩埋氧化物层和所述半导体层，同时将所述掩埋氧化物层和所述半导体层保持在所述SeOI晶片的第二区域中; 通过在掺杂层中或由掺杂层形成背栅，在第二区域中提供上晶体管; 以及通过在掺杂层中或由掺杂层形成源极和漏极区域来在第一区域中提供下部晶体管。

7. 发明授权

US07335936B2 DRAM memory having vertically arranged selection transistors 失效
标题翻译：具有垂直排列的选择晶体管的DRAM存储器
公开(公告)号：US07335936B2
公开(公告)日：2008-02-26
申请号：US10744051
申请日：2003-12-23
申请人： Michael Sommer , Gerhard Enders
发明人： Michael Sommer , Gerhard Enders
IPC分类号： H01L29/72
CPC分类号： H01L27/10864 , H01L27/10841 , H01L27/10891 , H01L29/66181
摘要： Memory cell having a trench capacitor that is constructed in a lower region of a substantially perpendicular trench hole, and which comprises an inner and an outer electrode, a dielectric layer being arranged between the inner and the outer electrodes, a vertical selection transistor that has a substantially perpendicular channel region, which is constructed adjacent to an upper region of the trench hole and which connects the inner electrode of the trench capacitor to a bit line, it being possible to construct a conductive channel as a function of the potential of a word line in the channel region, the channel region partially enclosing the trench hole in its upper region, and the associated work line at least partially surrounding the channel region.
摘要翻译：具有沟槽电容器的存储单元，其构造在基本上垂直的沟槽孔的下部区域中，并且包括内部和外部电极，布置在内部和外部电极之间的电介质层，垂直选择晶体管，其具有基本上垂直的沟道区域，其被构造成与沟槽孔的上部区域相邻并且将沟槽电容器的内部电极连接到位线，可以构造作为字线的电位的函数的导电沟道在通道区域中，通道区域部分地围绕其上部区域中的沟槽孔，并且相关联的工作线至少部分地围绕通道区域。

8. 发明申请

US20060148178A1 Method for producing a vertical transistor 审中-公开
标题翻译：垂直晶体管的制造方法
公开(公告)号：US20060148178A1
公开(公告)日：2006-07-06
申请号：US11367217
申请日：2006-03-03
申请人： Dietrich Bonart , Gerhard Enders , Peter Voigt
发明人： Dietrich Bonart , Gerhard Enders , Peter Voigt
IPC分类号： H01L21/336 , H01L21/3205
CPC分类号： H01L27/10876 , H01L27/10841 , H01L29/78642
摘要： The present invention relates to a method for producing a vertical transistor, and to a vertical transistor. A sacrificial gate oxide and a sacrificial gate electrode are used during the production of the vertical transistor to makes it possible to considerably reduce or entirely avoid negative effects that normally result from the production of insulation structures between the vertical transistors. In particular, broadening of the gate oxide at the edge of the gate electrode can be prevented, and the edge of the gate electrode can be influenced deliberately. This allows vertical transistors to be produced having a current/voltage characteristic that can be adjusted specifically. In particular, vertical transistors can be produced having a pronounced corner effect.
摘要翻译：本发明涉及垂直晶体管的制造方法和垂直晶体管。在制造垂直晶体管期间使用牺牲栅极氧化物和牺牲栅电极，使得可以显着地减少或完全避免通常由垂直晶体管之间的绝缘结构的产生产生的负面影响。特别地，可以防止在栅电极的边缘处的栅极氧化物的扩大，并且栅电极的边缘可能被故意地影响。这允许产生具有能够被特别调整的电流/电压特性的垂直晶体管。特别地，可以产生具有显着角落效应的垂直晶体管。

9. 发明授权

US06992345B2 Integrated semiconductor memory with a selection transistor formed at a ridge 失效
标题翻译：具有形成在脊上的选择晶体管的集成半导体存储器
公开(公告)号：US06992345B2
公开(公告)日：2006-01-31
申请号：US10727595
申请日：2003-12-05
申请人： Gerhard Enders , Andreas Spitzer
发明人： Gerhard Enders , Andreas Spitzer
IPC分类号： H01L27/108
CPC分类号： H01L27/10823 , H01L27/10829 , H01L27/10867 , H01L27/1203
摘要： An integrated semiconductor memory is disclosed having selection transistors which can be formed at a respective ridge. The ridge can be arranged on an insulation layer. In the ridge the first source/drain region can be formed at one lateral end of the ridge and the second source/drain region can be formed at another lateral end of the ridge. The longitudinal sides of the ridge and a top side of the ridge can be covered with a layer stack including a gate dielectric and a gate electrode. High write-read currents can be achieved in the on state of the selection transistors and leakage currents occurring in the off state can be reduced.
摘要翻译：公开了一种集成半导体存储器，其具有可以形成在各自的脊上的选择晶体管。脊可以布置在绝缘层上。在脊中，第一源极/漏极区域可以形成在脊的一个横向端部，并且第二源极/漏极区域可以形成在脊的另一侧向端部。脊的纵向边和脊的顶侧可以用包括栅极电介质和栅电极的层堆叠覆盖。可以在选择晶体管的导通状态下实现高写入电流，并且可以减少在断开状态下发生的漏电流。

10. 发明授权

US06876025B2 Dram cell and space-optimized memory array 失效
标题翻译： Dram cell和空间优化的内存阵列
公开(公告)号：US06876025B2
公开(公告)日：2005-04-05
申请号：US10462513
申请日：2003-06-16
申请人： Michael Sommer , Gerhard Enders
发明人： Michael Sommer , Gerhard Enders
IPC分类号： H01L21/8242 , H01L27/02 , H01L27/108 , H01L29/76 , H01L31/119
CPC分类号： H01L27/10876 , H01L27/0207 , H01L27/10864 , H01L27/10891
摘要： The memory cell according to the invention has a vertical selection transistor, via whose channel region the inner electrode of the trench capacitor can be connected to a bit line. The channel region is led to the bit line through an associated word line, which completely or partially encloses the channel region. As a result, a conductive channel can be formed within the channel region depending on the potential of the word line. Preferably, the extent of the trench hole in the word line direction is at least 1.5 times as large as in the bit line direction.
摘要翻译：根据本发明的存储单元具有垂直选择晶体管，其通道区域可以将沟槽电容器的内部电极连接到位线。通道区域通过相关联的字线被引导到位线，该字线完全或部分地包围通道区域。结果，可以根据字线的电位在通道区域内形成导电沟道。优选地，字线方向上的沟槽的面积是位线方向的至少1.5倍。

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