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1. 发明申请

US20100078770A1 Lock and Key Through-Via Method for Wafer Level 3 D Integration and Structures Produced 有权
标题翻译：晶圆3 D集成和结构的锁定和密钥通过方法
公开(公告)号：US20100078770A1
公开(公告)日：2010-04-01
申请号：US12239688
申请日：2008-09-26
申请人： Sampath Purushothaman , Mary E. Rothwell , Ghavam Ghavami Shahidi , Roy Rongqing Yu
发明人： Sampath Purushothaman , Mary E. Rothwell , Ghavam Ghavami Shahidi , Roy Rongqing Yu
IPC分类号： H01L23/52 , H01L21/60
CPC分类号： H01L21/76898 , H01L21/6835 , H01L23/481 , H01L24/11 , H01L24/83 , H01L24/90 , H01L25/0657 , H01L25/50 , H01L27/0688 , H01L2221/68377 , H01L2224/05001 , H01L2224/05009 , H01L2224/05124 , H01L2224/05139 , H01L2224/05144 , H01L2224/05147 , H01L2224/05155 , H01L2224/05164 , H01L2224/05169 , H01L2224/05184 , H01L2224/05567 , H01L2224/0557 , H01L2224/05573 , H01L2224/1147 , H01L2224/13025 , H01L2224/13099 , H01L2224/16147 , H01L2224/16237 , H01L2224/2919 , H01L2224/81141 , H01L2224/81191 , H01L2224/83121 , H01L2224/83141 , H01L2224/83194 , H01L2224/838 , H01L2224/9202 , H01L2225/06513 , H01L2225/06527 , H01L2225/06541 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01015 , H01L2924/01018 , H01L2924/01019 , H01L2924/01027 , H01L2924/01029 , H01L2924/01033 , H01L2924/01042 , H01L2924/01046 , H01L2924/01047 , H01L2924/0105 , H01L2924/01073 , H01L2924/01074 , H01L2924/01075 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/0132 , H01L2924/0133 , H01L2924/014 , H01L2924/04953 , H01L2924/0665 , H01L2924/14 , H01L2924/00 , H01L2924/01028 , H01L2924/00014
摘要： A three dimensional device stack structure comprises two or more active device and interconnect layers further connected together using through substrate vias. Methods of forming the three dimensional device stack structure comprise alignment, bonding by lamination, thinning and post thinning processing. The via features enable the retention of alignment through the lamination process and any subsequent process steps thus achieving a mechanically more robust stack structure compared to the prior art.
摘要翻译：三维器件堆叠结构包括两个或更多个有源器件和互连层，其通过衬底通孔进一步连接在一起。形成三维器件堆叠结构的方法包括对准，通过层压粘接，变薄和后变薄处理。通孔特征使得能够通过层压工艺和任何后续工艺步骤保持对准，从而与现有技术相比实现机械上更坚固的堆叠结构。

2. 发明授权

US6131182A Method and apparatus for synthesizing and optimizing control logic based on SRCMOS logic array macros 失效
标题翻译：用于合成和优化基于SRCMOS逻辑阵列宏的控制逻辑的方法和装置
公开(公告)号：US6131182A
公开(公告)日：2000-10-10
申请号：US850037
申请日：1997-05-02
申请人： Michael Patrick Beakes , Barbara Alana Chappell , Terry Ivan Chappell , Gary S. Ditlow , Barry Lee Dorfman , Bruce Martin Fleischer , Vinod Narayanan , Robert Alan Philhower , George Anthony Sai Halasz , Ghavam Ghavami Shahidi , David James Widiger
发明人： Michael Patrick Beakes , Barbara Alana Chappell , Terry Ivan Chappell , Gary S. Ditlow , Barry Lee Dorfman , Bruce Martin Fleischer , Vinod Narayanan , Robert Alan Philhower , George Anthony Sai Halasz , Ghavam Ghavami Shahidi , David James Widiger
IPC分类号： G06F17/50
CPC分类号： G06F17/505 , G06F17/5068
摘要： A computer-based method automatically synthesizes, optimizes and compiles high performance control logic using SRCMOS LOGIC ARRAY MACROS, abbreviated as SLAMs. The method includes a series of steps that transform a high level design description into a set of SLAMs, and includes the steps of partitioning the logic description of a unit into blocks that are suitable for mapping to a target SLAM structure; mapping each logic partition to the target SLAM structure; creating a configuration and relative layout for the internal structure for each SLAM; creating an external description for each SLAM, each description being of sufficient detail to carry out physical design and integration of the unit which contains the SLAM; assembling the partitions implemented as SLAMs with other macros in the unit; resolving interface conflicts between the different macros by selecting appropriate signal interfaces for various SLAMs; repeatedly changing the external specifications of the various SLAMs; analyzing the performance of the unit; automatically compiling the schematic and layout of each SLAM within the unit based on the configuration and relative layout; and assembling the macros and analyzing the design for design rule violations.
摘要翻译：基于计算机的方法使用SRCMOS LOGIC ARRAY MACROS（缩写为SLAM）自动合成，优化和编译高性能控制逻辑。该方法包括将高级设计描述转换成一组SLAM的一系列步骤，并且包括以下步骤：将单元的逻辑描述划分成适于映射到目标SLAM结构的块; 将每个逻辑分区映射到目标SLAM结构; 为每个SLAM创建内部结构的配置和相对布局; 为每个SLAM创建外部描述，每个描述具有足够的细节来执行包含SLAM的单元的物理设计和集成; 将实现为SLAM的分区与其他宏组合在一起; 通过为各种SLAM选择适当的信号接口来解决不同宏之间的接口冲突; 反复改变各种SLAM的外部规格; 分析单位的绩效; 根据配置和相对布局自动编译单元内各SLAM的原理图和布局; 并组装宏并分析违规设计规则的设计。

3. 发明申请

US20110111560A1 Lock and Key Through-Via Method for Wafer Level 3D Integration and Structures Produced Thereby 有权
标题翻译：用于晶圆级3D集成和结构的锁定和密钥通过方法
公开(公告)号：US20110111560A1
公开(公告)日：2011-05-12
申请号：US12615175
申请日：2009-11-09
申请人： Sampath Purushothaman , Mary E. Rothwell , Ghavam Ghavami Shahidi , Roy Rongging Yu
发明人： Sampath Purushothaman , Mary E. Rothwell , Ghavam Ghavami Shahidi , Roy Rongging Yu
IPC分类号： H01L21/50
CPC分类号： H01L25/0657 , H01L21/76898 , H01L25/50 , H01L2224/81141 , H01L2224/81191 , H01L2225/06513 , H01L2225/06541 , H01L2225/06593
摘要： A three dimensional device stack structure comprises two or more active device and interconnect layers further connected together using through substrate vias. Methods of forming the three dimensional device stack structure comprise alignment, bonding by lamination, thinning and post thinning processing. The via features enable the retention of alignment through the lamination process and any subsequent process steps thus achieving a mechanically more robust stack structure compared to the prior art.
摘要翻译：三维器件堆叠结构包括两个或更多个有源器件和互连层，其通过衬底通孔进一步连接在一起。形成三维器件堆叠结构的方法包括对准，通过层压粘接，变薄和后变薄处理。通孔特征使得能够通过层压工艺和任何后续工艺步骤保持对准，从而与现有技术相比实现机械上更坚固的堆叠结构。

4. 发明授权

US09064717B2 Lock and key through-via method for wafer level 3D integration and structures produced thereby 有权
标题翻译：用于晶片级3D集成的锁定和键通孔方法以及由此产生的结构
公开(公告)号：US09064717B2
公开(公告)日：2015-06-23
申请号：US12615175
申请日：2009-11-09
申请人： Sampath Purushothaman , Mary E. Rothwell , Ghavam Ghavami Shahidi , Roy Rongqing Yu
发明人： Sampath Purushothaman , Mary E. Rothwell , Ghavam Ghavami Shahidi , Roy Rongqing Yu
IPC分类号： H01L21/50 , H01L25/065 , H01L21/768 , H01L25/00
CPC分类号： H01L25/0657 , H01L21/76898 , H01L25/50 , H01L2224/81141 , H01L2224/81191 , H01L2225/06513 , H01L2225/06541 , H01L2225/06593
摘要： A three dimensional device stack structure comprises two or more active device and interconnect layers further connected together using through substrate vias. Methods of forming the three dimensional device stack structure comprise alignment, bonding by lamination, thinning and post thinning processing. The via features enable the retention of alignment through the lamination process and any subsequent process steps thus achieving a mechanically more robust stack structure compared to the prior art.
摘要翻译：三维器件堆叠结构包括两个或更多个有源器件和互连层，其通过衬底通孔进一步连接在一起。形成三维器件堆叠结构的方法包括对准，通过层压粘接，变薄和后变薄处理。通孔特征使得能够通过层压工艺和任何后续工艺步骤保持对准，从而与现有技术相比实现机械上更坚固的堆叠结构。

5. 发明授权

US07855455B2 Lock and key through-via method for wafer level 3 D integration and structures produced 有权
标题翻译：用于晶圆级3D集成和结构的锁定和键通孔方法
公开(公告)号：US07855455B2
公开(公告)日：2010-12-21
申请号：US12239688
申请日：2008-09-26
申请人： Sampath Purushothaman , Mary E. Rothwell , Ghavam Ghavami Shahidi , Roy Rongqing Yu
发明人： Sampath Purushothaman , Mary E. Rothwell , Ghavam Ghavami Shahidi , Roy Rongqing Yu
IPC分类号： H01L23/48
CPC分类号： H01L21/76898 , H01L21/6835 , H01L23/481 , H01L24/11 , H01L24/83 , H01L24/90 , H01L25/0657 , H01L25/50 , H01L27/0688 , H01L2221/68377 , H01L2224/05001 , H01L2224/05009 , H01L2224/05124 , H01L2224/05139 , H01L2224/05144 , H01L2224/05147 , H01L2224/05155 , H01L2224/05164 , H01L2224/05169 , H01L2224/05184 , H01L2224/05567 , H01L2224/0557 , H01L2224/05573 , H01L2224/1147 , H01L2224/13025 , H01L2224/13099 , H01L2224/16147 , H01L2224/16237 , H01L2224/2919 , H01L2224/81141 , H01L2224/81191 , H01L2224/83121 , H01L2224/83141 , H01L2224/83194 , H01L2224/838 , H01L2224/9202 , H01L2225/06513 , H01L2225/06527 , H01L2225/06541 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01015 , H01L2924/01018 , H01L2924/01019 , H01L2924/01027 , H01L2924/01029 , H01L2924/01033 , H01L2924/01042 , H01L2924/01046 , H01L2924/01047 , H01L2924/0105 , H01L2924/01073 , H01L2924/01074 , H01L2924/01075 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/0132 , H01L2924/0133 , H01L2924/014 , H01L2924/04953 , H01L2924/0665 , H01L2924/14 , H01L2924/00 , H01L2924/01028 , H01L2924/00014
摘要： A three dimensional device stack structure comprises two or more active device and interconnect layers further connected together using through substrate vias. Methods of forming the three dimensional device stack structure comprise alignment, bonding by lamination, thinning and post thinning processing. The via features enable the retention of alignment through the lamination process and any subsequent process steps thus achieving a mechanically more robust stack structure compared to the prior art.
摘要翻译：三维器件堆叠结构包括两个或更多个有源器件和互连层，其通过衬底通孔进一步连接在一起。形成三维器件堆叠结构的方法包括对准，通过层压粘接，变薄和后变薄处理。通孔特征使得能够通过层压工艺和任何后续工艺步骤保持对准，从而与现有技术相比实现机械上更坚固的堆叠结构。

6. 发明授权

US08093099B2 Lock and key through-via method for wafer level 3D integration and structures produced 有权
标题翻译：用于晶圆级3D集成和结构的锁定和键通孔方法
公开(公告)号：US08093099B2
公开(公告)日：2012-01-10
申请号：US12763596
申请日：2010-04-20
申请人： Sampath Purushothaman , Mary E. Rothwell , Ghavam Ghavami Shahidi , Roy Rongqing Yu
发明人： Sampath Purushothaman , Mary E. Rothwell , Ghavam Ghavami Shahidi , Roy Rongqing Yu
IPC分类号： H01L21/768
CPC分类号： H01L21/76898 , H01L21/6835 , H01L23/481 , H01L24/11 , H01L24/12 , H01L24/83 , H01L24/90 , H01L25/0657 , H01L25/50 , H01L27/0688 , H01L27/105 , H01L2221/68377 , H01L2224/1147 , H01L2224/13099 , H01L2224/16147 , H01L2224/16237 , H01L2224/2518 , H01L2224/2919 , H01L2224/81141 , H01L2224/81191 , H01L2224/83121 , H01L2224/83141 , H01L2224/83194 , H01L2224/838 , H01L2224/9202 , H01L2225/06513 , H01L2225/06517 , H01L2225/06541 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01015 , H01L2924/01018 , H01L2924/01019 , H01L2924/01027 , H01L2924/01029 , H01L2924/01033 , H01L2924/01042 , H01L2924/01046 , H01L2924/01047 , H01L2924/0105 , H01L2924/01073 , H01L2924/01074 , H01L2924/01075 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/0132 , H01L2924/0133 , H01L2924/014 , H01L2924/04953 , H01L2924/0665 , H01L2924/14 , H01L2924/00 , H01L2924/01028
摘要： A three dimensional device stack structure comprises two or more active device and interconnect layers further connected together using through substrate vias. Methods of forming the three dimensional device stack structure comprise alignment, bonding by lamination, thinning and post thinning processing. The via features enable the retention of alignment through the lamination process and any subsequent process steps thus achieving a mechanically more robust stack structure compared to the prior art.
摘要翻译：三维器件堆叠结构包括两个或更多个有源器件和互连层，其通过衬底通孔进一步连接在一起。形成三维器件堆叠结构的方法包括对准，通过层压粘接，变薄和后变薄处理。通孔特征使得能够通过层压工艺和任何后续工艺步骤保持对准，从而与现有技术相比实现机械上更坚固的堆叠结构。

7. 发明授权

US06566177B1 Silicon-on-insulator vertical array device trench capacitor DRAM 有权
标题翻译：绝缘体上的垂直阵列器件沟槽电容器DRAM
公开(公告)号：US06566177B1
公开(公告)日：2003-05-20
申请号：US09427257
申请日：1999-10-25
申请人： Carl J. Radens , Gary B. Bronner , Tze-chiang Chen , Bijan Davari , Jack A. Mandelman , Dan Moy , Devendra K. Sadana , Ghavam Ghavami Shahidi , Scott R. Stiffler
发明人： Carl J. Radens , Gary B. Bronner , Tze-chiang Chen , Bijan Davari , Jack A. Mandelman , Dan Moy , Devendra K. Sadana , Ghavam Ghavami Shahidi , Scott R. Stiffler
IPC分类号： H01L2100
CPC分类号： H01L27/10864 , H01L27/1087
摘要： A silicon on insulator (SOI) dynamic random access memory (DRAM) cell and array and method of manufacture. The memory cell includes a trench storage capacitor connected by a self aligned buried strap to a vertical access transistor. A buried oxide layer isolates an SOI layer from a silicon substrate. The trench capacitor is formed in the substrate and the access transistor is formed on a sidewall of the SOI layer. A polysilicon strap connected to the polysilicon plate of the storage capacitor provides a self-aligned contact to the source of the access transistor. Initially, the buried oxide layer is formed in the wafer. Deep trenches are etched, initially just through the SOI layer and the BOX layer. Protective sidewalls are formed in the trenches. Then, the deep trenches are etched into the substrate. The volume in the substrate is expanded to form a bottle shaped trench. A polysilicon capacitor plate is formed in the deep trenches and conductive polysilicon straps are formed in the trenches between the capacitor plates and the SOI sidewalls. Device regions are defined in the wafer and a sidewall gate is formed in the deep trenches. Shallow trenches isolation (STI) is used to isolate and define cells. Bitlines and wordlines are formed on the wafer.
摘要翻译：一种绝缘体上硅（SOI）动态随机存取存储器（DRAM）单元及阵列及其制造方法。存储单元包括通过自对准埋入带连接到垂直存取晶体管的沟槽存储电容器。掩埋氧化层将SOI层与硅衬底隔离。沟槽电容器形成在衬底中，并且存取晶体管形成在SOI层的侧壁上。连接到存储电容器的多晶硅板的多晶硅带提供与存取晶体管的源极的自对准接触。最初，在晶圆中形成掩埋氧化物层。深沟槽被蚀刻，最初刚刚通过SOI层和BOX层。在沟槽中形成保护侧壁。然后，将深沟槽蚀刻到衬底中。衬底中的体积被扩大以形成瓶形沟槽。在深沟槽中形成多晶硅电容器板，并且在电容器板和SOI侧壁之间的沟槽中形成导电多晶硅带。在晶片中限定器件区域，并且在深沟槽中形成侧壁栅极。浅沟槽隔离（STI）用于隔离和定义细胞。在晶片上形成位线和字线。

8. 发明授权

US06426252B1 Silicon-on-insulator vertical array DRAM cell with self-aligned buried strap 失效
标题翻译：绝缘体上的垂直阵列DRAM单元，具有自对准埋地带
公开(公告)号：US06426252B1
公开(公告)日：2002-07-30
申请号：US09427256
申请日：1999-10-25
申请人： Carl J. Radens , Gary B. Bronner , Tze-chiang Chen , Bijan Davari , Jack A. Mandelman , Dan Moy , Devendra K. Sadana , Ghavam Ghavami Shahidi , Scott R. Stiffler
发明人： Carl J. Radens , Gary B. Bronner , Tze-chiang Chen , Bijan Davari , Jack A. Mandelman , Dan Moy , Devendra K. Sadana , Ghavam Ghavami Shahidi , Scott R. Stiffler
IPC分类号： H01L218242
CPC分类号： H01L27/10864 , H01L27/10867 , H01L27/1203
摘要： A silicon on insulator (SOI) dynamic random access memory (DRAM) cell, array and method of manufacture. The memory cell includes a vertical access transistor above a trench storage capacitor in a layered wafer. A buried oxide (BOX) layer formed in a silicon wafer isolates an SOI layer from a silicon substrate. Deep trenches are etched through the upper surface SOI layer, the BOX layer and into the substrate. Each trench capacitor is formed in the substrate and, the access transistor is formed on a sidewall of the SOI layer. Recesses are formed in the BOX layer at the SOI layer. A polysilicon strap recessed in the BOX layer connects each polysilicon storage capacitor plate to a self-aligned contact at the source of the access transistor. Dopant is implanted into the wafer to define device regions. Access transistor gates are formed along the SOI layer sidewalls. Shallow trenches are formed and filled with insulating material to isolate cells from adjacent cells. Wordlines and bitlines are formed to complete the memory array.
摘要翻译：绝缘体上硅（SOI）动态随机存取存储器（DRAM）单元，阵列和制造方法。存储单元包括在分层晶片中的沟槽存储电容器上方的垂直存取晶体管。形成在硅晶片中的掩埋氧化物（BOX）层将SOI层与硅衬底隔离。深沟槽通过上表面SOI层，BOX层蚀刻并进入衬底。每个沟槽电容器形成在衬底中，并且存取晶体管形成在SOI层的侧壁上。在SOI层的BOX层中形成凹部。凹陷在BOX层中的多晶硅带将每个多晶硅存储电容器板连接到存取晶体管的源极处的自对准接触。将掺杂剂注入到晶片中以限定器件区域。存取晶体管栅极沿SOI层侧壁形成。形成浅沟槽并填充绝缘材料以将细胞与相邻细胞分离。形成字词和位线以完成内存数组。

9. 发明申请

US20100200992A1 Lock and Key Through-Via Method for Wafer Level 3D Integration and Structures Produced 有权
标题翻译：用于晶圆级3D集成和结构的锁定和密钥通过方法
公开(公告)号：US20100200992A1
公开(公告)日：2010-08-12
申请号：US12763596
申请日：2010-04-20
申请人： Sampath Purushothaman , Mary E. Rothwell , Ghavam Ghavami Shahidi , Roy Rongqing Yu
发明人： Sampath Purushothaman , Mary E. Rothwell , Ghavam Ghavami Shahidi , Roy Rongqing Yu
IPC分类号： H01L23/522 , H01L21/768
CPC分类号： H01L21/76898 , H01L21/6835 , H01L23/481 , H01L24/11 , H01L24/12 , H01L24/83 , H01L24/90 , H01L25/0657 , H01L25/50 , H01L27/0688 , H01L27/105 , H01L2221/68377 , H01L2224/1147 , H01L2224/13099 , H01L2224/16147 , H01L2224/16237 , H01L2224/2518 , H01L2224/2919 , H01L2224/81141 , H01L2224/81191 , H01L2224/83121 , H01L2224/83141 , H01L2224/83194 , H01L2224/838 , H01L2224/9202 , H01L2225/06513 , H01L2225/06517 , H01L2225/06541 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01015 , H01L2924/01018 , H01L2924/01019 , H01L2924/01027 , H01L2924/01029 , H01L2924/01033 , H01L2924/01042 , H01L2924/01046 , H01L2924/01047 , H01L2924/0105 , H01L2924/01073 , H01L2924/01074 , H01L2924/01075 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/0132 , H01L2924/0133 , H01L2924/014 , H01L2924/04953 , H01L2924/0665 , H01L2924/14 , H01L2924/00 , H01L2924/01028
摘要： A three dimensional device stack structure comprises two or more active device and interconnect layers further connected together using through substrate vias. Methods of forming the three dimensional device stack structure comprise alignment, bonding by lamination, thinning and post thinning processing. The via features enable the retention of alignment through the lamination process and any subsequent process steps thus achieving a mechanically more robust stack structure compared to the prior art.
摘要翻译：三维器件堆叠结构包括两个或更多个有源器件和互连层，其通过衬底通孔进一步连接在一起。形成三维器件堆叠结构的方法包括对准，通过层压粘接，变薄和后变薄处理。通孔特征使得能够通过层压工艺和任何后续工艺步骤保持对准，从而与现有技术相比实现机械上更坚固的堆叠结构。

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