会员体验
专利管家(专利管理)
工作空间(专利管理)
风险监控(情报监控)
数据分析(专利分析)
侵权分析(诉讼无效)
联系我们
交流群
官方交流:
QQ群: 891211   
微信请扫码    >>>
现在联系顾问~
热词
    • 2. 发明授权
    • Shift-add based parallel multiplication
    • 基于Shift-add的并行乘法
    • US07774399B2
    • 2010-08-10
    • US12148515
    • 2008-04-18
    • Gibson Dana ElliotCharles H. Moore
    • Gibson Dana ElliotCharles H. Moore
    • G06F7/52
    • G06F7/582
    • A system for performing parallel multiplication on a plurality of factors. In a binary processor, a first and a second memory have pluralities of bit-positions. The first memory holds a first value as a multiplier that will commonly serve as multiple of the factors, and the second memory holds a second value that is representative of multiple multiplicands that are other of the factors. A multiplier bit-count is determined of the significant bits in the multiplier. And a +* operation is performed with the first value and said second value a quantity of times equaling the multiplier bit-count.
    • 一种用于对多个因素执行并行乘法的系统。 在二进制处理器中,第一和第二存储器具有多个位位置。 第一存储器保持第一值作为通常用作因子的倍数的乘数,并且第二存储器保存代表作为其他因素的多个被乘数的第二值。 确定乘法器中有效位的乘法器位计数。 并且使用第一值和所述第二值执行+ *操作等于乘数位计数的次数。