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1. 发明授权

US07774399B2 Shift-add based parallel multiplication 有权
标题翻译：基于Shift-add的并行乘法
公开(公告)号：US07774399B2
公开(公告)日：2010-08-10
申请号：US12148515
申请日：2008-04-18
申请人： Gibson Dana Elliot , Charles H. Moore
发明人： Gibson Dana Elliot , Charles H. Moore
IPC分类号： G06F7/52
CPC分类号： G06F7/582
摘要： A system for performing parallel multiplication on a plurality of factors. In a binary processor, a first and a second memory have pluralities of bit-positions. The first memory holds a first value as a multiplier that will commonly serve as multiple of the factors, and the second memory holds a second value that is representative of multiple multiplicands that are other of the factors. A multiplier bit-count is determined of the significant bits in the multiplier. And a +* operation is performed with the first value and said second value a quantity of times equaling the multiplier bit-count.
摘要翻译：一种用于对多个因素执行并行乘法的系统。在二进制处理器中，第一和第二存储器具有多个位位置。第一存储器保持第一值作为通常用作因子的倍数的乘数，并且第二存储器保存代表作为其他因素的多个被乘数的第二值。确定乘法器中有效位的乘法器位计数。并且使用第一值和所述第二值执行+ *操作等于乘数位计数的次数。

2. 发明申请

US20090083360A1 Shift-add based parallel multiplication 有权
标题翻译：基于Shift-add的并行乘法
公开(公告)号：US20090083360A1
公开(公告)日：2009-03-26
申请号：US12148515
申请日：2008-04-18
申请人： Gibson Dana Elliot , Charles H. Moore
发明人： Gibson Dana Elliot , Charles H. Moore
IPC分类号： G06F7/523
CPC分类号： G06F7/582
摘要： A system for performing parallel multiplication on a plurality of factors. In a binary processor, a first and a second memory have pluralities of bit-positions. The first memory holds a first value as a multiplier that will commonly serve as multiple of the factors, and the second memory holds a second value that is representative of multiple multiplicands that are other of the factors. A multiplier bit-count is determined of the significant bits in the multiplier. And a +* operation is performed with the first value and said second value a quantity of times equaling the multiplier bit-count.
摘要翻译：一种用于对多个因素执行并行乘法的系统。在二进制处理器中，第一和第二存储器具有多个位位置。第一存储器保持第一值作为通常用作因子的倍数的乘数，并且第二存储器保存代表作为其他因素的多个被乘数的第二值。确定乘法器中有效位的乘法器位计数。并且使用第一值和所述第二值执行+ *操作等于乘数位计数的次数。

3. 发明授权

US09090117B2 Decorative panels with recessed patterns and methods of making the same with a flexible die 有权
标题翻译：具有凹陷图案的装饰面板和使用柔性模具制作相同的方法
公开(公告)号：US09090117B2
公开(公告)日：2015-07-28
申请号：US14346303
申请日：2012-02-22
申请人： Charles H. Moore , Matthew T. Sutton , John E. C. Willham , M. Hoyst Brewster
发明人： Charles H. Moore , Matthew T. Sutton , John E. C. Willham , M. Hoyst Brewster
IPC分类号： B29C43/10 , B44C5/04 , B44C1/24 , B29L31/00 , B29C43/02 , B29C43/36
CPC分类号： B44C5/04 , B29C43/021 , B29C43/10 , B29C2043/3652 , B29L2031/7232 , B29L2031/776 , B44C1/24 , Y10T428/24355
摘要： Implementations of the present invention relate to decorative thermoplastic resin panels, which can include one or more recesses. The recess of the thermoplastic resin panels can have texture or texture patterns that differ from the texture or texture patterns of non-recessed portions or other recesses of the decorative thermoplastic resin panel. Additionally, the present invention relates to a method for forming recesses in thermoplastic panels with a flexible die.
摘要翻译：本发明的实施方案涉及装饰性热塑性树脂板，其可以包括一个或多个凹部。热塑性树脂板的凹部可以具有不同于装饰热塑性树脂板的非凹部或其他凹部的质地或纹理图案的纹理或纹理图案。此外，本发明涉及一种用于在具有柔性模具的热塑性面板中形成凹部的方法。

4. 发明授权

US08468323B2 Clockless computer using a pulse generator that is triggered by an event other than a read or write instruction in place of a clock 失效
标题翻译：使用不同于读取或写入指令而不是时钟的事件触发的脉冲发生器的无时钟计算机
公开(公告)号：US08468323B2
公开(公告)日：2013-06-18
申请号：US13053062
申请日：2011-03-21
申请人： Charles H. Moore , Jeffrey Arthur Fox , John W. Rible
发明人： Charles H. Moore , Jeffrey Arthur Fox , John W. Rible
IPC分类号： G06F15/00 , G06F15/76 , G06F7/38 , G06F1/00
CPC分类号： G06F9/30134 , G06F9/30043 , G06F9/30054 , G06F9/30065 , G06F9/30079 , G06F9/32 , G06F9/325 , G06F9/3885 , G06F9/4486 , G06F15/8023
摘要： A computer array (10) has a plurality of computers (12). The computers (12) communicate with each other asynchronously, and the computers (12) themselves operate in a generally asynchronous manner internally. When one computer (12) attempts to communicate with another it goes to sleep until the other computer (12) is ready to complete the transaction, thereby saving power and reducing heat production. The sleeping computer (12) can be awaiting data or instructions (12). In the case of instructions, the sleeping computer (12) can be waiting to store the instructions or to immediately execute the instructions. In the later case, the instructions are placed in an instruction register (30a) when they are received and executed therefrom, without first placing the instructions first into memory. The instructions can include a micro-loop (100) which is capable of performing a series of operations repeatedly. In one application, the sleeping computer (12) is awakened by an input such that it commences an action that would otherwise have required an interrupt of an otherwise active computer.
摘要翻译：计算机阵列（10）具有多个计算机（12）。计算机（12）以异步方式彼此通信，并且计算机（12）本身以内部的大致异步方式进行操作。当一台计算机（12）尝试与另一台计算机（12）进行通信时，它将进入睡眠状态，直到另一台计算机（12）准备完成交易，从而节省电力并减少热量产生。休眠计算机（12）可以等待数据或指令（12）。在指令的情况下，睡眠计算机（12）可以等待存储指令或者立即执行指令。在后一种情况下，在首先将指令首先置于存储器中之前，将指令置于指令寄存器（30a）中，当它们被接收和执行时，它们被放置在指令寄存器（30a）中。指令可以包括能够重复执行一系列操作的微循环（100）。在一个应用中，休眠计算机（12）被输入唤醒，使得它开始了否则将需要另外活动的计算机的中断的动作。

5. 发明申请

US20120288694A1 RESIN PANELS WITH LARGE DECORATIVE OBJECTS AND METHODS OF MAKING SAME 有权
标题翻译：具有大型装饰物的树脂板及其制造方法
公开(公告)号：US20120288694A1
公开(公告)日：2012-11-15
申请号：US13468633
申请日：2012-05-10
申请人： Guillaume Martin , Charles H. Moore , Matthew T. Sutton
发明人： Guillaume Martin , Charles H. Moore , Matthew T. Sutton
IPC分类号： B32B3/02 , B32B21/08 , B32B7/00
CPC分类号： B32B3/08 , B32B27/08 , B32B2307/412 , Y10T428/18 , Y10T428/183 , Y10T428/2495 , Y10T428/31989
摘要： Implementations of the present invention relate to systems, methods, and apparatus for manufacturing aesthetically pleasing architectural resin panels having a thick three-dimensional interlayer. In particular, at least one implementation includes a layup assembly that includes a decorative interlayer, positioned between resin sheets, that decorative interlayer comprising one or more three-dimensional decorative objects and one or more resin blocks. At least one implementation also includes a single-step lamination or pressing process that uses a combination of heat and pressure to melt the resin sheets and the resin blocks together, forming a decorative resin panel which includes the three-dimensional objects.
摘要翻译：本发明的实施例涉及用于制造具有厚的三维中间层的美观的建筑树脂板的系统，方法和装置。特别地，至少一个实施方案包括铺设组件，其包括位于树脂片之间的装饰性中间层，该装饰中间层包括一个或多个三维装饰物体和一个或多个树脂块。至少一个实施方案还包括使用热和压力的组合将树脂片和树脂块熔化在一起的单步层压或压制方法，形成包括三维物体的装饰性树脂板。

6. 发明授权

US08120938B2 Method and apparatus for arranging multiple processors on a semiconductor chip 失效
标题翻译：用于在半导体芯片上布置多个处理器的方法和装置
公开(公告)号：US08120938B2
公开(公告)日：2012-02-21
申请号：US12148523
申请日：2008-04-18
申请人： Charles H. Moore , Jeffrey Arthur Fox , John W. Rible
发明人： Charles H. Moore , Jeffrey Arthur Fox , John W. Rible
IPC分类号： G11C5/02
CPC分类号： G06F15/8023
摘要： A method and apparatus for connecting multiple cores to form a multi core processor. Each processor is connected to at least two other processors, each of which is a mirror image of the first processor. The processors are connected to form a two dimensional matrix connected by one drop busses.
摘要翻译：一种用于连接多个核以形成多核处理器的方法和装置。每个处理器连接到至少两个其他处理器，每个处理器是第一处理器的镜像。处理器被连接以形成由一个总线连接的二维矩阵。

7. 发明申请

US20110185088A1 Asynchronous computer communication 有权
公开(公告)号：US20110185088A1
公开(公告)日：2011-07-28
申请号：US12932713
申请日：2011-03-04
申请人： Charles H. Moore
发明人： Charles H. Moore
IPC分类号： G06F13/14
CPC分类号： G06F1/3209 , H04L67/10
摘要： A computer array (10) has a plurality of computers (12). The computers (12) communicate with each other asynchronously, and the computers (12) themselves operate in a generally asynchronous manner internally. When one computer (12) attempts to communicate with another it goes to sleep until the other computer (12) is ready to complete the transaction, thereby saving power and reducing heat production. A plurality of read lines (18), write lines (20) and data lines (22) interconnect the computers (12). When one computer (12) sets a read line (18) high and the other computer sets a corresponding write line (20) then data is transferred on the data lines (22). When both the read line (18) and corresponding write line (20) go low this allows both communicating computers (12) to know that the communication is completed. An acknowledge line (72) goes high to restart the computers (12).

8. 发明申请

US20100123570A1 Localized Control Method and Apparatus 审中-公开
标题翻译：本地化控制方法和装置
公开(公告)号：US20100123570A1
公开(公告)日：2010-05-20
申请号：US12338932
申请日：2008-12-18
申请人： Nicholas A. Antonopoulos , F. Eric Saunders , Charles H. Moore
发明人： Nicholas A. Antonopoulos , F. Eric Saunders , Charles H. Moore
IPC分类号： G08B23/00 , H05B37/02
CPC分类号： H05B37/0227
摘要： A zoned interactive control area (10) wherein an architectural space is divided into a plurality of zones (16), each having its own sensor(s) and zone lights (18). The zone lights (18) are controlled by a controller (20) such that there are different lighting levels (55, 57, 59) depending upon whether a zone (16) is occupied, whether an adjacent zone (16)is occupied, whether some other zone (16)is occupied, and the like. A variable control method (50) is adaptable such that fine control and adaptation for special circumstances can be achieved. Other types of devices can also be controlled according to the present inventive method and apparatus.
摘要翻译：一种划分的交互式控制区域（10），其中建筑空间被分成多个区域（16），每个区域具有其自己的传感器和区域光（18）。区域灯（18）由控制器（20）控制，使得根据区域（16）是否被占用，相邻区域（16）是否被占用，是否存在不同的照明级别（55,57,59），是否一些其他区域（16）被占用等等。可变控制方法（50）适应性强，可以实现特殊情况的精细控制和适应。也可以根据本发明的方法和装置来控制其他类型的装置。

9. 发明申请

US20100117880A1 Variable sized aperture window of an analog-to-digital converter 审中-公开
标题翻译：模数转换器的可变尺寸孔径窗口
公开(公告)号：US20100117880A1
公开(公告)日：2010-05-13
申请号：US12462828
申请日：2009-08-10
申请人： Charles H. Moore , Leslie O. Snively , John Huie
发明人： Charles H. Moore , Leslie O. Snively , John Huie
IPC分类号： H03M1/00 , H03M1/12
CPC分类号： H03M1/1245 , H03M1/1215 , H03M1/60
摘要： An improvement in sampling a high frequency input analog signal and converting it to a digital output signal is disclosed. This is accomplished by using a multitude of analog-to-digital converters in conjunction with a distributed sampling system. This combination of multiple converters and a distributed sampling system allows use of conventional device processing, such as that of 0.18 micron silicon, and also provides accurate sampling of very high frequency input signals. The distributed sampling system provides multiple samplings of the input signal by using multiple ADCs for multiple samplings, wherein each sampling is sequentially offset a fixed amount of time from the most recent preceding sampling. Each ADC has a designated central processing unit (CPU) to obtain sufficient data transfer capabilities. The samplings from the multitude of ADCs are a series of sequential digital output values. The digital output values could be the result of samplings all at the same frequency, or at different frequencies. Types of distributed sampling systems include a multitude of elongated trace patterns interconnected in series, a multitude of inverter pairs interconnected in series, a specific permittivity material device, and a sequencer or multiplier. A second enhanced sampling system includes a variable sized aperture window, wherein a width of a sample pulse is narrowed through a variable clock mechanism to produce a faster sampling rate. This variable sized aperture window system can be used by itself, or in combination with any of the presently described multiple ADC distributed sampling systems.
摘要翻译：公开了对高频输入模拟信号进行采样并将其转换为数字输出信号的改进。这是通过使用多个模数转换器与分布式采样系统结合来实现的。多个转换器和分布式采样系统的组合允许使用诸如0.18微米硅的常规器件处理，并且还提供极高频率输入信号的精确采样。分布式采样系统通过对多个采样使用多个ADC来提供输入信号的多次采样，其中每个采样从最近的先前采样顺序地偏移固定的时间量。每个ADC都有一个指定的中央处理单元（CPU），以获得足够的数据传输能力。来自多个ADC的采样是一系列顺序数字输出值。数字输出值可能是以相同频率或不同频率进行采样的结果。分布式采样系统的类型包括串联互连的多个细长迹线图案，串联互连的多个逆变器对，特定介电常数材料器件和定序器或乘法器。第二增强采样系统包括可变大小的孔径窗口，其中采样脉冲的宽度通过可变时钟机构变窄以产生更快的采样率。该可变尺寸的孔径窗系统可以自身使用，或与任何目前描述的多个ADC分布式采样系统组合使用。

10. 发明申请

US20090265524A1 Method and apparatus for arranging multiple processors on a semiconductor chip 失效
标题翻译：用于在半导体芯片上布置多个处理器的方法和装置
公开(公告)号：US20090265524A1
公开(公告)日：2009-10-22
申请号：US12148523
申请日：2008-04-18
申请人： Charles H. Moore , Jeffrey Arthur Fox , John W. Rible
发明人： Charles H. Moore , Jeffrey Arthur Fox , John W. Rible
IPC分类号： G06F15/76 , G06F9/30 , G06F12/00
CPC分类号： G06F15/8023
摘要： A method and apparatus for connecting multiple cores to form a multi core processor. Each processor is connected to at least two other processors, each of which is a mirror image of the first processor. The processors are connected to form a two dimensional matrix connected by one drop busses.
摘要翻译：一种用于连接多个核以形成多核处理器的方法和装置。每个处理器连接到至少两个其他处理器，每个处理器是第一处理器的镜像。处理器被连接以形成由一个总线连接的二维矩阵。

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