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1. 发明授权

US07493131B2 Velocity responsive power control 有权
标题翻译：速度响应功率控制
公开(公告)号：US07493131B2
公开(公告)日：2009-02-17
申请号：US10097039
申请日：2002-03-12
申请人： Gilbert Christopher Sih , Shimman Patel , Thunyachate Ekvetchavit
发明人： Gilbert Christopher Sih , Shimman Patel , Thunyachate Ekvetchavit
IPC分类号： H04B7/00 , H04Q7/20
CPC分类号： H04W52/282 , H04W52/60
摘要： The velocity of a wireless communications device (WCD) (106) is estimated. In response to this estimate a power control command rate is determined. The WCD 106 transmits power control signals to a base station (102) according to the power control command rate. The power control command rate may be determined by mapping the estimated velocity to a velocity range, and selecting a rate that corresponds to the velocity range as the power control command rate. Velocity is estimated by measuring a level crossing rate of a multipath signal.
摘要翻译：估计无线通信设备（WCD）（106）的速度。响应于该估计，确定功率控制命令速率。 WCD 106根据功率控制命令速率向基站（102）发送功率控制信号。功率控制命令速率可以通过将估计的速度映射到速度范围，并且选择与速度范围对应的速率作为功率控制命令速率来确定。通过测量多路径信号的电平穿越率来估计速度。

2. 发明授权

US07116957B2 Velocity responsive filtering for pilot signal reception 有权
标题翻译：用于导频信号接收的速度响应滤波
公开(公告)号：US07116957B2
公开(公告)日：2006-10-03
申请号：US09986222
申请日：2001-10-22
申请人： Gilbert Christopher Sih , Andrew Kan , Stein A. Lundby , Shimman Patel
发明人： Gilbert Christopher Sih , Andrew Kan , Stein A. Lundby , Shimman Patel
IPC分类号： H04B1/06
CPC分类号： H04B1/707 , H04B2201/70701 , H04L2027/0069 , H04L2027/0081
摘要： The velocity of a wireless communications device (106) is estimated. In response to this estimate, a filter bandwidth, such as a pilot filter (310) bandwidth, is adjusted so that the introduction of noise and distortion to a signal received by the device is mitigated. The filter bandwidth is adjusted by increasing it as the estimated velocity increases; and decreasing it as the estimated velocity decreases. Such adjustments may be accomplished through providing a number of predetermined bandwidths that each correspond to a particular velocity range, and setting the filter bandwidth to the predetermined bandwidth that corresponds to the estimated velocity.
摘要翻译：估计无线通信设备（106）的速度。响应于该估计，调整诸如导频滤波器（310）带宽之类的滤波器带宽，以便减轻由设备接收的信号引入噪声和失真。滤波器带宽随着估计速度的增加而增加; 并随着估计速度的降低而减小。这样的调整可以通过提供多个预定带宽来实现，每个预定带宽对应于特定的速度范围，并且将滤波器带宽设置为对应于估计速度的预定带宽。

3. 发明授权

US07023902B2 Apparatus and method for scalable offline CDMA demodulation 有权
标题翻译：用于可缩放离线CDMA解调的装置和方法
公开(公告)号：US07023902B2
公开(公告)日：2006-04-04
申请号：US10007543
申请日：2001-11-06
申请人： Gilbert Christopher Sih , Ziad Mansour
发明人： Gilbert Christopher Sih , Ziad Mansour
IPC分类号： H04K1/00
CPC分类号： H04B1/7117 , H04B2201/70707
摘要： Techniques for scalable CDMA demodulation with maximum response latency are disclosed. In one aspect, a finger timing unit generates signals indicating cycle boundaries for a plurality of fingers, and an offline processing unit processes stored samples for those fingers in response to the signals. In another aspect, incoming samples are stored in a RAM, while finger timing is maintained using a plurality of counters. The RAM address is stored on symbol boundaries. Symbols for each finger are generated in an offline processing unit, clocked at a higher speed than the finger counters, from a RAM location computed using the stored RAM address. Various other aspects are also presented. These aspects provide for decoupling of the chip rate processing from chip time, which allows a single offline processing unit to service a plurality of fingers, thus reducing additional hardware required to support additional fingers while maintaining maximum latency requirements.
摘要翻译：公开了具有最大响应延迟的可扩展CDMA解调技术。一方面，手指定时单元产生指示多个手指的周期边界的信号，并且离线处理单元响应于该信号来处理这些手指的存储样本。在另一方面，输入的样本存储在RAM中，而使用多个计数器保持手指定时。 RAM地址存储在符号边界上。从使用存储的RAM地址计算的RAM位置的离线处理单元生成以比手指计数器更高的速度产生的符号。还提出了各种其他方面。这些方面提供了芯片速率处理与芯片时间的去耦合，这允许单个脱机处理单元为多个指状物提供服务，从而减少支持附加手指所需的附加硬件，同时保持最大等待时间要求。

4. 发明授权

US08626099B2 Direct conversion receiver architecture 有权
标题翻译：直接转换接收机架构
公开(公告)号：US08626099B2
公开(公告)日：2014-01-07
申请号：US11376502
申请日：2006-03-14
申请人： Tao Li , Christian Holenstein , Inyup Kang , Brett C. Walker , Paul E. Peterzell , Raghu Challa , Matthew L. Severson , Arun Raghupathy , Gilbert Christopher Sih
发明人： Tao Li , Christian Holenstein , Inyup Kang , Brett C. Walker , Paul E. Peterzell , Raghu Challa , Matthew L. Severson , Arun Raghupathy , Gilbert Christopher Sih
IPC分类号： H04B1/06
CPC分类号： H03G3/3078 , H03G3/3068 , H03G3/3089
摘要： A direct downconversion receiver architecture having a DC loop to remove DC offset from the signal components, a digital variable gain amplifier (DVGA) to provide a range of gains, an automatic gain control (AGC) loop to provide gain control for the DVGA and RF/analog circuitry, and a serial bus interface (SBI) unit to provide controls for the RF/analog circuitry via a serial bus. The DVGA may be advantageously designed and located as described herein. The operating mode of the VGA loop may be selected based on the operating mode of the DC loop, since these two loops interact with one another. The duration of time the DC loop is operated in an acquisition mode may be selected to be inversely proportional to the DC loop bandwidth in the acquisition mode. The controls for some or all of the RF/analog circuitry may be provided via the serial bus.
摘要翻译：具有用于去除信号分量的DC偏移的DC环路的直接下变频接收机架构，提供一系列增益的数字可变增益放大器（DVGA），用于为DVGA和RF提供增益控制的自动增益控制（AGC）回路 /模拟电路和串行总线接口（SBI）单元，通过串行总线为RF /模拟电路提供控制。可以如本文所述有利地设计和定位DVGA。可以基于DC循环的操作模式来选择VGA循环的操作模式，因为这两个循环彼此相互作用。在采集模式下，DC环路工作的持续时间可以被选择为与采集模式中的DC环路带宽成反比。一些或全部RF /模拟电路的控制可以通过串行总线提供。

5. 发明授权

US08615212B2 Direct conversion receiver architecture 有权
公开(公告)号：US08615212B2
公开(公告)日：2013-12-24
申请号：US11862330
申请日：2007-09-27
申请人： Tao Li , Christian Holenstein , Inyup Kang , Brett C. Walker , Paul E. Peterzell , Raghu Challa , Matthew L. Severson , Arun Raghupathy , Gilbert Christopher Sih
发明人： Tao Li , Christian Holenstein , Inyup Kang , Brett C. Walker , Paul E. Peterzell , Raghu Challa , Matthew L. Severson , Arun Raghupathy , Gilbert Christopher Sih
IPC分类号： H04B7/00
CPC分类号： H03G3/3078 , H03G3/3068 , H03G3/3089
摘要： A direct downconversion receiver architecture having a DC loop to remove DC offset from the signal components, a digital variable gain amplifier (DVGA) to provide a range of gains, an automatic gain control (AGC) loop to provide gain control for the DVGA and RF/analog circuitry, and a serial bus interface (SBI) unit to provide controls for the RF/analog circuitry via a serial bus. The DVGA may be advantageously designed and located as described herein. The operating mode of the VGA loop may be selected based on the operating mode of the DC loop, since these two loops interact with one another. The duration of time the DC loop is operated in an acquisition mode may be selected to be inversely proportional to the DC loop bandwidth in the acquisition mode. The controls for some or all of the RF/analog circuitry may be provided via the serial bus.

6. 发明申请

US20110170611A1 VIDEO ENCODING AND DECODING TECHNIQUES 审中-公开
标题翻译：视频编码和解码技术
公开(公告)号：US20110170611A1
公开(公告)日：2011-07-14
申请号：US13073583
申请日：2011-03-28
申请人： King-Chung Lai , Gilbert Christopher Sih , Chienchung Chang , Anthony Patrick Mauro, II
发明人： King-Chung Lai , Gilbert Christopher Sih , Chienchung Chang , Anthony Patrick Mauro, II
IPC分类号： H04N7/26
CPC分类号： H04N19/43 , H04N19/51 , H04N19/61
摘要： This disclosure describes video encoding techniques capable of reducing the number of processing cycles and memory transfers necessary to encode a video sequence. In this manner, the disclosed video encoding techniques may increase video encoding speed and reduce power consumption. In general, the video encoding techniques make use of a candidate memory that stores video blocks in columns corresponding to a search space for a motion estimation routine. A memory control unit addresses the candidate memory to retrieve multiple pixels in parallel for simultaneous comparison to pixels in a video block to be encoded, e.g., using Sum of Absolute Difference (SAD) or Sum of Squared Difference (SSD) techniques. A difference processor performs the parallel calculations. In addition, for subsequent video blocks to be encoded, the candidate memory can be incrementally updated by loading a new column of video blocks, rather than reloading the entire search space.
摘要翻译：本公开描述了能够减少编码视频序列所需的处理周期数量和存储器传输的视频编码技术。以这种方式，所公开的视频编码技术可以增加视频编码速度并降低功耗。通常，视频编码技术利用将视频块存储在与用于运动估计例程的搜索空间相对应的列中的候选存储器。存储器控制单元寻址候选存储器以并行检索多个像素，以便与要编码的视频块中的像素同时比较，例如使用绝对差值（SAD）或平方和（SSD）技术求和。差分处理器执行并行计算。此外，对于要编码的后续视频块，可以通过加载新的视频块列来递增地更新候选存储器，而不是重新加载整个搜索空间。

7. 发明授权

US07769950B2 Cached memory system and cache controller for embedded digital signal processor 有权
标题翻译：用于嵌入式数字信号处理器的缓存存储系统和缓存控制器
公开(公告)号：US07769950B2
公开(公告)日：2010-08-03
申请号：US10807648
申请日：2004-03-24
申请人： Gilbert Christopher Sih , Charles E. Sakamaki , De D. Hsu , Jian Wei , Richard Higgins
发明人： Gilbert Christopher Sih , Charles E. Sakamaki , De D. Hsu , Jian Wei , Richard Higgins
IPC分类号： G06F12/00
CPC分类号： G06F12/0811 , G06F12/08 , G06F12/0857 , G06F12/0897 , G06F2212/251 , G06F2212/253
摘要： A cached memory system that can handle high-rate input data and ensure that an embedded DSP can meet real-time constraints is described. The cached memory system includes a cache memory located close to a processor core, an on-chip memory at the next higher memory level, and an external main memory at the topmost memory level. A cache controller handles paging of instructions and data between the cache memory and the on-chip memory for cache misses. A direct memory exchange (DME) controller handles user-controlled paging between the on-chip memory and the external memory. A user/programmer can arrange to have the instructions and data required by the processor core to be present in the on-chip memory well in advance of when they are actually needed by the processor core.
摘要翻译：描述了可以处理高速率输入数据并确保嵌入式DSP能够满足实时约束的高速缓存存储器系统。缓存的存储器系统包括位于处理器核心附近的高速缓存存储器，处于下一较高存储器级别的片上存储器以及最高存储器级别的外部主存储器。缓存控制器处理高速缓冲存储器和片上存储器之间的指令和数据的分页用于高速缓存未命中。直接存储交换（DME）控制器处理片上存储器和外部存储器之间的用户控制的寻呼。用户/程序员可以安排在处理器核心实际需要之前将处理器核心所需的指令和数据存储在片上存储器中。

8. 发明授权

US07076225B2 Variable gain selection in direct conversion receiver 失效
标题翻译：直接转换接收机中的可变增益选择
公开(公告)号：US07076225B2
公开(公告)日：2006-07-11
申请号：US10034734
申请日：2001-12-21
申请人： Tao Li , Christian Holenstein , Inyup Kang , Brett C. Walker , Paul E. Peterzell , Raghu Challa , Matthew L. Severson , Arun Raghupathy , Gilbert Christopher Sih
发明人： Tao Li , Christian Holenstein , Inyup Kang , Brett C. Walker , Paul E. Peterzell , Raghu Challa , Matthew L. Severson , Arun Raghupathy , Gilbert Christopher Sih
IPC分类号： H04B7/00
CPC分类号： H03G3/3078 , H03G3/3068 , H03G3/3089
摘要： A direct downconversion receiver architecture having a DC loop to remove DC offset from the signal components, a digital variable gain amplifier (DVGA) to provide a range of gains, an automatic gain control (AGC) loop to provide gain control for the DVGA and RF/analog circuitry, and a serial bus interface (SBI) unit to provide controls for the RF/analog circuitry via a serial bus. The DVGA may be advantageously designed and located as described herein. The operating mode of the VGA loop may be selected based on the operating mode of the DC loop, since these two loops interact with one another. The duration of time the DC loop is operated in an acquisition mode may be selected to be inversely proportional to the DC loop bandwidth in the acquisition mode. The controls for some or all of the RF/analog circuitry may be provided via the serial bus.
摘要翻译：具有用于去除信号分量的DC偏移的DC环路的直接下变频接收机架构，提供一系列增益的数字可变增益放大器（DVGA），用于为DVGA和RF提供增益控制的自动增益控制（AGC）回路 /模拟电路和串行总线接口（SBI）单元，通过串行总线为RF /模拟电路提供控制。可以如本文所述有利地设计和定位DVGA。可以基于DC循环的操作模式来选择VGA循环的操作模式，因为这两个循环彼此相互作用。在采集模式下，DC环路工作的持续时间可以被选择为与采集模式中的DC环路带宽成反比。一些或全部RF /模拟电路的控制可以通过串行总线提供。

9. 发明授权

US08316185B2 Cached memory system and cache controller for embedded digital signal processor 有权
标题翻译：用于嵌入式数字信号处理器的缓存存储系统和缓存控制器
公开(公告)号：US08316185B2
公开(公告)日：2012-11-20
申请号：US12792865
申请日：2010-06-03
申请人： Gilbert Christopher Sih , Charles E. Sakamaki , De D. Hsu , Jian Wei , Richard Higgins
发明人： Gilbert Christopher Sih , Charles E. Sakamaki , De D. Hsu , Jian Wei , Richard Higgins
IPC分类号： G06F12/00
CPC分类号： G06F12/0811 , G06F12/08 , G06F12/0857 , G06F12/0897 , G06F2212/251 , G06F2212/253
摘要： A cached memory system that can handle high-rate input data and ensure that an embedded DSP can meet real-time constraints is described. The cached memory system includes a cache memory located close to a processor core, an on-chip memory at the next higher memory level, and an external main memory at the topmost memory level. A cache controller handles paging of instructions and data between the cache memory and the on-chip memory for cache misses. A direct memory exchange (DME) controller handles user-controlled paging between the on-chip memory and the external memory. A user/programmer can arrange to have the instructions and data required by the processor core to be present in the on-chip memory well in advance of when they are actually needed by the processor core.
摘要翻译：描述了可以处理高速率输入数据并确保嵌入式DSP能够满足实时约束的高速缓存存储器系统。缓存的存储器系统包括位于处理器核心附近的高速缓存存储器，处于下一较高存储器级别的片上存储器以及最高存储器级别的外部主存储器。缓存控制器处理高速缓冲存储器和片上存储器之间的指令和数据的分页用于高速缓存未命中。直接存储交换（DME）控制器处理片上存储器和外部存储器之间的用户控制的寻呼。用户/程序员可以安排在处理器核心实际需要之前将处理器核心所需的指令和数据存储在片上存储器中。

10. 发明授权

US07940844B2 Video encoding and decoding techniques 有权
标题翻译：视频编码和解码技术
公开(公告)号：US07940844B2
公开(公告)日：2011-05-10
申请号：US10371793
申请日：2003-02-21
申请人： King-Chung Lai , Gilbert Christopher Sih , Chienchung Chang , Anthony Patrick Mauro, II
发明人： King-Chung Lai , Gilbert Christopher Sih , Chienchung Chang , Anthony Patrick Mauro, II
IPC分类号： H04N7/12
CPC分类号： H04N19/43 , H04N19/51 , H04N19/61
摘要： This disclosure describes video encoding techniques capable of reducing the number of processing cycles and memory transfers necessary to encode a video sequence. In this manner, the disclosed video encoding techniques may increase video encoding speed and reduce power consumption. In general, the video encoding techniques make use of a candidate memory that stores video blocks in columns corresponding to a search space for a motion estimation routine. A memory control unit addresses the candidate memory to retrieve multiple pixels in parallel for simultaneous comparison to pixels in a video block to be encoded, e.g., using Sum of Absolute Difference (SAD) or Sum of Squared Difference (SSD) techniques. A difference processor performs the parallel calculations. In addition, for subsequent video blocks to be encoded, the candidate memory can be incrementally updated by loading a new column of video blocks, rather than reloading the entire search space.
摘要翻译：本公开描述了能够减少编码视频序列所需的处理周期数量和存储器传输的视频编码技术。以这种方式，所公开的视频编码技术可以增加视频编码速度并降低功耗。通常，视频编码技术利用将视频块存储在与用于运动估计例程的搜索空间相对应的列中的候选存储器。存储器控制单元寻址候选存储器以并行检索多个像素，以便与要编码的视频块中的像素同时比较，例如使用绝对差值（SAD）或平方和差（SSD）技术。差分处理器执行并行计算。此外，对于要编码的后续视频块，可以通过加载新的视频块列来递增地更新候选存储器，而不是重新加载整个搜索空间。

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