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1. 发明授权

US09632782B2 Method and apparatus to process SHA-2 secure hashing algorithm 有权
公开(公告)号：US09632782B2
公开(公告)日：2017-04-25
申请号：US13976274
申请日：2012-03-30
申请人： Kirk S. Yap , Gilbert M. Wolrich , James D. Guilford , Vinodh Gopal , Erdinc Ozturk , Sean M. Gulley , Wajdi K. Feghali , Martin G. Dixon
发明人： Kirk S. Yap , Gilbert M. Wolrich , James D. Guilford , Vinodh Gopal , Erdinc Ozturk , Sean M. Gulley , Wajdi K. Feghali , Martin G. Dixon
IPC分类号： G06F9/30 , G06F21/60 , H04L9/06 , H04L9/32
CPC分类号： G06F9/3016 , G06F9/30007 , G06F9/30036 , G06F9/30058 , G06F9/30098 , G06F9/30145 , G06F9/3802 , G06F9/384 , G06F12/0875 , G06F12/0897 , G06F12/1027 , G06F15/8007 , G06F21/602 , G06F2212/452 , G06F2212/68 , H04L9/0643 , H04L9/3239 , H04L2209/125
摘要： A processor includes an instruction decoder to receive a first instruction to process a secure hash algorithm 2 (SHA-2) hash algorithm, the first instruction having a first operand associated with a first storage location to store a SHA-2 state and a second operand associated with a second storage location to store a plurality of messages and round constants. The processor further includes an execution unit coupled to the instruction decoder to perform one or more iterations of the SHA-2 hash algorithm on the SHA-2 state specified by the first operand and the plurality of messages and round constants specified by the second operand, in response to the first instruction.

2. 发明申请

US20160285472A1 Systems, Methods, and Apparatuses for Decompression using Hardware and Software 有权
标题翻译：使用硬件和软件解压缩的系统，方法和设备
公开(公告)号：US20160285472A1
公开(公告)日：2016-09-29
申请号：US14671462
申请日：2015-03-27
申请人： Vinodh GOPAL , James D. GUILFORD , Kirk S. YAP , Sean M. GULLEY , Gilbert M. WOLRICH
发明人： Vinodh GOPAL , James D. GUILFORD , Kirk S. YAP , Sean M. GULLEY , Gilbert M. WOLRICH
IPC分类号： H03M7/30
CPC分类号： H03M7/3086 , H03M7/30 , H03M7/46
摘要： Detailed herein are embodiments of systems, methods, and apparatuses for decompression using hardware and software. For example, in embodiment a hardware apparatus comprises an input buffer to store incoming data from a compressed stream, a selector to select at least one byte stored in the input buffer, a decoder to decode the selected at least one byte and determine if the decoded at least one byte is a literal or a symbol, an overlap condition, a size of a record from the decoded stream, a length value of the data to be retrieved from the decoded stream, and an offset value for the decoded data, and a token format converter to convert the decoded data and data from source and destination offset base registers into a fixed-length token.
摘要翻译：这里详细描述了使用硬件和软件进行解压缩的系统，方法和装置的实施例。例如，在实施例中，硬件装置包括用于存储来自压缩流的输入数据的输入缓冲器，选择器以选择存储在输入缓冲器中的至少一个字节，解码器来解码所选择的至少一个字节并确定是否解码至少一个字节是文字或符号，重叠条件，来自解码流的记录的大小，要从解码流中检索的数据的长度值和解码数据的偏移值，以及令牌格式转换器将解码的数据和数据从源和目标偏移基址寄存器转换为固定长度的令牌。

3. 发明授权

US09292548B2 Digest generation 有权
标题翻译：消化一代
公开(公告)号：US09292548B2
公开(公告)日：2016-03-22
申请号：US13995236
申请日：2011-11-01
申请人： Vinodh Gopal , James D. Guilford , Schuyler Eldridge , Gilbert M. Wolrich , Erdinc Ozturk , Wajdi K. Feghali
发明人： Vinodh Gopal , James D. Guilford , Schuyler Eldridge , Gilbert M. Wolrich , Erdinc Ozturk , Wajdi K. Feghali
IPC分类号： G06F17/30
CPC分类号： G06F17/30303 , G06F17/30306 , G06F17/3033
摘要： In one embodiment, circuitry may generate digests to be combined to produce a hash value. The digests may include at least one digest and at least one other digest generated based at least in part upon at least one CRC value and at least one other CRC value. The circuitry may include cyclical redundancy check (CRC) generator circuitry to generate the at least one CRC value based at least in part upon at least one input string. The CRC generator circuitry also may generate the at least one other CRC value based least in part upon at least one other input string. The at least one other input string resulting at least in part from at least one pseudorandom operation involving, at least in part, the at least one input string. Many modifications, variations, and alternatives are possible without departing from this embodiment.
摘要翻译：在一个实施例中，电路可以生成待组合的摘要以产生散列值。摘要可以至少部分地基于至少一个CRC值和至少一个其它CRC值来生成至少一个摘要和至少一个其他摘要。电路可以包括循环冗余校验（CRC）发生器电路，以至少部分地基于至少一个输入串来生成至少一个CRC值。 CRC发生器电路还可以至少部分地基于至少一个其他输入串来生成至少一个其它CRC值。所述至少一个其他输入字符串至少部分地由至少一个涉及至少一个输入字符串的伪随机操作产生。在不脱离本实施例的情况下，可以进行许多修改，变型和替换。

4. 发明授权

US09092645B2 Efficient multiplication, exponentiation and modular reduction implementations 有权
标题翻译：有效的乘法，乘法和模块化削减实现
公开(公告)号：US09092645B2
公开(公告)日：2015-07-28
申请号：US13994782
申请日：2011-12-05
申请人： Erdinc Ozturk , Vinodh Gopal , Gilbert M. Wolrich , Wajdi K. Feghali , James D. Guilford , Deniz Karakoyunlu , Martin G. Dixon , Kahraman D. Akdemir
发明人： Erdinc Ozturk , Vinodh Gopal , Gilbert M. Wolrich , Wajdi K. Feghali , James D. Guilford , Deniz Karakoyunlu , Martin G. Dixon , Kahraman D. Akdemir
IPC分类号： H04L29/00 , G06F21/71 , H04L9/30
CPC分类号： G06F21/71 , G06F7/723 , H04L9/3006 , H04L2209/12
摘要： In one embodiment, the present disclosure provides a method that includes segmenting an n-bit exponent e into a first segment et and a number t of k-bit segments ei in response to a request to determine a modular exponentiation result R, wherein R is a modular exponentiation of a generator base g for the exponent e and a q-bit modulus m, wherein the generator base g equals two and k is based at least in part on a processor configured to determine the result R; iteratively determining a respective intermediate modular exponentiation result for each segment ei, wherein the determining comprises multiplication, exponentiation and a modular reduction of at least one of a multiplication result and an exponentiation result; and generating the modular exponentiation result R=ge mod m based on, at least in part, at least one respective intermediate modular exponentiation result.
摘要翻译：在一个实施例中，本公开提供了一种方法，其包括响应于确定模幂运算结果R的请求，将n位指数e分割成第一段et和数目t的k比特段ei，其中R是指数e的发生器基数g和q位模数m的模幂运算，其中发生器基g等于2，并且k至少部分地基于被配置为确定结果R的处理器; 迭代地确定每个段ei的相应的中间模幂运算结果，其中所述确定包括相乘结果和求幂结果中的至少一个的乘法，乘法和模块化减少; 并且至少部分地基于至少一个相应的中间模幂运算结果来产生模幂运算结果R = ge mod m。

5. 发明申请

US20150169472A1 USING A MEMORY ADDRESS TO FORM A TWEAK KEY TO USE TO ENCRYPT AND DECRYPT DATA 有权
标题翻译：使用存储器地址形成一个用于加密和分解数据的双重密钥
公开(公告)号：US20150169472A1
公开(公告)日：2015-06-18
申请号：US14105061
申请日：2013-12-12
申请人： Kirk S. YAP , Gilbert M. WOLRICH , Vinodh GOPAL , Wajdi K. FEGHALI
发明人： Kirk S. YAP , Gilbert M. WOLRICH , Vinodh GOPAL , Wajdi K. FEGHALI
IPC分类号： G06F12/14
CPC分类号： G06F12/1408 , G06F12/1466 , G06F2212/1052
摘要： Provided are a memory system, memory controller, and method for using a memory address to form a tweak key to use to encrypt and decrypt data. A base tweak co is generated as a function of an address of a block of data in the memory storage. For each sub-block of the block, performing: processing the base tweak to determine a sub-block tweak; combining the sub-block tweak with the sub-block to produce a modified sub-block; and performing an encryption operation comprising one of encryption or decryption on the modified sub-block to produce sub-block output comprising one of encrypted data and unencrypted data for the sub-block.
摘要翻译：提供了一种用于使用存储器地址形成用于加密和解密数据的调整密钥的存储器系统，存储器控制器和方法。作为存储器存储器中的数据块的地址的函数产生基本调整co。对于块的每个子块，执行：处理基本调整以确定子块调整; 将子块调整与子块组合以产生修改的子块; 并且对所述修改的子块执行包括加密或解密之一的加密操作，以产生包括所述子块的加密数据和未加密数据之一的子块输出。

6. 发明申请

US20150082047A1 EFFICIENT MULTIPLICATION, EXPONENTIATION AND MODULAR REDUCTION IMPLEMENTATIONS 有权
标题翻译：有效的实施，授权和模块化的减少实施
公开(公告)号：US20150082047A1
公开(公告)日：2015-03-19
申请号：US13994782
申请日：2011-12-05
申请人： Vinodh Gopal , Gilbert M. Wolrich , Wajdi K. Feghali , James D. Guilford , Deniz Karakoyunlu , Martin G. Dixon , Kahraman D. Akdemir
发明人： Erdinc Ozturk , Vinodh Gopal , Gilbert M. Wolrich , Wajdi K. Feghali , James D. Guilford , Deniz Karakoyunlu , Martin G. Dixon , Kahraman D. Akdemir
IPC分类号： G06F21/71 , H04L9/30
CPC分类号： G06F21/71 , G06F7/723 , H04L9/3006 , H04L2209/12
摘要： In one embodiment, the present disclosure provides a method that includes segmenting an n-bit exponent e into a first segment et and a number t of k-bit segments ei in response to a request to determine a modular exponentiation result R, wherein R is a modular exponentiation of a generator base g for the exponent e and a q-bit modulus m, wherein the generator base g equals two and k is based at least in part on a processor configured to determine the result R; iteratively determining a respective intermediate modular exponentiation result for each segment ei, wherein the determining comprises multiplication, exponentiation and a modular reduction of at least one of a multiplication result and an exponentiation result; and generating the modular exponentiation result R=ge mod m based on, at least in part, at least one respective intermediate modular exponentiation result.
摘要翻译：在一个实施例中，本公开提供了一种方法，其包括响应于确定模幂运算结果R的请求，将n位指数e分割成第一段et和数目t的k比特段ei，其中R是指数e的发生器基数g和q位模数m的模幂运算，其中发生器基g等于2，并且k至少部分地基于被配置为确定结果R的处理器; 迭代地确定每个段ei的相应的中间模幂运算结果，其中所述确定包括相乘结果和求幂结果中的至少一个的乘法，乘法和模块化减少; 并且至少部分地基于至少一个相应的中间模幂运算结果来产生模幂运算结果R = ge mod m。

7. 发明授权

US08953785B2 Instruction set for SKEIN256 SHA3 algorithm on a 128-bit processor 有权
标题翻译： 128位处理器上的SKEIN256 SHA3算法指令集
公开(公告)号：US08953785B2
公开(公告)日：2015-02-10
申请号：US13631143
申请日：2012-09-28
申请人： Gilbert M. Wolrich , Kirk S. Yap , Vinodh Gopal
发明人： Gilbert M. Wolrich , Kirk S. Yap , Vinodh Gopal
IPC分类号： H04L9/28
CPC分类号： H04L9/0643 , G06F9/30007 , G06F9/30032 , G06F9/30036
摘要： According to one embodiment, a processor includes an instruction decoder to receive a first instruction to perform first SKEIN256 MIX-PERMUTE operations, the first instruction having a first operand associated with a first storage location to store a plurality of odd words, a second operand associated with a second storage location to store a plurality of even words, and a third operand. The processor further includes a first execution unit coupled to the instruction decoder, in response to the first instruction, to perform multiple rounds of the first SKEIN256 MIX-PERMUTE operations based on the odd words and even words using a first rotate value obtained from a third storage location indicated by the third operand, and to store new odd words in the first storage location indicated by the first operand.
摘要翻译：根据一个实施例，处理器包括指令解码器，用于接收执行第一SKEIN256 MIX-PERMUTE操作的第一指令，所述第一指令具有与第一存储位置相关联的第一操作数，以存储多个奇数字，第二操作数相关联具有存储多个偶数字的第二存储位置和第三操作数。处理器还包括响应于第一指令而耦合到指令解码器的第一执行单元，使用从第三指令获得的第一旋转值，基于奇数字和偶数字进行第一SKEIN256 MIX-PERMUTE操作的多轮由第三操作数指示的存储位置，并将新的奇数字存储在由第一操作数指示的第一存储位置中。

8. 发明申请

US20140237218A1 SIMD INTEGER MULTIPLY-ACCUMULATE INSTRUCTION FOR MULTI-PRECISION ARITHMETIC 有权
标题翻译：用于多精度算术的SIMD整数多项式累积指令
公开(公告)号：US20140237218A1
公开(公告)日：2014-08-21
申请号：US13992728
申请日：2011-12-19
申请人： Vinodh Gopal , Gilbert M. Wolrich , Erdinc Ozturk , James D. Guilford , Kirk S. Yap , Sean M. Gulley , wajdi K. Feghali , Martin G. Dixon
发明人： Vinodh Gopal , Gilbert M. Wolrich , Erdinc Ozturk , James D. Guilford , Kirk S. Yap , Sean M. Gulley , wajdi K. Feghali , Martin G. Dixon
IPC分类号： G06F9/30
CPC分类号： G06F9/3001 , G06F9/30036 , G06F9/30101 , G06F9/3893
摘要： A multiply-and-accumulate (MAC) instruction allows efficient execution of unsigned integer multiplications. The MAC instruction indicates a first vector register as a first operand, a second vector register as a second operand, and a third vector register as a destination. The first vector register stores a first factor, and the second vector register stores a partial sum. The MAC instruction is executed to multiply the first factor with an implicit second factor to generate a product, and to add the partial sum to the product to generate a result. The first factor, the implicit second factor and the partial sum have a same data width and the product has twice the data width. The most significant half of the result is stored in the third vector register, and the least significant half of the result is stored in the second vector register.
摘要翻译：乘法和累加（MAC）指令允许有效执行无符号整数乘法。 MAC指令表示作为第一操作数的第一向量寄存器，作为第二操作数的第二向量寄存器和作为目的地的第三向量寄存器。第一向量寄存器存储第一因子，第二向量寄存器存储部分和。执行MAC指令以将第一因子与隐式第二因子相乘以生成乘积，并将部分和添加到乘积以生成结果。第一个因素，隐含的第二个因子和部分和具有相同的数据宽度，产品的数据宽度是两倍。结果的最大一半存储在第三向量寄存器中，结果的最低有效半存储在第二向量寄存器中。

9. 发明申请

US20140189290A1 INSTRUCTION FOR FAST ZUC ALGORITHM PROCESSING 有权
标题翻译：用于快速ZUC算法处理的指令
公开(公告)号：US20140189290A1
公开(公告)日：2014-07-03
申请号：US13730230
申请日：2012-12-28
申请人： Gilbert M. Wolrich , Vinodh Gopal , Kirk S. Yap , Wajdi K. Feghali
发明人： Gilbert M. Wolrich , Vinodh Gopal , Kirk S. Yap , Wajdi K. Feghali
IPC分类号： G06F15/76
CPC分类号： G06F9/3867 , G06F9/30007 , G06F9/30036 , G06F9/3005 , G06F9/30098 , G06F15/8007 , G09C1/00 , H04L9/0662 , H04L2209/125
摘要： Vector instructions for performing ZUC stream cipher operations are received and executed by the execution circuitry of a processor. The execution circuitry receives a first vector instruction to perform an update to a liner feedback shift register (LFSR), and receives a second vector instruction to perform an update to a state of a finite state machine (FSM), where the FSM receives inputs from re-ordered bits of the LFSR. The execution circuitry executes the first vector instruction and the second vector instruction in a single-instruction multiple data (SIMD) pipeline.
摘要翻译：用于执行ZUC流密码操作的矢量指令由处理器的执行电路接收和执行。执行电路接收第一向量指令以对线性反馈移位寄存器（LFSR）进行更新，并且接收第二向量指令以对有限状态机（FSM）的状态进行更新，其中FSM接收来自重新排列了LFSR的位。执行电路在单指令多数据（SIMD）流水线中执行第一向量指令和第二向量指令。

10. 发明申请

US20140093069A1 INSTRUCTION SET FOR MESSAGE SCHEDULING OF SHA256 ALGORITHM 有权
标题翻译： SHA256算法的消息调度指令集
公开(公告)号：US20140093069A1
公开(公告)日：2014-04-03
申请号：US13631165
申请日：2012-09-28
申请人： Gilbert M. Wolrich , Kirk S. Yap , James D. Guilford , Vinodh Gopal , Sean M. Gulley
发明人： Gilbert M. Wolrich , Kirk S. Yap , James D. Guilford , Vinodh Gopal , Sean M. Gulley
IPC分类号： H04L9/28
CPC分类号： G09C1/00 , G06F9/30007 , H04L9/0643 , H04L2209/125
摘要： A processor includes a first execution unit to receive and execute a first instruction to process a first part of secure hash algorithm 256 (SHA256) message scheduling operations, the first instruction having a first operand associated with a first storage location to store a first set of message inputs and a second operand associated with a second storage location to store a second set of message inputs. The processor further includes a second execution unit to receive and execute a second instruction to process a second part of the SHA256 message scheduling operations, the second instruction having a third operand associated with a third storage location to store an intermediate result of the first part and a third set of message inputs and a fourth operand associated with a fourth storage location to store a fourth set of message inputs.
摘要翻译：处理器包括第一执行单元，用于接收和执行第一指令以处理安全散列算法256（SHA256）消息调度操作的第一部分，所述第一指令具有与第一存储位置相关联的第一操作数，以存储第一组消息输入和与第二存储位置相关联的第二操作数，以存储第二组消息输入。所述处理器还包括第二执行单元，用于接收和执行用于处理所述SHA256消息调度操作的第二部分的第二指令，所述第二指令具有与第三存储位置相关联的第三操作数，以存储所述第一部分的中间结果;以及第三组消息输入和与第四存储位置相关联的第四操作数，以存储第四组消息输入。

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