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1. 发明授权

US10790855B2 Method and device for error correction coding based on high-rate Generalized Concatenated Codes 有权
公开(公告)号：US10790855B2
公开(公告)日：2020-09-29
申请号：US16395046
申请日：2019-04-25
申请人： HYPERSTONE GMBH
发明人： Juergen Freudenberger , Jens Spinner , Christoph Baumhof
IPC分类号： H03M13/00 , H03M13/25 , G11C29/52 , H03M13/29 , H03M13/15
摘要： Field error correction coding is particularly suitable for applications in non-volatile flash memories. We describe a method for error correction encoding of data to be stored in a memory device, a corresponding method for decoding a codeword matrix resulting from the encoding method, a coding device, and a computer program for performing the methods on the coding device, using a new construction for high-rate generalized concatenated (GC) codes. The codes, which are well suited for error correction in flash memories for high reliability data storage, are constructed from inner nested binary Bose-Chaudhuri-Hocquenghem (BCH) codes and outer codes, preferably Reed-Solomon (RS) codes. For the inner codes extended BCH codes are used, where only single parity-check codes are applied in the first level of the GC code. This enables high-rate codes.

2. 发明申请

US20150286526A1 METHOD FOR RENEWING DATA IN ORDER TO INCREASE THE RELIABILITY OF FLASH MEMORIES 有权
标题翻译：用于更新数据的方法以增加闪存的可靠性
公开(公告)号：US20150286526A1
公开(公告)日：2015-10-08
申请号：US14493391
申请日：2014-09-23
申请人： HYPERSTONE GMBH
发明人： MARTIN ROEDER , CHRISTOPH BAUMHOF , AXEL MEHNERT , FRANZ SCHMIDBERGER
IPC分类号： G06F11/10 , G11C29/52
CPC分类号： G06F11/1068 , G11C29/42 , G11C29/52 , G11C2029/0409 , G11C2029/0411
摘要： A method renews data in a flash memory which is organized in memory units and whose memory units which have been written to are error-protected using ECC words. The memory units which have been written to are test-read in regularly activated test-reading cycles, and either individual memory units which have been written to or all memory units which have been written to are renewed on the basis of the ECC error states which have occurred in a test-reading cycle.
摘要翻译：一种方法更新闪存中的数据，闪速存储器被组织在存储器单元中，并且已经写入的存储器单元使用ECC字进行错误保护。已写入的存储器单元在定期激活的测试读取周期中进行测试读取，并且已经写入的单个存储器单元或已写入的所有存储器单元基于ECC错误状态被更新发生在测试阅读周期。

3. 发明申请

US20150212935A1 METHOD FOR RELIABLY ADDRESSING A LARGE FLASH MEMORY AND FLASH MEMORY 有权
标题翻译：用于可靠地寻址大容量存储器和闪速存储器的方法
公开(公告)号：US20150212935A1
公开(公告)日：2015-07-30
申请号：US14305376
申请日：2014-06-16
申请人： HYPERSTONE GMBH
发明人： MARTIN ROEDER , THOMAS SEIDEL
IPC分类号： G06F12/02 , G06F12/08 , G06F12/06
CPC分类号： G06F12/0246 , G06F2212/65 , G06F2212/7201
摘要： A flash memory for a host system has a multiplicity of memory blocks. The memory blocks are subdivided into memory pages which can be written to and each memory page are also subdivided into partial pages and each partial page having a physical partial page address which is assigned a logical partial page address which can be addressed. The physical partial page addresses assigned to the logical partial page addresses are able to be determined using hierarchically organized structures of address tables for converting logical partial page addresses into physical partial page addresses. The multiplicity of memory blocks of the flash memory are divided into areas which comprise at least one static area of memory blocks which have been written to, a write area to which new and changed useful data are written, a block management area which stores management data for the memory blocks, and a logbook area.
摘要翻译：用于主机系统的闪存具有多个存储器块。存储器块被细分为可写入的存储器页，并且每个存储器页也被细分为部分页，并且每个部分页具有被分配有可寻址的逻辑部分页地址的物理部分页地址。分配给逻辑部分页面地址的物理部分页面地址能够使用用于将逻辑部分页面地址转换为物理部分页面地址的地址表的层次组织结构来确定。闪速存储器的多个存储块被划分为包括写入到存储块的至少一个静态区域的区域，写入新的和改变的有用数据的写入区域，存储管理数据的块管理区域用于内存块和日志区域。

4. 发明授权

US11231854B2 Methods and apparatus for estimating the wear of a non-volatile memory 有权
公开(公告)号：US11231854B2
公开(公告)日：2022-01-25
申请号：US16722178
申请日：2019-12-20
申请人： HYPERSTONE GMBH
发明人： Steffen Allert , Martin Roeder , Christoph Baumhof
IPC分类号： G06F3/06
摘要： Some embodiments relate to a method and a corresponding apparatus for estimating the wear of a non-volatile memory. Such a method may include determining a load profile with respect to a real access load occurring during a defined test period where the load profile indicates a respectively associated access load for accesses to a first NVM, and generating access data representing the determined load profile. The method further includes determining an estimated value for the wear of a particular second NVM in part on the basis of the access data.

5. 发明申请

US20190268023A1 Method and Device for Error Correction Coding Based on High-Rate Generalized Concatenated Codes 审中-公开
公开(公告)号：US20190268023A1
公开(公告)日：2019-08-29
申请号：US16395046
申请日：2019-04-25
申请人： HYPERSTONE GMBH
发明人： Juergen Freudenberger , Jens Spinner , Christoph Baumhof
IPC分类号： H03M13/25 , H03M13/29 , G11C29/52 , H03M13/15
摘要： Field error correction coding is particularly suitable for applications in non-volatile flash memories. We describe a method for error correction encoding of data to be stored in a memory device, a corresponding method for decoding a codeword matrix resulting from the encoding method, a coding device, and a computer program for performing the methods on the coding device, using a new construction for high-rate generalized concatenated (GC) codes. The codes, which are well suited for error correction in flash memories for high reliability data storage, are constructed from inner nested binary Bose-Chaudhuri-Hocquenghem (BCH) codes and outer codes, preferably Reed-Solomon (RS) codes. For the inner codes extended BCH codes are used, where only single parity-check codes are applied in the first level of the GC code. This enables high-rate codes.

6. 发明申请

US20190035474A1 Method and Apparatus for Enhancing the Reliability of a Non-Volatile Memory 审中-公开
公开(公告)号：US20190035474A1
公开(公告)日：2019-01-31
申请号：US15701205
申请日：2017-09-11
申请人： HYPERSTONE GMBH
发明人： Fabio Tassan , Jan Peter Berns , Christoph Baumhof
IPC分类号： G11C16/10 , G11C29/12
摘要： Various embodiments are related to non-volatile memories, systems, and methods of using such.

7. 发明申请

US20180175890A1 Methods and Apparatus for Error Correction Coding Based on Data Compression 审中-公开
公开(公告)号：US20180175890A1
公开(公告)日：2018-06-21
申请号：US15848012
申请日：2017-12-20
申请人： HYPERSTONE GMBH
发明人： Juergen Freudenberger , Mohammed I. M. Rajab , Christoph Baumhof
IPC分类号： H03M13/00 , H04L1/00 , H03M13/37
CPC分类号： H03M13/6312 , G06F11/00 , H03M7/30 , H03M7/3068 , H03M7/40 , H03M13/05 , H03M13/3753 , H04L1/0041 , H04L1/0045
摘要： Embodiments are generally related to the field of channel and source coding of data to be sent over a channel, such as a communication link or a data memory. Some specific embodiments are related to a method of encoding data for transmission over a channel, a corresponding decoding method, a coding device for performing one or both of these methods and a computer program comprising instructions to cause said coding device to perform one or both of said methods.

8. 发明申请

US20190173495A1 Method and Decoder for Soft Input Decoding of Generalized Concatenated Codes 审中-公开
公开(公告)号：US20190173495A1
公开(公告)日：2019-06-06
申请号：US16252604
申请日：2019-01-19
申请人： HYPERSTONE GMBH
发明人： Juergen Freudenberger , Jens Spinner , Christoph Baumhof
IPC分类号： H03M13/29 , H03M13/00 , H03M13/45 , H03M13/11 , H03M13/39 , H03M13/35 , H03M13/15 , H03M13/25
摘要： The invention relates to a soft input decoding method and a decoder for generalized concatenated (GC) codes. The GC codes are constructed from inner nested block codes, such as binary Bose-Chaudhuri-Hocquenghem, BCH, codes and outer codes, such as Reed-Solomon, RS, codes. In order to enable soft input decoding for the inner block codes, a sequential stack decoding algorithm is used. Ordinary stack decoding of binary block codes requires the complete trellis of the code. In one aspect, the present invention applies instead a representation of the block codes based on the trellises of supercodes in order to reduce the memory requirements for the representation of the inner codes. This enables an efficient hardware implementation. In another aspect, the present invention provides a soft input decoding method and device employing a sequential stack decoding algorithm in combination with list-of-two decoding which is particularly well suited for applications that require very low residual error rates.

9. 发明授权

US10276246B2 Method and apparatus for enhancing the reliability of a non-volatile memory 有权
公开(公告)号：US10276246B2
公开(公告)日：2019-04-30
申请号：US15701205
申请日：2017-09-11
申请人： HYPERSTONE GMBH
发明人： Fabio Tassan , Jan Peter Berns , Christoph Baumhof
IPC分类号： G11C16/10 , G11C29/12
摘要： Various embodiments are related to non-volatile memories, systems, and methods of using such. Some instances provide a computer readable medium that includes instructions executable by one or more processors of an NVM controller for controlling a NVM using memory pages where the NVM controller having a predefined error correction coding, ECC, capability (ECCCTRL). Executing the instructions may cause the NVM controller to: perform a monitoring process and perform a transitioning process.

10. 发明申请

US20170331499A1 METHOD AND DECODER FOR SOFT INPUT DECODING OF GENERALIZED CONCATENATED CODES 审中-公开
公开(公告)号：US20170331499A1
公开(公告)日：2017-11-16
申请号：US15594830
申请日：2017-05-15
申请人： HYPERSTONE GMBH
发明人： JUERGEN FREUDENBERGER , JENS SPINNER , CHRISTOPH BAUMHOF
IPC分类号： H03M13/29 , H03M13/25 , H03M13/15 , H03M13/11 , G11B20/18
CPC分类号： H03M13/293 , G11B2020/1836 , G11B2020/1859 , H03M13/1191 , H03M13/1515 , H03M13/152 , H03M13/253 , H03M13/29 , H03M13/2906 , H03M13/2909 , H03M13/2927 , H03M13/2948 , H03M13/2993 , H03M13/356 , H03M13/3944 , H03M13/458 , H03M13/618
摘要： A soft input decoding method and a decoder for generalized concatenated (GC) codes. The GC codes are constructed from inner nested block codes, such as binary Bose-Chaudhuri-Hocquenghem, BCH, codes and outer codes, such as Reed-Solomon, RS, codes. In order to enable soft input decoding for the inner block codes, a sequential stack decoding algorithm is used. Ordinary stack decoding of binary block codes requires the complete trellis of the code. In one aspect, the present invention applies instead a representation of the block codes based on the trellises of supercodes in order to reduce the memory requirements for the representation of the inner codes. This enables an efficient hardware implementation. In another aspect, there is provided a soft input decoding method and device employing a sequential stack decoding algorithm in combination with list-of-two decoding which is particularly well suited for applications that require very low residual error rates.

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