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1. 发明授权

US08823360B2 Semiconductor device 有权
标题翻译：半导体器件
公开(公告)号：US08823360B2
公开(公告)日：2014-09-02
申请号：US13213778
申请日：2011-08-19
申请人： Hajime Akiyama , Akira Okada
发明人： Hajime Akiyama , Akira Okada
IPC分类号： G01R15/18
CPC分类号： G01R31/2884 , B82Y25/00 , G01R15/205 , G01R33/091 , G01R33/093 , G01R33/096 , G01R33/098 , H01F10/325 , H01F10/3254 , H01L2224/4846 , H01L2224/49111
摘要： A semiconductor device comprises: a semiconductor element including an electrode; a leading line electrically connected to the electrode, passing above the electrode, and led to a side thereof; and a current sensor sensing current flowing through the leading line. The current sensor includes a magneto-resistance element placed above the electrode and below the leading line. A resistance value of the magneto-resistance element varies linearly according to magnetic field generated by the current.
摘要翻译：半导体器件包括：包括电极的半导体元件; 电连接到电极的引线，通过电极上方并被引导到其一侧; 以及感测电流流经前导线的电流传感器。电流传感器包括放置在电极上方和导线下方的磁阻元件。磁阻元件的电阻值根据电流产生的磁场线性变化。

2. 发明申请

US20140202364A1 METHOD OF WASTE MELTING TREATMENT 审中-公开
标题翻译：废物熔融处理方法
公开(公告)号：US20140202364A1
公开(公告)日：2014-07-24
申请号：US14119108
申请日：2012-05-23
申请人： Takashi Nakayama , Takeshi Uchiyama , Hajime Akiyama , Tomohiro Yoshida , Tamio Ida
发明人： Takashi Nakayama , Takeshi Uchiyama , Hajime Akiyama , Tomohiro Yoshida , Tamio Ida
IPC分类号： F23G5/027 , F23G5/44 , F23G5/08
CPC分类号： F23G5/027 , F23G5/0276 , F23G5/08 , F23G5/165 , F23G5/24 , F23G5/444 , F23G2202/20
摘要： A waste-melting method, in which waste is fed into a waste-melting furnace (1), and the waste is thermally decomposed and combusted, and then, thermal decomposition and combustion residues are melted, is characterized in that coal coke and a biomass-molded material obtained by press-molding a biomass starting material while heating the biomass starting material to a temperature lower than the carbonization temperature thereof are fed into the melting furnace, a high-temperature grate is formed with coal coke at the bottom of the melting furnace, and the coal coke and the biomass-molded material are combusted and used as heat sources for melting.
摘要翻译：将废物进料到废熔炉（1）中并将废物热分解燃烧，然后将热分解和燃烧残渣熔化的废熔融方法，其特征在于焦炭和生物质在将生物质原料加热至低于其碳化温度的温度下通过将生物质原料压制成型而获得的模塑材料进料到熔化炉中，在熔化炉底部形成高温炉煤焦炭炉，煤焦炭和生物质成型材料燃烧并用作熔化热源。

3. 发明授权

US08609443B2 Semiconductor device manufacturing method 有权
标题翻译：半导体器件制造方法
公开(公告)号：US08609443B2
公开(公告)日：2013-12-17
申请号：US13666473
申请日：2012-11-01
申请人： Kazuhiro Shimizu , Hajime Akiyama , Naoki Yasuda
发明人： Kazuhiro Shimizu , Hajime Akiyama , Naoki Yasuda
IPC分类号： H01L21/66
CPC分类号： H01L21/67271 , H01L21/67282 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor device manufacturing apparatus is provided with a drawing pattern printing part having a print head which injects a conductive solvent, an insulative solvent and an interface treatment solution. The print head is formed in such a way that desired circuit drawing pattern can be printed on a wafer based on information on the drawing pattern from a wafer testing part, information on the wafer from a storage part and coordinate information from a chip coordinate recognition part. In a semiconductor device manufacturing method according to the present invention, a semiconductor device is manufactured by using the semiconductor device manufacturing apparatus in such a manner that desired circuits are formed through printing process. In the semiconductor device, pad electrodes and so on are formed in such a way that trimming process can be conducted by printing circuit drawing patterns.
摘要翻译：半导体器件制造装置具备：具有喷射导电性溶剂的印刷头，绝缘性溶剂和界面处理液的图形印刷部。打印头形成为使得可以基于来自晶片测试部分的绘图图案的信息，从存储部分获得关于晶片的信息和来自芯片坐标识别部分的坐标信息，将期望的电路图形图案印刷在晶片上。在根据本发明的半导体器件制造方法中，通过使用半导体器件制造设备以通过印刷处理形成期望的电路的方式制造半导体器件。在半导体器件中，焊盘电极等以能够通过打印电路图形进行修整处理的方式形成。

4. 发明申请

US20130152965A1 SEMICONDUCTOR CLEANING DEVICE AND SEMICONDUCTOR CLEANING METHOD 有权
标题翻译：半导体清洁器件和半导体清洁方法
公开(公告)号：US20130152965A1
公开(公告)日：2013-06-20
申请号：US13595299
申请日：2012-08-27
申请人： Akira OKADA , Takaya Noguchi , Hajime Akiyama
发明人： Akira OKADA , Takaya Noguchi , Hajime Akiyama
IPC分类号： B08B6/00
CPC分类号： H01L21/02076 , B08B5/04 , B08B6/00 , H01L21/02041 , H01L21/02046 , H01L21/67 , H01L21/67028 , H01L21/673 , H01L21/67333
摘要： A semiconductor cleaning device includes an external electrode opposed to a side surface of the semiconductor device; a base configured to allow arrangement of the semiconductor device, and having an opening positioned between the side surface of the semiconductor device in the arranged state and the external electrode, and located below the side surface of the semiconductor device; a frame having an electrically insulating property, being in contact with the external electrode, arranged on the base and opposed to the side surface of the semiconductor device; and suction means connected to the opening in the base and being capable of taking in the foreign matter through the opening. Thereby, the semiconductor cleaning device and a semiconductor cleaning method that can remove the foreign matter adhered to the side surface of the semiconductor device and can prevent re-adhesion of the removed foreign matter can be obtained.
摘要翻译：半导体清洁装置包括与半导体器件的侧表面相对的外部电极; 基座，被配置为允许半导体器件的布置，并且具有位于布置状态的半导体器件的侧表面之间的开口和外部电极，并且位于半导体器件的侧表面之下; 具有与外部电极接触的具有电绝缘性能的框架，布置在基座上并与半导体器件的侧表面相对; 以及连接到基座中的开口并且能够通过开口吸收异物的抽吸装置。由此，可以获得能够除去附着在半导体装置的侧面的异物并能够防止除去的异物的再附着的半导体清洗装置和半导体清洗方法。

5. 发明授权

US08324657B2 Semiconductor device 有权
标题翻译：半导体器件
公开(公告)号：US08324657B2
公开(公告)日：2012-12-04
申请号：US13160204
申请日：2011-06-14
申请人： Kazuhiro Shimizu , Hajime Akiyama , Naoki Yasuda
发明人： Kazuhiro Shimizu , Hajime Akiyama , Naoki Yasuda
IPC分类号： H01L29/74 , H01L31/111
CPC分类号： H01L21/67271 , H01L21/67282 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor device manufacturing apparatus is provided with a drawing pattern printing part having a print head which injects a conductive solvent, an insulative solvent and an interface treatment solution. The print head is formed in such a way that desired circuit drawing pattern can be printed on a wafer based on information on the drawing pattern from a wafer testing part, information on the wafer from a storage part and coordinate information from a chip coordinate recognition part. In a semiconductor device manufacturing method according to the present invention, a semiconductor device is manufactured by using the semiconductor device manufacturing apparatus in such a manner that desired circuits are formed through printing process. In the semiconductor device, pad electrodes and so on are formed in such a way that trimming process can be conducted by printing circuit drawing patterns.
摘要翻译：半导体器件制造装置具备：具有喷射导电性溶剂的印刷头，绝缘性溶剂和界面处理液的图形印刷部。打印头形成为使得可以基于来自晶片测试部件的绘图图案的信息，从存储部分获得关于晶片的信息和来自芯片坐标识别部分的坐标信息，将期望的电路图形图案印刷在晶片上。在根据本发明的半导体器件制造方法中，通过使用半导体器件制造设备以通过印刷处理形成期望的电路的方式制造半导体器件。在半导体器件中，焊盘电极等以能够通过打印电路图形进行修整处理的方式形成。

6. 发明授权

US07851873B2 Semiconductor device and method of manufacturing the same 有权
标题翻译：半导体装置及其制造方法
公开(公告)号：US07851873B2
公开(公告)日：2010-12-14
申请号：US12123720
申请日：2008-05-20
申请人： Hajime Akiyama
发明人： Hajime Akiyama
IPC分类号： H01L29/76 , H01L29/94 , H01L31/062 , H01L31/113 , H01L31/119
CPC分类号： H01L29/407 , H01L29/0692 , H01L29/0878 , H01L29/1045 , H01L29/1083 , H01L29/404 , H01L29/7824 , H01L29/7835 , H01L29/78624
摘要： The HVIC includes a dielectric layer and an SOI active layer stacked on a silicon substrate, a transistor formed in the surface of the SOI active layer, and a trench isolation region formed around the transistor. The dielectric layer includes a first buried oxide film formed in the surface of the silicon substrate, a shield layer formed below the first buried oxide film opposite the element area, a second buried oxide film formed around the shield layer, and a third buried oxide film formed below the shield layer and the second buried oxide film. Therefore, the potential distribution curves PC within the dielectric layer are low in density and a high withstand voltage is achieved.
摘要翻译： HVIC包括层叠在硅衬底上的电介质层和SOI有源层，形成在SOI有源层的表面中的晶体管和形成在晶体管周围的沟槽隔离区。电介质层包括形成在硅衬底的表面上的第一掩埋氧化物膜，形成在与元件区域相对的第一掩埋氧化物膜下方的屏蔽层，形成在屏蔽层周围的第二掩埋氧化物膜，以及第三掩埋氧化物膜形成在屏蔽层和第二埋氧化膜的下方。因此，电介质层内的电位分布曲线PC的密度低，实现了高耐压。

7. 发明授权

US07485943B2 Dielectric isolation type semiconductor device and manufacturing method therefor 有权
标题翻译：绝缘隔离型半导体器件及其制造方法
公开(公告)号：US07485943B2
公开(公告)日：2009-02-03
申请号：US11408087
申请日：2006-04-21
申请人： Hajime Akiyama
发明人： Hajime Akiyama
IPC分类号： H01L29/00 , H01L27/01
CPC分类号： H01L29/7824 , H01L24/05 , H01L29/0653 , H01L29/0886 , H01L29/405 , H01L29/407 , H01L29/78603 , H01L2224/04042 , H01L2224/05556 , H01L2224/48463 , H01L2924/12036 , H01L2924/13091 , H01L2924/14 , H01L2924/00
摘要： A dielectric isolation type semiconductor device includes a dielectric isolation type substrate in which a support substrate, an embedded dielectric layer, and a first conductive type semiconductor substrate of a low impurity concentration are laminated one over another. The semiconductor substrate includes a first semiconductor region of a first conductive type having a high impurity concentration, a second semiconductor region of a second conductive type having a high impurity concentration arranged so as to surround the first semiconductor region, a first main electrode joined to a surface of the first semiconductor region, and a second main electrode joined to a surface of the second semiconductor region. A first dielectric portion is arranged adjacent the embedded dielectric layer so as to surround a region of the support substrate superposed on the first semiconductor region in a direction of lamination thereof, and a wire connected with the first main electrode.
摘要翻译：绝缘隔离型半导体器件包括绝缘隔离型衬底，其中支撑衬底，嵌入电介质层和低杂质浓度的第一导电类型半导体衬底彼此层叠。半导体衬底包括具有高杂质浓度的第一导电类型的第一半导体区域，具有以包围第一半导体区域排列的杂质浓度高的第二导电类型的第二半导体区域，与第一半导体区域第一半导体区域的表面和与第二半导体区域的表面接合的第二主电极。第一电介质部分布置成与嵌入的电介质层相邻，以便围绕叠置在第一半导体区域上的支撑衬底的层叠方向的区域和与第一主电极连接的电线。

8. 发明申请

US20070072394A1 Semiconductor device manufacturing apparatus, semiconductor device manufacturing method and semiconductor device 有权
标题翻译：半导体装置制造装置，半导体装置的制造方法以及半导体装置
公开(公告)号：US20070072394A1
公开(公告)日：2007-03-29
申请号：US11412990
申请日：2006-04-28
申请人： Kazuhiro Shimizu , Hajime Akiyama , Naoki Yasuda
发明人： Kazuhiro Shimizu , Hajime Akiyama , Naoki Yasuda
IPC分类号： H01L21/00
CPC分类号： H01L21/67271 , H01L21/67282 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor device manufacturing apparatus is provided with a drawing pattern printing part having a print head which injects a conductive solvent, an insulative solvent and an interface treatment solution. The print head is formed in such a way that desired circuit drawing pattern can be printed on a wafer based on information on the drawing pattern from a wafer testing part, information on the wafer from a storage part and coordinate information from a chip coordinate recognition part. In a semiconductor device manufacturing method according to the present invention, a semiconductor device is manufactured by using the semiconductor device manufacturing apparatus in such a manner that desired circuits are formed through printing process. In the semiconductor device, pad electrodes and so on are formed in such a way that trimming process can be conducted by printing circuit drawing patterns.
摘要翻译：半导体器件制造装置具备：具有喷射导电性溶剂的印刷头，绝缘性溶剂和界面处理液的图形印刷部。打印头形成为使得可以基于来自晶片测试部件的绘图图案的信息，从存储部分获得关于晶片的信息和来自芯片坐标识别部分的坐标信息，将期望的电路图形图案印刷在晶片上。在根据本发明的半导体器件制造方法中，通过使用半导体器件制造设备以通过印刷处理形成期望的电路的方式制造半导体器件。在半导体器件中，焊盘电极等以能够通过打印电路图形进行修整处理的方式形成。

9. 发明申请

US20060138586A1 Dielectric isolation type semiconductor device and method for manufacturing the same 有权
公开(公告)号：US20060138586A1
公开(公告)日：2006-06-29
申请号：US11354961
申请日：2006-02-16
申请人： Hajime Akiyama , Shinichi Izuo
发明人： Hajime Akiyama , Shinichi Izuo
IPC分类号： H01L29/00
CPC分类号： H01L21/76264 , H01L29/0696 , H01L29/402 , H01L29/66681 , H01L29/7394 , H01L29/7455 , H01L29/7824 , H01L29/78603 , H01L2924/0002 , H01L2924/00
摘要： A dielectric isolation type semiconductor device and a manufacturing method therefor achieve high dielectric resistance while preventing the dielectric strength of the semiconductor device from being limited depending on the thickness of a dielectric layer and the thickness of a first semiconductor layer. A semiconductor substrate (1) and an n− type semiconductor layer (2) are bonded to each other through a buried oxide film layer (3). A first porous oxide film area (10) is formed in the semiconductor substrate in a state contacting with the buried oxide film layer. A power device is formed on the n− type semiconductor layer. The first porous oxide film area is formed in an area including a location right under a first main electrode (6) and extending from the first main electrode side up to a range of more than 40% of a distance (L) between the first and second main electrodes (6, 7).

10. 发明授权

US5182626A Insulated gate bipolar transistor and method of manufacturing the same 失效
标题翻译：绝缘栅双极晶体管及其制造方法
公开(公告)号：US5182626A
公开(公告)日：1993-01-26
申请号：US543532
申请日：1990-06-26
申请人： Hajime Akiyama , Hisao Kondoh
发明人： Hajime Akiyama , Hisao Kondoh
IPC分类号： H01L21/331 , H01L29/08 , H01L29/739
CPC分类号： H01L21/263 , H01L29/0834 , H01L29/66333 , H01L29/7395
摘要： In the present invention, baneful influences such as the reduction of the threshold voltage due to the irradiation of an ionizing radiation such as an electron beam and a light ion beam are removed to practice the lifetime control of an IGBT with good controllability. Basically, the lifetime control without change in the threshold voltage is implemented by increasing the threshold voltage on or before irradiating the ionizing radiation so as to cancel the influence of each other. Further, the lifetime control without change in the threshold voltage is implemented with higher accuracy by irradiating a light ion beam from a rear main electrode side so as to cause crystal defects locally in a specific region in an epitaxial layer.
摘要翻译：在本发明中，除去诸如电子束和光离子束等电离辐射的照射引起的阈值电压的降低等的恶化影响，从而实现具有良好可控性的IGBT的寿命控制。基本上，通过在照射电离辐射之前或之前增加阈值电压来实现阈值电压的变化，从而消除彼此的影响。此外，通过从后部主电极侧照射光离子束，以更高的精度实现阈值电压的变化的寿命控制，从而在外延层的特定区域局部引起晶体缺陷。

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