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1. 发明授权

US09389841B2 Methods and systems for using state vector data in a state machine engine 有权
标题翻译：在状态机引擎中使用状态向量数据的方法和系统
公开(公告)号：US09389841B2
公开(公告)日：2016-07-12
申请号：US13552488
申请日：2012-07-18
申请人： David R. Brown , Harold B Noyes
发明人： David R. Brown , Harold B Noyes
IPC分类号： G06F12/00 , G06F9/45 , G06N3/02
CPC分类号： G06F3/0613 , G06F3/0647 , G06F3/0656 , G06F3/0664 , G06F3/0673 , G06F8/42 , G06N3/02
摘要： A state machine engine includes a state vector system. The state vector system includes an input buffer configured to receive state vector data from a restore buffer and to provide state vector data to a state machine lattice. The state vector system also includes an output buffer configured to receive state vector data from the state machine lattice and to provide state vector data to a save buffer.
摘要翻译：状态机引擎包括状态向量系统。状态向量系统包括：输入缓冲器，被配置为从恢复缓冲器接收状态向量数据，并向状态机格状态提供状态向量数据。状态向量系统还包括：输出缓冲器，被配置为从状态机格点接收状态向量数据，并向保存缓冲器提供状态向量数据。

2. 发明授权

US09323994B2 Multi-level hierarchical routing matrices for pattern-recognition processors 有权
标题翻译：用于模式识别处理器的多级分层路由矩阵
公开(公告)号：US09323994B2
公开(公告)日：2016-04-26
申请号：US12638759
申请日：2009-12-15
申请人： Harold B Noyes , David R. Brown
发明人： Harold B Noyes , David R. Brown
IPC分类号： G06F9/02 , G06F13/00 , G06F19/24 , G06K9/00 , G06F17/30
CPC分类号： G06F15/80 , G06F17/30985 , G06K9/00986 , G06N5/003
摘要： Multi-level hierarchical routing matrices for pattern-recognition processors are provided. One such routing matrix may include one or more programmable and/or non-programmable connections in and between levels of the matrix. The connections may couple routing lines to feature cells, groups, rows, blocks, or any other arrangement of components of the pattern-recognition processor.
摘要翻译：提供了用于模式识别处理器的多级分层路由矩阵。一个这样的路由矩阵可以包括在矩阵的层内和之间的一个或多个可编程和/或不可编程的连接。这些连接可以将路由线路耦合到特征单元，组，行，块或模式识别处理器的任何其他组件的布置。

3. 发明授权

US09164945B2 Devices, systems, and methods to synchronize parallel processing of a single data stream 有权
标题翻译：用于同步单个数据流的并行处理的设备，系统和方法
公开(公告)号：US09164945B2
公开(公告)日：2015-10-20
申请号：US12325990
申请日：2008-12-01
申请人： Harold B Noyes
发明人： Harold B Noyes
IPC分类号： G06F9/30 , G06F13/42 , G06K9/00
CPC分类号： G06F13/4213 , G06K9/00979
摘要： Disclosed are methods and devices, among which is a system that includes one or more pattern-recognition processors, such as in a pattern-recognition cluster. The pattern-recognition processors may be activated to perform a search of a data stream individually using a chip select or in parallel using a universal select signal. In this manner, the plurality of pattern-recognition processors may be enabled concurrently for synchronized processing of the data stream.
摘要翻译：公开了方法和装置，其中包括一个或多个模式识别处理器的系统，诸如在模式识别簇中。可以激活模式识别处理器以使用片选或使用通用选择信号并行地执行数据流的搜索。以这种方式，可以同时启用多个模式识别处理器以用于数据流的同步处理。

4. 发明授权

US08713223B2 Methods and systems to accomplish variable width data input 有权
标题翻译：完成可变宽度数据输入的方法和系统
公开(公告)号：US08713223B2
公开(公告)日：2014-04-29
申请号：US13599173
申请日：2012-08-30
申请人： Harold B Noyes
发明人： Harold B Noyes
IPC分类号： G06F13/12 , H03M13/00 , G06F13/38
CPC分类号： G06F13/385 , G06F13/4018
摘要： Disclosed are methods and systems for variable width data input to a pattern-recognition processor. A variable width data input method may include receiving bytes over a data bus having a first width and receiving one or more signals indicating the validity of each of the one or more bytes. The valid bytes may be sequentially provided to a pattern-recognition processor in an 8-bit wide data stream. In an embodiment, a system may include one or more address lines configured to provide the one or more signals indicating the validity of the bytes transferred over the data bus. The system may include a buffer and control logic to sequentially process the valid bytes.
摘要翻译：公开了用于将可变宽度数据输入到模式识别处理器的方法和系统。可变宽度数据输入方法可以包括通过具有第一宽度的数据总线接收字节，并且接收指示一个或多个字节中的每一个的有效性的一个或多个信号。有效字节可以顺序地提供给8位宽数据流中的模式识别处理器。在一个实施例中，系统可以包括一个或多个地址线，其被配置为提供指示通过数据总线传送的字节的有效性的一个或多个信号。系统可以包括缓冲器和控制逻辑以顺序地处理有效字节。

5. 发明授权

US08489534B2 Adaptive content inspection 有权
标题翻译：自适应内容检查
公开(公告)号：US08489534B2
公开(公告)日：2013-07-16
申请号：US12638767
申请日：2009-12-15
申请人： Paul D. Dlugosch , Harold B Noyes
发明人： Paul D. Dlugosch , Harold B Noyes
IPC分类号： G06F17/18
CPC分类号： G06N5/022 , H04L63/0245
摘要： Methods and apparatus are provided involving adaptive content inspection. In one embodiment, a content inspection processor may identify information with respect to input data and provide the information to a host controller. The host controller may adapt search criteria or other parameters and provide the adapted parameter to the content inspection processor. Other embodiments may include a content inspection processor having integrated feedback, such that results data is fed back to the content inspection processor. The results data may be processed before being provided to the content inspection processor.
摘要翻译：提供了涉及自适应内容检查的方法和装置。在一个实施例中，内容检查处理器可以识别关于输入数据的信息，并将信息提供给主机控制器。主机控制器可以调整搜索标准或其他参数，并将适配参数提供给内容检查处理器。其他实施例可以包括具有集成反馈的内容检查处理器，使得结果数据被反馈到内容检查处理器。可以在提供给内容检查处理器之前处理结果数据。

6. 发明申请

US20130154685A1 BOOLEAN LOGIC IN A STATE MACHINE LATTICE 有权
公开(公告)号：US20130154685A1
公开(公告)日：2013-06-20
申请号：US13327510
申请日：2011-12-15
申请人： Harold B Noyes , David R. Brown , Paul Glendenning , Irene J. Xu
发明人： Harold B Noyes , David R. Brown , Paul Glendenning , Irene J. Xu
IPC分类号： H03K19/173
CPC分类号： H03K19/17708 , G05B19/045 , G06F7/00 , G06F9/4498 , G06F17/5054 , H03K19/0175 , H03K19/17704 , H03K19/20 , H03K19/21 , Y02T10/82
摘要： Disclosed are methods and devices, among which is a device that includes a finite state machine lattice. The lattice may includes a programmable Boolean logic cell that may be programmed to perform various logic functions on a data stream. The programmability includes an inversion of a first input to the Boolean logic cell, an inversion of a last output of the Boolean logic cell, and a selection of an AND gate or an OR gate as a final output of the Boolean logic cell. The Boolean logic cell also includes end of data circuitry configured to cause the Boolean logic cell to only output after an end of data signifying the end of a data stream is received at the Boolean logic cell.

7. 发明申请

US20110145544A1 MULTI-LEVEL HIERARCHICAL ROUTING MATRICES FOR PATTERN-RECOGNITION PROCESSORS 有权
标题翻译：模式识别处理器的多层次分层路由矩阵
公开(公告)号：US20110145544A1
公开(公告)日：2011-06-16
申请号：US12638759
申请日：2009-12-15
申请人： Harold B Noyes , David R. Brown
发明人： Harold B Noyes , David R. Brown
IPC分类号： G06F15/80 , G06F9/06
CPC分类号： G06F15/80 , G06F17/30985 , G06K9/00986 , G06N5/003
摘要： Multi-level hierarchical routing matrices for pattern-recognition processors are provided. One such routing matrix may include one or more programmable and/or non-programmable connections in and between levels of the matrix. The connections may couple routing lines to feature cells, groups, rows, blocks, or any other arrangement of components of the pattern-recognition processor.
摘要翻译：提供了用于模式识别处理器的多级分层路由矩阵。一个这样的路由矩阵可以包括在矩阵的层内和之间的一个或多个可编程和/或不可编程的连接。这些连接可以将路由线路耦合到特征单元，组，行，块或模式识别处理器的任何其他组件的布置。

8. 发明申请

US20100138575A1 DEVICES, SYSTEMS, AND METHODS TO SYNCHRONIZE SIMULTANEOUS DMA PARALLEL PROCESSING OF A SINGLE DATA STREAM BY MULTIPLE DEVICES 审中-公开
标题翻译：通过多个设备同步同步DMA并行处理单个数据流的设备，系统和方法
公开(公告)号：US20100138575A1
公开(公告)日：2010-06-03
申请号：US12325986
申请日：2008-12-01
申请人： Harold B Noyes
发明人： Harold B Noyes
IPC分类号： G06F13/40
CPC分类号： G06F16/24568 , G06F13/28 , G06F13/4282
摘要： Disclosed are methods and devices, among which is a system that includes a device that includes one or more pattern-recognition processors in a pattern-recognition cluster, for example. One of the one or more pattern-recognition processors may be initialized to perform as a direct memory access master device able to control the remaining pattern-recognition processors for synchronized processing of a data stream.
摘要翻译：公开了方法和装置，其中包括例如在模式识别集群中包括一个或多个模式识别处理器的装置的系统。可以将一个或多个模式识别处理器中的一个初始化为能够控制剩余模式识别处理器以用于数据流的同步处理的直接存储器访问主设备。

9. 发明申请

US20100115158A1 Methods and Systems to Accomplish Variable Width Data Input 有权
标题翻译：完成可变宽度数据输入的方法和系统
公开(公告)号：US20100115158A1
公开(公告)日：2010-05-06
申请号：US12265421
申请日：2008-11-05
申请人： Harold B Noyes
发明人： Harold B Noyes
IPC分类号： G06F13/14
CPC分类号： G06F13/385 , G06F13/4018
摘要： Disclosed are methods and systems for variable width data input to a pattern-recognition processor. A variable width data input method may include receiving bytes over a data bus having a first width and receiving one or more signals indicating the validity of each of the one or more bytes The valid bytes may be sequentially provided to a pattern-recognition processor in an 8-bit wide data stream. In an embodiment, a system may include one or more address lines configured to provide the one or more signals indicating the validity of the bytes transferred over the data bus. The system may include a buffer and control logic to sequentially process the valid bytes.
摘要翻译：公开了用于将可变宽度数据输入到模式识别处理器的方法和系统。可变宽度数据输入方法可以包括通过具有第一宽度的数据总线接收字节，并且接收指示一个或多个字节中的每一个的有效性的一个或多个信号。有效字节可以顺序地提供给8位宽数据流中的模式识别处理器。在一个实施例中，系统可以包括一个或多个地址线，其被配置为提供指示通过数据总线传送的字节的有效性的一个或多个信号。系统可以包括缓冲器和控制逻辑以顺序地处理有效字节。

10. 发明申请

US20100100691A1 Indirect Register Access Method and System 有权
标题翻译：间接寄存器访问方法和系统
公开(公告)号：US20100100691A1
公开(公告)日：2010-04-22
申请号：US12253967
申请日：2008-10-18
申请人： Harold B Noyes , Mark Jurenka , Gavin Huggins
发明人： Harold B Noyes , Mark Jurenka , Gavin Huggins
IPC分类号： G06F12/00
CPC分类号： G11C7/1036 , G06F9/3012 , G06F9/30138 , G06F9/34 , G06F12/0615 , G06F2212/656
摘要： Systems and methods are provided for managing access to registers. In one embodiment, a system may include a processor and a plurality of registers. The processor and the plurality of registers may be integrated into a single device, or may be in separate devices. The plurality of registers may include a first set of registers that are directly accessible by the processor, and a second set of registers that are not directly accessible by the processor. The second set of registers may, however, be accessed indirectly by the processor via the first set of registers. In one embodiment, the first set of registers may include a register for selecting a register bank from the second set of registers, and a register for selecting a particular address within the register bank, to allow indirect access by the processor to the registers of the second set.
摘要翻译：提供了系统和方法来管理对寄存器的访问。在一个实施例中，系统可以包括处理器和多个寄存器。处理器和多个寄存器可以集成到单个设备中，或者可以在单独的设备中。多个寄存器可以包括可由处理器直接访问的第一组寄存器和不能由处理器直接访问的第二组寄存器。然而，第二组寄存器可以由处理器经由第一组寄存器间接访问。在一个实施例中，第一组寄存器可以包括用于从第二组寄存器中选择寄存器组的寄存器和用于选择寄存器组内的特定地址的寄存器，以允许处理器间接访问寄存器组的寄存器第二集

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