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1. 发明申请

US20190238137A1 FOUR-INPUT JOSEPHSON GATES 审中-公开
公开(公告)号：US20190238137A1
公开(公告)日：2019-08-01
申请号：US16102385
申请日：2018-08-13
申请人： JACK R. POWELL, III , ALEXANDER L. BRAUN
发明人： JACK R. POWELL, III , ALEXANDER L. BRAUN
IPC分类号： H03K19/195 , G06N10/00 , B82Y10/00 , H03M7/00 , H03K19/177 , G11C11/44 , H01L39/02
CPC分类号： H03K19/195 , B82Y10/00 , G06N10/00 , G11C11/44 , H01L39/025 , H03K19/17708 , H03K19/1952 , H03K19/1954 , H03M7/003
摘要： Superconducting methods of determining AND, OR, AND-OR, and OR-AND logic values use single flux quantum (SFQ) pulses to assert logical inputs of a reciprocal quantum logic (RQL) gate by placing currents in input storage loops in the RQL gate and, based on the currents in the storage loops, triggering logical decision Josephson junctions (JJs) in the gate, such that an assertion or de-assertion signal corresponding to the logical function of the gate is observed at the output. The methods permit for outputs based on at least four logical inputs to be achieved.

2. 发明申请

US20180234092A1 FEEDBACK CONTROLLER FOR RESONANT GATE DRIVE 审中-公开
公开(公告)号：US20180234092A1
公开(公告)日：2018-08-16
申请号：US15433209
申请日：2017-02-15
申请人： ABB Schweiz AG
发明人： Jukka-Pekka Sjoroos , Kari Tikkanen
IPC分类号： H03K17/567 , H03K17/691 , H03K19/177
CPC分类号： H03K19/17708 , H03K17/08128 , H03K17/691
摘要： Unique systems, methods, techniques and apparatuses of a gate driver are disclosed herein. One exemplary embodiment is a gate driver comprising a first and second DC rail, a first converter arm including a first and second semiconductor device, a second converter arm including a third and fourth semiconductor device, an inductor, and a controller. The controller is configured to open and close the primary switching device by operating the semiconductor devices so as to transmit power between the gate driver and a gate of a primary switching device. The controller is configured to transmit a gate signal to the primary switching device by closing the second semiconductor device, then opening the second semiconductor device and closing the fourth semiconductor device in response to the gate of the primary switching device receiving power with a voltage greater than or equal in magnitude to the voltage of the second DC rail.

3. 发明申请

US20170024615A1 SYSTEM AND METHOD FOR EDITING VIDEO AND AUDIO CLIPS 审中-公开
标题翻译：用于编辑视频和音频命令的系统和方法
公开(公告)号：US20170024615A1
公开(公告)日：2017-01-26
申请号：US15215723
申请日：2016-07-21
申请人： Shred Video, Inc.
发明人： Michael Allen , Mark Godfrey
IPC分类号： G06K9/00 , G10L25/57 , G10L15/08 , G10L15/04 , G11B27/034 , G11B27/19
CPC分类号： G06K9/00765 , G06F17/30743 , G06K9/00711 , G06K9/00718 , G06K9/00744 , G06K9/6215 , G11B27/034 , G11B27/19 , H03K19/17708
摘要： In accordance with an embodiment, a method is disclosed for detecting action in a video clip. An audio clip is extracted from the video clip. The audio clip is converted to an auditory spectrogram. The auditory spectrogram is used to construct a self-similarity matrix. The self-similarity matrix is then used to calculate a novelty curve. The clip is then segmented into segments according to peaks in the novelty curve. Each of segments is scored, and then classified as an action clip if the score is above or below a predetermined threshold. Related methods for folding a digitized song into a shorter version of itself and for sequencing a set of user-supplied video and photo clips to a user-supplied song are further disclosed.
摘要翻译：根据实施例，公开了一种用于检测视频剪辑中的动作的方法。从视频剪辑中提取音频剪辑。音频剪辑转换为听觉谱图。听觉谱图用于构建自相似矩阵。然后使用自相似矩阵来计算新颖性曲线。然后根据新颖性曲线中的峰将剪辑分割成段。每个段被评分，并且如果分数高于或低于预定阈值，则将其分类为动作剪辑。进一步公开了将数字化歌曲折叠成自己的较短版本并将用户提供的一组视频和照片剪辑排列到用户提供的歌曲的相关方法。

4. 发明授权

US09509312B2 Boolean logic in a state machine lattice 有权
公开(公告)号：US09509312B2
公开(公告)日：2016-11-29
申请号：US14832543
申请日：2015-08-21
申请人： Micron Technology, Inc.
发明人： Harold B Noyes , David R. Brown , Paul Glendenning , Irene Junjuan Xu
IPC分类号： H03K19/177 , H03K19/20 , G05B19/045 , G06F9/44 , G06F17/50 , H03K19/0175 , G06F7/00
CPC分类号： H03K19/17708 , G05B19/045 , G06F7/00 , G06F9/4498 , G06F17/5054 , H03K19/0175 , H03K19/17704 , H03K19/20 , H03K19/21 , Y02T10/82
摘要： Disclosed are methods and devices, among which is a device that includes a finite state machine lattice. The lattice may includes a programmable Boolean logic cell that may be programmed to perform various logic functions on a data stream. The programmability includes an inversion of a first input to the Boolean logic cell, an inversion of a last output of the Boolean logic cell, and a selection of an AND gate or an OR gate as a final output of the Boolean logic cell. The Boolean logic cell also includes end of data circuitry configured to cause the Boolean logic cell to only output after an end of data signifying the end of a data stream is received at the Boolean logic cell.

5. 发明授权

US09385798B1 Apparatus and method for efficient waveform portability between different platforms 有权
标题翻译：不同平台之间有效的波形可移植性的装置和方法
公开(公告)号：US09385798B1
公开(公告)日：2016-07-05
申请号：US14606701
申请日：2015-01-27
申请人： RAYTHEON COMPANY
发明人： Harry Marr , Ian S. Robinson , Ray T. Hsu
IPC分类号： H04L27/00 , H04B7/06 , H03K19/177
CPC分类号： H04B7/0613 , G06F1/0342 , H03K19/17708 , H04K3/42 , H04K3/44
摘要： Method and apparatus for generating channelized hardware-independent waveforms include: generating metadata associated with a waveform, the metadata including a frequency list, a phase list and amplitude information, wherein the metadata is generated independent of a number of channels; interpreting the metadata to generate channel select, frequency, phase and amplitude parameters; providing the frequency, phase and amplitude parameters to a direct digital synthesizer (DDS) to generate a digital signal; providing the channel select parameter to a channel selector to generate a plurality of channelized waveforms from the generated digital signal; and transmitting the plurality of channelized waveforms over a plurality of communication channels.
摘要翻译：用于产生信道化与硬件无关的波形的方法和装置包括：生成与波形相关联的元数据，所述元数据包括频率列表，相位列表和幅度信息，其中独立于多个信道生成所述元数据; 解释元数据以产生通道选择，频率，相位和幅度参数; 将频率，相位和幅度参数提供给直接数字合成器（DDS）以产生数字信号; 向频道选择器提供频道选择参数以从所生成的数字信号中产生多个信道化波形; 以及在多个通信信道上发送多个信道化波形。

6. 发明授权

US09374094B1 3D field programmable gate array system with reset manufacture and method of manufacture thereof 有权
标题翻译：具有复位制造的3D现场可编程门阵列系统及其制造方法
公开(公告)号：US09374094B1
公开(公告)日：2016-06-21
申请号：US14470901
申请日：2014-08-27
申请人： Altera Corporation
发明人： Ping Xiao
IPC分类号： H03K19/017 , H03K19/08 , H03K19/0175 , H01L25/16 , H03K19/177 , H03K17/22
CPC分类号： H03K19/1774 , H01L23/3128 , H01L23/49827 , H01L24/13 , H01L24/14 , H01L24/16 , H01L24/17 , H01L25/0652 , H01L25/0655 , H01L25/0657 , H01L25/16 , H01L25/18 , H01L2224/13025 , H01L2224/1403 , H01L2224/14181 , H01L2224/16145 , H01L2224/16146 , H01L2224/16155 , H01L2224/16227 , H01L2224/16235 , H01L2225/06513 , H01L2225/06517 , H01L2225/06541 , H01L2225/06548 , H01L2924/10253 , H01L2924/14 , H01L2924/1431 , H01L2924/15192 , H01L2924/15311 , H01L2924/157 , H01L2924/18161 , H03K17/223 , H03K19/0175 , H03K19/08 , H03K19/17708
摘要： A 3D field programmable gate array (FPGA) system, and method of manufacture therefor, includes: a field programmable gate array (FPGA) die having a configurable power on reset (POR) unit; a heterogeneous integrated circuit die coupled to the FPGA die; and a 3D power on reset (POR) output configured by the configurable POR unit for initializing the FPGA die and the heterogeneous integrated circuit die.
摘要翻译： 3D现场可编程门阵列（FPGA）系统及其制造方法包括：具有可配置上电复位（POR）单元的现场可编程门阵列（FPGA）管芯; 耦合到FPGA管芯的异质集成电路管芯; 以及由可配置POR单元配置的用于初始化FPGA管芯和异质集成电路管芯的3D上电复位（POR）输出。

7. 发明授权

US08710863B2 Configurable logic cells 有权
标题翻译：可配置的逻辑单元
公开(公告)号：US08710863B2
公开(公告)日：2014-04-29
申请号：US13449993
申请日：2012-04-18
申请人： Kevin Lee Kilzer , Sean Steedman , Jerrold S. Zdenek , Vivien N. Delport , Zeke Lundstrum , Fanie Duvenhage
发明人： Kevin Lee Kilzer , Sean Steedman , Jerrold S. Zdenek , Vivien N. Delport , Zeke Lundstrum , Fanie Duvenhage
IPC分类号： G06F7/38 , H03K19/173
CPC分类号： G06F15/7871 , H03K19/177 , H03K19/17708
摘要： A processor includes a RISC CPU core; and a plurality of peripherals including one or more configurable logic cell peripherals. The configurable logic cell peripheral may be configured to allow real-time software access to internal configuration and signals paths of the processor. The configurable logic cell peripheral may have real-time configuration control.
摘要翻译：处理器包括一个RISC CPU内核; 以及包括一个或多个可配置逻辑单元外围设备的多个外围设备。可配置逻辑单元外设可以被配置为允许实时软件访问处理器的内部配置和信号路径。可配置逻辑单元外设可能具有实时配置控制。

8. 发明申请

US20130135009A1 METHOD AND APPARATUS FOR IDENTIFYING CONNECTIONS BETWEEN CONFIGURABLE NODES IN A CONFIGURABLE INTEGRATED CIRCUIT 失效
标题翻译：用于识别可配置集成电路中可配置节点之间的连接的方法和装置
公开(公告)号：US20130135009A1
公开(公告)日：2013-05-30
申请号：US13621132
申请日：2012-09-15
申请人： Andre Rohe , Steven Teig
发明人： Andre Rohe , Steven Teig
IPC分类号： H03K19/177
CPC分类号： H03K19/17708 , G06F17/5054 , G06F17/5077 , G06F2217/08
摘要： Some embodiments provide a method that defines a set of connections that connect the nodes in a configurable node array. The method identifies different sets of connections for connecting a set of the nodes. For each identified set of connections, the method computes a metric score that quantifies a quality of the identified set of connections. The method then selects one of the identified sets of connections to connect the configurable nodes in the array.
摘要翻译：一些实施例提供了一种定义连接可配置节点阵列中的节点的一组连接的方法。该方法识别用于连接一组节点的不同连接集。对于每个确定的连接集合，该方法计算度量分数，其量化所识别的一组连接的质量。然后，该方法选择一组已识别的连接以连接阵列中的可配置节点。

9. 发明申请

US20120271968A1 LOGIC DEVICE FOR COMBINING VARIOUS INTERRUPT SOURCES INTO A SINGLE INTERRUPT SOURCE AND VARIOUS SIGNAL SOURCES TO CONTROL DRIVE STRENGTH 审中-公开
标题翻译：用于将各种中断源组合到单个中断源和各种信号源以控制驱动强度的逻辑设备
公开(公告)号：US20120271968A1
公开(公告)日：2012-10-25
申请号：US13450079
申请日：2012-04-18
申请人： Kevin Lee Kilzer , Sean Steedman , Jerrold S. Zdenek , Vivien N. Delport , Zeke Lundstrum , Fanie Duvenhage
发明人： Kevin Lee Kilzer , Sean Steedman , Jerrold S. Zdenek , Vivien N. Delport , Zeke Lundstrum , Fanie Duvenhage
IPC分类号： G06F13/14
CPC分类号： H03K19/17712 , H03K19/17708
摘要： A processor includes a RISC CPU core and a plurality of peripherals including a configurable logic cell peripheral. The configurable logic cell peripheral may be configured to combine a plurality of inputs into a single output. The configurable logic cell may be programmable to function as one of a plurality of predetermined logic functions.
摘要翻译：处理器包括RISC CPU内核和包括可配置逻辑单元外围设备的多个外围设备。可配置逻辑单元外设可以被配置为将多个输入组合成单个输出。可配置逻辑单元可以被编程为用作多个预定逻辑功能之一。

10. 发明授权

US07849434B2 Method and apparatus for identifying connections between configurable nodes in a configurable integrated circuit 有权
标题翻译：用于识别可配置集成电路中的可配置节点之间的连接的方法和装置
公开(公告)号：US07849434B2
公开(公告)日：2010-12-07
申请号：US11852320
申请日：2007-09-09
申请人： Andre Rohe , Steven Teig
发明人： Andre Rohe , Steven Teig
IPC分类号： G06F17/50
CPC分类号： H03K19/17708 , G06F17/5054 , G06F17/5077 , G06F2217/08
摘要： Some embodiments provide a method that defines a set of connections that connect the nodes in a configurable node array. The method identifies different sets of connections for connecting a set of the nodes. For each identified set of connections, the method computes a metric score that quantifies a quality of the identified set of connections. The method then selects one of the identified sets of connections to connect the configurable nodes in the array.
摘要翻译：一些实施例提供了一种定义连接可配置节点阵列中的节点的一组连接的方法。该方法识别用于连接一组节点的不同连接集。对于每个确定的连接集合，该方法计算度量分数，其量化所识别的一组连接的质量。然后，该方法选择一组已识别的连接以连接阵列中的可配置节点。

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