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1. 发明授权

US07095074B2 Semiconductor device with reduced memory leakage current 有权
标题翻译：具有减少内存泄漏电流的半导体器件
公开(公告)号：US07095074B2
公开(公告)日：2006-08-22
申请号：US10196166
申请日：2002-07-17
申请人： Keisuke Tsukamoto , Yoshihiro Ikeda , Tsutomu Okazaki , Daisuke Okada , Hiroshi Yanagita
发明人： Keisuke Tsukamoto , Yoshihiro Ikeda , Tsutomu Okazaki , Daisuke Okada , Hiroshi Yanagita
IPC分类号： H01L29/76 , H01L29/788
CPC分类号： H01L27/11526 , H01L27/105 , H01L27/11543
摘要： Defects in element forming regions on which memory cells of a non-volatile memory are formed are to be diminished to reduce leakage current. End portions of element forming regions with non-volatile memory cells formed thereon are extended a length D by utilizing the region which underlies a dummy conductive film, whereby a stress induced from an insulating film which surrounds the element forming regions is concentrated on the extended region. As a result, defects do not extend up to the regions where memory cells are formed and therefore it is possible to reduce leakage current in the memory cells.
摘要翻译：在其上形成非易失性存储器的存储单元的元件形成区域中的缺陷将被减小以减少泄漏电流。在其上形成有非易失性存储单元的元件形成区域的端部通过利用虚设导电膜下面的区域而延伸长度D，由此围绕元件形成区域的绝缘膜引起的应力集中在延伸区域上。结果，缺陷不延伸到形成存储单元的区域，因此可以减少存储单元中的漏电流。

2. 发明授权

US08110878B2 Semiconductor device having a plurality of shallow wells 有权
标题翻译：具有多个浅井的半导体装置
公开(公告)号：US08110878B2
公开(公告)日：2012-02-07
申请号：US13179163
申请日：2011-07-08
申请人： Naozumi Morino , Atsushi Hiraiwa , Kazutoshi Oku , Toshiaki Ito , Motoshige Igarashi , Takayuki Sasaki , Masao Sugiyama , Hiroshi Yanagita , Shinichi Watarai
发明人： Naozumi Morino , Atsushi Hiraiwa , Kazutoshi Oku , Toshiaki Ito , Motoshige Igarashi , Takayuki Sasaki , Masao Sugiyama , Hiroshi Yanagita , Shinichi Watarai
IPC分类号： H01L29/76 , H01L29/94 , H01L31/062 , H01L31/113 , H01L31/119 , H01L27/01 , H01L27/12 , H01L31/0392 , H01L23/62
CPC分类号： H01L21/823892 , H01L27/0629 , H01L27/0928 , H01L2224/05554
摘要： There is provided a technology which allows improvements in manufacturing yield and product reliability in a semiconductor device having a triple well structure. A shallow p-type well is formed in a region different from respective regions in a p-type substrate where a deep n-type well, a shallow p-type well, and a shallow n-type well are formed. A p-type diffusion tap formed in the shallow p-type well is wired to a p-type diffusion tap formed in a shallow n-type well in the deep n-type well using an interconnection in a second layer. The respective gate electrodes of an nMIS and a pMIS each formed in the deep n-type well are coupled to the respective drain electrodes of an nMIS and a pMIS each formed in the substrate using an interconnection in a second or higher order layer.
摘要翻译：提供了一种在具有三重阱结构的半导体器件中提高制造产量和产品可靠性的技术。在形成深n型阱，浅P型阱和浅n型阱的p型衬底中，在与各个区域不同的区域中形成浅的p型阱。形成在浅p型阱中的p型扩散抽头使用在第二层中的互连在深n型阱中连接到形成在浅n型阱中的p型扩散阱。每个形成在深n型阱中的nMIS和pMIS的相应栅极电极使用在第二层或更高级层中的互连而在衬底中形成的nMIS和pMIS的相应漏电极耦合。

3. 发明授权

US07982271B2 Semiconductor device 有权
标题翻译：半导体器件
公开(公告)号：US07982271B2
公开(公告)日：2011-07-19
申请号：US12901858
申请日：2010-10-11
申请人： Naozumi Morino , Atsushi Hiraiwa , Kazutoshi Oku , Toshiaki Ito , Motoshige Igarashi , Takayuki Sasaki , Masao Sugiyama , Hiroshi Yanagita , Shinichi Watarai
发明人： Naozumi Morino , Atsushi Hiraiwa , Kazutoshi Oku , Toshiaki Ito , Motoshige Igarashi , Takayuki Sasaki , Masao Sugiyama , Hiroshi Yanagita , Shinichi Watarai
IPC分类号： H01L29/76 , H01L29/94 , H01L31/062 , H01L31/113 , H01L31/119 , H01L27/01 , H01L27/12 , H01L31/0392 , H01L23/62
CPC分类号： H01L21/823892 , H01L27/0629 , H01L27/0928 , H01L2224/05554
摘要： There is provided a technology which allows improvements in manufacturing yield and product reliability in a semiconductor device having a triple well structure. A shallow p-type well is formed in a region different from respective regions in a p-type substrate where a deep n-type well, a shallow p-type well, and a shallow n-type well are formed. A p-type diffusion tap formed in the shallow p-type well is wired to a p-type diffusion tap formed in a shallow n-type well in the deep n-type well using an interconnection in a second layer. The respective gate electrodes of an nMIS and a pMIS each formed in the deep n-type well are coupled to the respective drain electrodes of an nMIS and a pMIS each formed in the substrate using an interconnection in a second or higher order layer.
摘要翻译：提供了一种在具有三重阱结构的半导体器件中提高制造产量和产品可靠性的技术。在形成深n型阱，浅P型阱和浅n型阱的p型衬底中，在与各个区域不同的区域中形成浅的p型阱。形成在浅p型阱中的p型扩散抽头使用在第二层中的互连在深n型阱中连接到形成在浅n型阱中的p型扩散阱。每个形成在深n型阱中的nMIS和pMIS的相应栅极电极使用在第二层或更高级层中的互连而在衬底中形成的nMIS和pMIS的相应漏电极耦合。

4. 发明申请

US20100328340A1 IMAGE PROCESSING DEVICE, IMAGE PROCESSING METHOD, AND IMAGE PROCESSING PROGRAM STORAGE MEDIUM 审中-公开
标题翻译：图像处理设备，图像处理方法和图像处理程序存储介质
公开(公告)号：US20100328340A1
公开(公告)日：2010-12-30
申请号：US12628744
申请日：2009-12-01
申请人： Hiroshi YANAGITA
发明人： Hiroshi YANAGITA
IPC分类号： G09G5/02 , G06K9/00
CPC分类号： H04N1/46
摘要： An image processing device including an input section, an image storage section, a storage area reserving section, a controller, and an output section is provided. The storage area reserving section reserves, when description data input via the input section indicates that a partial image including a transmission image is to be stored, a partial image area and an entire image area at the image storage section. The color space converter performs conversion using a first output color space conversion function that converts a description color space of the description data into an output color space that includes an entire image plane and a partial image plane. The controller converts the color-space converted partial image into an output image format and writes it in the partial image area, and converts the color-space converted entire image into an output image format and writes it in the entire image area.
摘要翻译：提供一种包括输入部分，图像存储部分，存储区域保留部分，控制器和输出部分的图像处理装置。当通过输入部分输入的描述数据指示要存储包括发送图像的部分图像，部分图像区域和图像存储部分的整个图像区域时，存储区域保留部分保留。色彩空间转换器使用将描述数据的描述颜色空间转换为包括整个图像平面和部分图像平面的输出颜色空间的第一输出颜色空间转换功能来执行转换。控制器将色彩空间转换的部分图像转换为输出图像格式并将其写入部分图像区域，并将色彩空间转换的整个图像转换为输出图像格式，并将其写入整个图像区域。

5. 发明申请

US20090278204A1 SEMICONDUCTOR DEVICE 失效
标题翻译：半导体器件
公开(公告)号：US20090278204A1
公开(公告)日：2009-11-12
申请号：US12422278
申请日：2009-04-12
申请人： Naozumi MORINO , Atsushi HIRAIWA , Kazutoshi OKU , Toshiaki ITO , Motoshige IGARASHI , Takayuki SASAKI , Masao SUGIYAMA , Hiroshi YANAGITA , Shinichi WATARAI
发明人： Naozumi MORINO , Atsushi HIRAIWA , Kazutoshi OKU , Toshiaki ITO , Motoshige IGARASHI , Takayuki SASAKI , Masao SUGIYAMA , Hiroshi YANAGITA , Shinichi WATARAI
IPC分类号： H01L27/088
CPC分类号： H01L21/823892 , H01L27/0629 , H01L27/0928 , H01L2224/05554
摘要： There is provided a technology which allows improvements in manufacturing yield and product reliability in a semiconductor device having a triple well structure. A shallow p-type well is formed in a region different from respective regions in a p-type substrate where a deep n-type well, a shallow p-type well, and a shallow n-type well are formed. A p-type diffusion tap formed in the shallow p-type well is wired to a p-type diffusion tap formed in a shallow n-type well in the deep n-type well using an interconnection in a second layer. The respective gate electrodes of an nMIS and a pMIS each formed in the deep n-type well are coupled to the respective drain electrodes of an nMIS and a pMIS each formed in the substrate using an interconnection in a second or higher order layer.
摘要翻译：提供了一种在具有三重阱结构的半导体器件中提高制造产量和产品可靠性的技术。在形成深n型阱，浅P型阱和浅n型阱的p型衬底中，在与各个区域不同的区域中形成浅的p型阱。形成在浅p型阱中的p型扩散抽头使用在第二层中的互连在深n型阱中连接到形成在浅n型阱中的p型扩散阱。每个形成在深n型阱中的nMIS和pMIS的相应栅极电极使用在第二层或更高级层中的互连而在衬底中形成的nMIS和pMIS的相应漏电极耦合。

6. 发明授权

US06808951B2 Semiconductor integrated circuit device and manufacturing method thereof 失效
标题翻译：半导体集成电路器件及其制造方法
公开(公告)号：US06808951B2
公开(公告)日：2004-10-26
申请号：US09987884
申请日：2001-11-16
申请人： Yoshihiro Ikeda , Tsutomu Okazaki , Keisuke Tsukamoto , Hiroshi Yanagita , Daisuke Okada
发明人： Yoshihiro Ikeda , Tsutomu Okazaki , Keisuke Tsukamoto , Hiroshi Yanagita , Daisuke Okada
IPC分类号： H01L2100
CPC分类号： H01L27/11521 , H01L27/115 , H01L27/11524
摘要： An insulating film for protecting an upper portion of a control gate electrode is constituted by a silicon oxide film, and thereby stress affecting a gate oxide film and a substrate that is located below a bottom portion thereof is reduced. Further, an etching prevention film consisting of a silicon nitride film is formed on a sidewall of the silicon oxide film, and thereby it is possible to prevent the sidewall of the silicon oxide film from being etched in a hydrofluoric acid cleaning step after processing of a gate electrode.
摘要翻译：用于保护控制栅电极的上部的绝缘膜由氧化硅膜构成，从而降低了影响栅极氧化膜和位于其底部下方的衬底的应力。此外，在氧化硅膜的侧壁上形成由氮化硅膜构成的防蚀膜，从而可以防止氧化硅膜的侧壁在氢氟酸清洗工序中被蚀刻栅电极。

7. 发明申请

US20110266631A1 SEMICONDUCTOR DEVICE 有权
公开(公告)号：US20110266631A1
公开(公告)日：2011-11-03
申请号：US13179163
申请日：2011-07-08
申请人： Naozumi MORINO , Atsushi HIRAIWA , Kazutoshi OKU , Toshiaki ITO , Motoshige IGARASHI , Takayuki SASAKI , Masao SUGIYAMA , Hiroshi YANAGITA , Shinichi WATARAI
发明人： Naozumi MORINO , Atsushi HIRAIWA , Kazutoshi OKU , Toshiaki ITO , Motoshige IGARASHI , Takayuki SASAKI , Masao SUGIYAMA , Hiroshi YANAGITA , Shinichi WATARAI
IPC分类号： H01L27/092
CPC分类号： H01L21/823892 , H01L27/0629 , H01L27/0928 , H01L2224/05554
摘要： There is provided a technology which allows improvements in manufacturing yield and product reliability in a semiconductor device having a triple well structure. A shallow p-type well is formed in a region different from respective regions in a p-type substrate where a deep n-type well, a shallow p-type well, and a shallow n-type well are formed. A p-type diffusion tap formed in the shallow p-type well is wired to a p-type diffusion tap formed in a shallow n-type well in the deep n-type well using an interconnection in a second layer. The respective gate electrodes of an nMIS and a pMIS each formed in the deep n-type well are coupled to the respective drain electrodes of an nMIS and a pMIS each formed in the substrate using an interconnection in a second or higher order layer.

8. 发明授权

US07553334B2 Defective product inspection apparatus, probe positioning method and probe moving method 有权
标题翻译：产品检验设备不良，探头定位方法和探头移动方法
公开(公告)号：US07553334B2
公开(公告)日：2009-06-30
申请号：US11976238
申请日：2007-10-23
申请人： Eiichi Hazaki , Yasuhiro Mitsui , Takashi Furukawa , Hiroshi Yanagita , Susumu Kato , Osamu Satou , Osamu Yamada , Yoshikazu Inada
发明人： Eiichi Hazaki , Yasuhiro Mitsui , Takashi Furukawa , Hiroshi Yanagita , Susumu Kato , Osamu Satou , Osamu Yamada , Yoshikazu Inada
IPC分类号： G01N13/10
CPC分类号： G01R31/2891 , G01N23/225 , G01R31/2887 , H01J37/20 , H01J37/226 , H01J37/28 , H01J2237/2007 , H01J2237/2008 , H01J2237/20221 , H01J2237/204 , H01J2237/24564 , H01J2237/2482
摘要： For adjusting a positional relationship between a specimen and a probe to measure an electric characteristic of the specimen through a contact therebetween, a base table holding a specimen table holding the specimen and a probe holder holding the probe is positioned at a first position to measure the positional relationship between the probe and the specimen at the first position, and subsequently positioned at a second position to measure the positional relationship therebetween at the second position so that the probe and the specimen are contact each other at the second position, the specimen table and the probe holder are movable with respect to each other on the base table at each of the first and second positions to adjust the positional relationship between the probe and the specimen, and a measuring accuracy at the second position is superior to a measuring accuracy at the first position.
摘要翻译：为了调整试样与探针之间的位置关系，通过它们之间的接触测量试样的电特性，将保持试样的试样台的基台和保持探针的探针架固定在第一位置，以测量在第一位置处的探针和样本之间的位置关系，并且随后位于第二位置以测量其在第二位置处的位置关系，使得探针和样本在第二位置彼此接触，样本台和探针支架能够在基台上在第一和第二位置中的每一个处相对于彼此移动，以调节探针与样本之间的位置关系，并且第二位置处的测量精度优于第一名

9. 发明授权

US07297945B2 Defective product inspection apparatus, probe positioning method and probe moving method 有权
标题翻译：产品检验设备不良，探头定位方法和探头移动方法
公开(公告)号：US07297945B2
公开(公告)日：2007-11-20
申请号：US11002710
申请日：2004-12-03
申请人： Eiichi Hazaki , Yasuhiro Mitsui , Takashi Furukawa , Hiroshi Yanagita , Susumu Kato , Osamu Satou , Osamu Yamada , Yoshikazu Inada
发明人： Eiichi Hazaki , Yasuhiro Mitsui , Takashi Furukawa , Hiroshi Yanagita , Susumu Kato , Osamu Satou , Osamu Yamada , Yoshikazu Inada
IPC分类号： G01N23/00
CPC分类号： G01R31/2891 , G01N23/225 , G01R31/2887 , H01J37/20 , H01J37/226 , H01J37/28 , H01J2237/2007 , H01J2237/2008 , H01J2237/20221 , H01J2237/204 , H01J2237/24564 , H01J2237/2482
摘要： For adjusting a positional relationship between a specimen and a probe to measure an electric characteristic of the specimen through a contact therebetween, a base table holding a specimen table holding the specimen and a probe holder holding the probe is positioned at a first position to measure the positional relationship between the probe and the specimen at the first position, and subsequently positioned at a second position to measure the positional relationship therebetween at the second position so that the probe and the specimen are contact each other at the second position, the specimen table and the probe holder are movable with respect to each other on the base table at each of the first and second positions to adjust the positional relationship between the probe and the specimen, and a measuring accuracy at the second position is superior to a measuring accuracy at the first position.
摘要翻译：为了调整试样与探针之间的位置关系，通过它们之间的接触测量试样的电特性，将保持试样的试样台的基台和保持探针的探针架固定在第一位置，以测量在第一位置处的探针和样本之间的位置关系，并且随后位于第二位置以测量其在第二位置处的位置关系，使得探针和样本在第二位置彼此接触，样本台和探针支架能够在基台上在第一和第二位置中的每一个处相对于彼此移动，以调节探针与样本之间的位置关系，并且第二位置处的测量精度优于第一名

10. 发明授权

US07001808B2 Semiconductor integrated circuit device having a dummy conductive film and method of manufacturing the same 有权
标题翻译：具有虚拟导电膜的半导体集成电路器件及其制造方法
公开(公告)号：US07001808B2
公开(公告)日：2006-02-21
申请号：US10786334
申请日：2004-02-26
申请人： Keisuke Tsukamoto , Yoshihiro Ikeda , Tsutomu Okazaki , Daisuke Okada , Hiroshi Yanagita
发明人： Keisuke Tsukamoto , Yoshihiro Ikeda , Tsutomu Okazaki , Daisuke Okada , Hiroshi Yanagita
IPC分类号： H01L31/336
CPC分类号： H01L27/11526 , H01L27/105 , H01L27/11543
摘要： Defects in element forming regions on which memory cells of a non-volatile memory are formed are to be diminished to reduce leakage current. End portions of element forming regions with non-volatile memory cells formed thereon are extended a length D by utilizing the region which underlies a dummy conductive film, whereby a stress induced from an insulating film which surrounds the element forming regions is concentrated on the extended region. As a result, defects do not extend up to the regions where memory cells are formed and therefore it is possible to reduce leakage current in the memory cells.
摘要翻译：在其上形成非易失性存储器的存储单元的元件形成区域中的缺陷将被减小以减少泄漏电流。在其上形成有非易失性存储单元的元件形成区域的端部通过利用虚设导电膜下面的区域而延伸长度D，由此围绕元件形成区域的绝缘膜引起的应力集中在延伸区域上。结果，缺陷不延伸到形成存储单元的区域，因此可以减少存储单元中的漏电流。

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