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1. 发明授权

US08898671B2 Processor that executes a plurality of threads by promoting efficiency of transfer of data that is shared with the plurality of threads 有权
标题翻译：处理器，其通过提高与所述多个线程共享的数据的传送效率来执行多个线程
公开(公告)号：US08898671B2
公开(公告)日：2014-11-25
申请号：US13393967
申请日：2011-07-06
申请人： Hiroyuki Morishita
发明人： Hiroyuki Morishita
IPC分类号： G06F9/46 , G06F9/26 , G06F13/00 , G06F12/00 , G06F7/00 , G06F9/48 , G06F9/38 , G06F9/30
CPC分类号： G06F9/3009 , G06F9/30047 , G06F9/30076 , G06F9/3834 , G06F9/3838 , G06F9/3851 , G06F9/4812 , G06F9/4843 , G06F9/526
摘要： Provide is a processor that can maintain a dependency relationship between a plurality of instructions and one read instruction. The processor comprises: a setting unit configured to set, when an instruction that exists at a location ensuring that writing into a memory area has been completed is executed, usage information indicating whether writing into the memory area has been completed such that the usage information indicates that writing into a memory area during execution of one thread has been completed; and a control unit configured to (i) perform execution of a read instruction to read data stored in the memory area when the usage information indicates that writing into the memory area during execution of the one thread has been completed, and (ii) suppress execution of the read instruction when the usage information indicates that writing into the memory area during execution of the one thread has not been completed.
摘要翻译：提供是可以维持多个指令和一个读取指令之间的依赖关系的处理器。处理器包括：设置单元，被配置为当确保存储在存储区域中的写入的位置处的指令已经完成时，设置指示是否已经完成了对存储区域的写入的使用信息，使得使用信息指示在一个线程的执行过程中写入一个内存区域已经完成; 以及控制单元，被配置为当所述使用信息指示在所述一个线程的执行期间写入到所述存储区域中时，执行读取指令来读取存储在所述存储区域中的数据的执行，以及（ii）抑制执行当使用信息指示在一个线程的执行期间写入存储区域尚未完成时，读取指令。

2. 发明授权

US08788793B2 Instruction issue to plural computing units from plural stream buffers based on priority in instruction order table 有权
标题翻译：根据指令顺序表中的优先级从多个流缓冲器向多个计算单元发出指令
公开(公告)号：US08788793B2
公开(公告)日：2014-07-22
申请号：US13320668
申请日：2010-05-18
申请人： Hiroyuki Morishita
发明人： Hiroyuki Morishita
IPC分类号： G06F9/30 , G06F9/38
CPC分类号： G06F9/3851 , G06F9/3889
摘要： A processor including L computing units, L being an integer of 2 or greater, the processor comprising: an instruction buffer including M×Z instruction storage areas each storing one instruction, M instruction streams being input in a state of being distinguished from each other, each of the M instruction streams including Z instructions, M and Z each being an integer of 2 or greater, M×Z being equal to or greater than L; an order information holding unit holding order information that indicates an order of the M×Z instruction storage areas; an extraction unit operable to extract instructions from the M×Z instruction storage areas; and a control unit operable to cause the extraction unit to extract L instructions in executable state from the M×Z instruction storage areas in accordance with the order indicated by the order information, and input the instructions into different ones of the L computing units.
摘要翻译：一种处理器，包括L个计算单元，L为2或更大的整数，所述处理器包括：指令缓冲器，包括M×Z指令存储区域，每个指令存储区域存储一个指令，M个指令流以彼此区分的状态输入; 每个M个指令流包括Z指令，M和Z各自为2或更大的整数，M×Z等于或大于L; 订单信息保存单元，保存指示M×Z指令存储区域的顺序的订单信息; 提取单元，用于从M×Z指令存储区域中提取指令; 以及控制单元，其可操作以使得所述提取单元根据所述订单信息指示的顺序从所述M×Z指令存储区域提取处于可执行状态的L指令，并且将所述指令输入到所述L个计算单元中的不同的计算单元。

3. 发明授权

US08433884B2 Multiprocessor 有权
标题翻译：多处理器
公开(公告)号：US08433884B2
公开(公告)日：2013-04-30
申请号：US12674052
申请日：2009-06-16
申请人： Hiroyuki Morishita
发明人： Hiroyuki Morishita
IPC分类号： G06F9/312
CPC分类号： G06F9/544 , G06F9/3009 , G06F9/30123 , G06F9/3851 , G06F9/3857 , G06F9/3877 , G06F9/3885
摘要： A multiprocessor executes a plurality of threads without decreasing execution efficiency. The multiprocessor includes a first processor allocating a different register file to each of a predetermined number of threads to be executed from among plural threads, and executing the predetermined number of threads in parallel; and a second processor performing processing according to a processing request made by the first processor. The first processor has areas allocated to the plurality of threads in one-to-one correspondence, makes the processing request to the second processor according to an instruction included in one of the predetermined number of threads, upon receiving a request for writing a value resulting from the processing from the second processor, judges whether the one thread is being executed, and when judging negatively, performs control such that the obtained value is written into one of the areas allocated to the one thread.
摘要翻译：多处理器执行多个线程而不降低执行效率。多处理器包括：第一处理器，其从多个线程中分配不同的寄存器文件到要执行的预定数量的线程，并且并行执行预定数量的线程; 以及第二处理器，其根据由所述第一处理器进行的处理请求执行处理。第一处理器具有以一一对应的方式分配给多个线程的区域，在接收到写入值的请求时，根据包含在预定数量的线程之一中的指令向第二处理器发送处理请求从第二处理器的处理中，判断一个线程是否正在执行，并且当判断为否定时，执行控制，使得所获得的值被写入分配给一个线程的区域之一。

4. 发明申请

US20110113220A1 MULTIPROCESSOR 有权
标题翻译：多用户
公开(公告)号：US20110113220A1
公开(公告)日：2011-05-12
申请号：US12674052
申请日：2009-06-16
申请人： Hiroyuki Morishita
发明人： Hiroyuki Morishita
IPC分类号： G06F15/76 , G06F9/02
CPC分类号： G06F9/544 , G06F9/3009 , G06F9/30123 , G06F9/3851 , G06F9/3857 , G06F9/3877 , G06F9/3885
摘要： Provided is a multiprocessor capable of executing a plurality of threads without decreasing execution efficiency.The multiprocessor includes: a first processor allocating a different register file to each of a predetermined number of threads to be executed from among plural threads, and executing the predetermined number of threads in parallel; and a second processor performing processing according to a processing request made by the first processor. The first processor has areas allocated to the plurality of threads in one-to-one correspondence, makes the processing request to the second processor according to an instruction included in one of the predetermined number of threads, upon receiving a request for writing a value resulting from the processing from the second processor, judges whether the one thread is being executed, and when judging negatively, performs control such that the obtained value is written into one of the areas allocated to the one thread.
摘要翻译：提供了能够执行多个线程而不降低执行效率的多处理器。多处理器包括：第一处理器，从多个线程中分配不同的寄存器文件到预定数量的要执行的线程，并且并行执行预定数量的线程; 以及第二处理器，其根据由所述第一处理器进行的处理请求执行处理。第一处理器具有以一一对应的方式分配给多个线程的区域，在接收到写入值的请求时，根据包含在预定数量的线程之一中的指令向第二处理器发送处理请求从第二处理器的处理中，判断一个线程是否正在执行，并且当判断为否定时，执行控制，使得所获得的值被写入分配给一个线程的区域之一。

5. 发明申请

US20100174884A1 PROCESSOR HAVING RECONFIGURABLE ARITHMETIC ELEMENT 审中-公开
标题翻译：具有可重构算术元素的处理器
公开(公告)号：US20100174884A1
公开(公告)日：2010-07-08
申请号：US12159271
申请日：2006-11-09
申请人： Hiroyuki Morishita , Takao Yamamoto , Masaitsu Nakajima
发明人： Hiroyuki Morishita , Takao Yamamoto , Masaitsu Nakajima
IPC分类号： G06F9/302 , G06F9/30 , G06F15/80 , G06F9/06
CPC分类号： G06F9/3885 , G06F9/30014 , G06F9/30181 , G06F9/3897
摘要： A processor (101) in which a plurality of arithmetic elements executing instructions are embedded includes: fixed function arithmetic elements (121 to 123) each having a circuit configuration that is not dynamically reconfigurable; a reconfigurable arithmetic element (125) having a circuit configuration that is dynamically reconfigurable; and an arithmetic operation control unit (113) which allocates instructions to the fixed function arithmetic elements (121 to 123) and the reconfigurable arithmetic element (125) and issues the allocated instructions to the respective arithmetic elements.
摘要翻译：其中嵌入执行指令的多个运算元件的处理器（101）包括：每个具有不能动态重新配置的电路配置的固定功能运算元件（121至123）具有可动态重新配置的电路配置的可重构算术元件（125）; 以及向所述固定功能运算元件（121〜123）和所述可重构运算元件（125）分配指令的运算控制单元（113），并且将分配的指令发布给各个运算元件。

6. 发明申请

US20080282061A1 Array Type Operation Device 有权
标题翻译：阵列类型操作装置
公开(公告)号：US20080282061A1
公开(公告)日：2008-11-13
申请号：US11572701
申请日：2005-08-02
申请人： Hiroyuki Morishita , Takeshi Tanaka , Masaki Maeda , Yorihiko Wakayama
发明人： Hiroyuki Morishita , Takeshi Tanaka , Masaki Maeda , Yorihiko Wakayama
IPC分类号： G06F15/80 , G06F9/30
CPC分类号： G06F15/8007 , G06F1/3203 , G06F9/3842 , G06F9/3885 , H04N19/43 , H04N19/61
摘要： An array calculation device that includes a processor array composed of a plurality of processor elements having been assigned with orders, acquires an instruction in each cycle, generates, in each cycle, operation control information for controlling an operation of a processor element of a first order, and then generates an instruction to the processor element of the first order in accordance with the operation control information and the acquired instruction, and also generates, in each cycle, operation control information for controlling an operation of each processor element of a next order and onwards, in accordance with operation control information generated for controlling an operation of a processor element of an immediately preceding order, and then generates an instruction to each processor element of the next order and onwards, in accordance with the operation control information generated and the acquired instruction.
摘要翻译：一种阵列计算装置，包括由已经被分配了多个处理器元件的处理器阵列组成的处理器阵列，获取每个周期中的指令，在每个周期中生成用于控制一阶处理器元件的操作的操作控制信息，然后根据操作控制信息和获取的指令向第一级处理器单元生成指令，并且在每个周期中还生成用于控制下一个订单的每个处理器元件的操作的操作控制信息，以及根据生成的用于控制紧接在前的顺序的处理器元件的操作的操作控制信息，然后根据产生的和所获取的操作控制信息产生对下一个订单的每个处理器元件的指令指令。

7. 发明授权

US07315934B2 Data processor and program for processing a data matrix 有权
标题翻译：用于处理数据矩阵的数据处理器和程序
公开(公告)号：US07315934B2
公开(公告)日：2008-01-01
申请号：US10377328
申请日：2003-02-28
申请人： Hiroyuki Morishita , Atsushi Ito , Satoshi Takashima , Hideshi Nishida , Kozo Kimura , Tokuzo Kiyohara , Akira Miyoshi , Hiroshi Kadota
发明人： Hiroyuki Morishita , Atsushi Ito , Satoshi Takashima , Hideshi Nishida , Kozo Kimura , Tokuzo Kiyohara , Akira Miyoshi , Hiroshi Kadota
IPC分类号： G06F15/76
CPC分类号： G06F9/3012 , G06F9/30036 , G06F9/3824 , G06F9/3885
摘要： A data processor has sixteen processing elements that each include a register file and an arithmetic logic unit. A network unit connects between the register files of the processing elements and the arithmetic logic units of the processing elements. The network unit has a selector for simultaneously performing a plurality of data transfers which are each made from a register file of one processing element to an operation unit of another processing element. With the provision of this selector that can perform such simultaneous data transfers, the processing efficiency of the processing elements can be maintained even if a change occurs in operand assignments and the like.
摘要翻译：数据处理器具有16个处理元件，每个处理元件包括寄存器文件和算术逻辑单元。网络单元连接处理元件的寄存器文件和处理元件的算术逻辑单元。网络单元具有选择器，用于同时执行多个数据传送，每个数据传输由一个处理元件的寄存器文件制成到另一个处理元件的操作单元。通过提供可以执行这种同时数据传输的该选择器，即使在操作数分配等中发生改变，也可以保持处理元件的处理效率。

8. 发明授权

US07294410B2 Method of coating with lead-free electrodeposition coating composition and coated article 失效
标题翻译：无铅电沉积涂料组合物和涂层制品的涂布方法
公开(公告)号：US07294410B2
公开(公告)日：2007-11-13
申请号：US10547909
申请日：2004-03-03
申请人： Hiroyuki Morishita , Katsuyoshi Kaneko , Fumiaki Niisato , Toshiyuki Ishii
发明人： Hiroyuki Morishita , Katsuyoshi Kaneko , Fumiaki Niisato , Toshiyuki Ishii
IPC分类号： B32B15/08 , B32B15/18 , C25D13/08 , B62D63/04
CPC分类号： C25D13/10 , C09D5/4492 , Y10T428/12569 , Y10T428/12611 , Y10T428/12799 , Y10T428/31678
摘要： The present invention relates to a cationic electrodeposition coating composition substantially free of lead compounds, and more specifically to a method of coating an alloyed hot-dip galvanized steel plate with the composition and a coated article obtained by the method having edge portions and general surfaces excellent in corrosion resistance. The invention provides a method of coating an alloyed hotdip galvanized steel plate with a lead-free cationic electrodeposition coating composition containing a rust preventive pigment to form an electrodeposition coating film excellent in corrosion resistance, and a coated article obtained by the electrodeposition.
摘要翻译：本发明涉及一种基本上不含铅化合物的阳离子电沉积涂料组合物，更具体地涉及一种涂覆合金化的热浸镀锌钢板的方法，该组合物和通过该方法获得的涂层制品具有优异的边缘部分和一般表面耐腐蚀性。本发明提供了一种用含有防锈颜料的无铅阳离子电沉积涂料组合物涂覆合金化的热镀锌钢板的方法，以形成耐腐蚀性优异的电沉积涂膜，以及通过电沉积获得的涂布制品。

9. 发明申请

US20070167582A1 Lead-free electrodeposition coating composition and coated article 失效
标题翻译：无铅电沉积涂料组合物和涂层制品
公开(公告)号：US20070167582A1
公开(公告)日：2007-07-19
申请号：US10547908
申请日：2004-03-03
申请人： Hiroyuki Morishita , Katsuyoshi Kaneko , Fumiaki Niisato , Toshiyuki Ishii , Kageki Fujimoto
发明人： Hiroyuki Morishita , Katsuyoshi Kaneko , Fumiaki Niisato , Toshiyuki Ishii , Kageki Fujimoto
IPC分类号： C08F8/00
CPC分类号： C08G18/8077 , C08G18/58 , C08G18/8012 , C08G18/8064 , C09D5/4492 , Y10T428/31504 , Y10T428/31511 , Y10T428/31515 , Y10T428/31522 , Y10T428/31529
摘要： The present invention relates to a cationic electrodeposition coating composition substantially free of lead compounds, which is excellent in curability and can be finish-coated with a splendid appearance, and an article coated with the composition. The invention provides a lead-free electrodeposition coating composition excellent in curability and a coated article, the composition being capable of forming a coating film, which emits less tin compounds to have no influence on appearance of a finish coating film and film performances.
摘要翻译：本发明涉及一种基本上不含铅化合物的阳离子电沉积涂料组合物，该组合物具有优异的固化性，并且可以用美丽的外观进行表面涂覆，以及涂有该组合物的制品。本发明提供了一种固化性优异的无铅电沉积涂料组合物和涂层制品，该组合物能够形成涂膜，其发出较少的锡化合物，从而不影响涂饰膜的外观和膜性能。

10. 发明授权

US09317287B2 Multiprocessor system 有权
标题翻译：多处理器系统
公开(公告)号：US09317287B2
公开(公告)日：2016-04-19
申请号：US14232389
申请日：2012-06-06
申请人： Hiroyuki Morishita
发明人： Hiroyuki Morishita
IPC分类号： G06F9/38 , G06F9/30 , G06F11/36 , G06F9/00
CPC分类号： G06F9/30145 , G06F9/30185 , G06F9/3836 , G06F9/3877 , G06F11/362
摘要： To provide a multi-processor system that efficiently debugs operations of one processor and operations of another processor. The multiprocessor system has a first processor and a second processor that executes processing by receiving notification from the first processor. The first processor: sequentially specifies instructions to be executed from an instruction queue; sends a notification based on a processing request instruction to the second processor when an instruction that is specified is the processing request instruction; executes the instruction that is specified when the instruction that is specified is not the processing request instruction; and determines whether or not a debug mode is set. When the first processor determines that the debug mode is set, the first processor stops specifying instructions after specifying the processing request instruction, and, after sending the notification, resumes specifying instructions after detecting that the second processor has completed processing corresponding to the notification.
摘要翻译：提供有效调试一个处理器的操作和另一个处理器的操作的多处理器系统。多处理器系统具有通过从第一处理器接收通知来执行处理的第一处理器和第二处理器。第一处理器：从指令队列中顺序指定要执行的指令; 当指定的指令是处理请求指令时，基于处理请求指令向第二处理器发送通知; 当指定的指令不是处理请求指令时执行指定的指令; 并确定是否设置了调试模式。当第一处理器确定调试模式被设置时，第一处理器在指定处理请求指令之后停止指定指令，并且在发送通知之后，在检测到第二处理器已经完成与通知相对应的处理之后恢复指定指令。

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