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1. 发明授权

US09317287B2 Multiprocessor system 有权
标题翻译：多处理器系统
公开(公告)号：US09317287B2
公开(公告)日：2016-04-19
申请号：US14232389
申请日：2012-06-06
申请人： Hiroyuki Morishita
发明人： Hiroyuki Morishita
IPC分类号： G06F9/38 , G06F9/30 , G06F11/36 , G06F9/00
CPC分类号： G06F9/30145 , G06F9/30185 , G06F9/3836 , G06F9/3877 , G06F11/362
摘要： To provide a multi-processor system that efficiently debugs operations of one processor and operations of another processor. The multiprocessor system has a first processor and a second processor that executes processing by receiving notification from the first processor. The first processor: sequentially specifies instructions to be executed from an instruction queue; sends a notification based on a processing request instruction to the second processor when an instruction that is specified is the processing request instruction; executes the instruction that is specified when the instruction that is specified is not the processing request instruction; and determines whether or not a debug mode is set. When the first processor determines that the debug mode is set, the first processor stops specifying instructions after specifying the processing request instruction, and, after sending the notification, resumes specifying instructions after detecting that the second processor has completed processing corresponding to the notification.
摘要翻译：提供有效调试一个处理器的操作和另一个处理器的操作的多处理器系统。多处理器系统具有通过从第一处理器接收通知来执行处理的第一处理器和第二处理器。第一处理器：从指令队列中顺序指定要执行的指令; 当指定的指令是处理请求指令时，基于处理请求指令向第二处理器发送通知; 当指定的指令不是处理请求指令时执行指定的指令; 并确定是否设置了调试模式。当第一处理器确定调试模式被设置时，第一处理器在指定处理请求指令之后停止指定指令，并且在发送通知之后，在检测到第二处理器已经完成与通知相对应的处理之后恢复指定指令。

2. 发明授权

US09201899B2 Transposition operation device, integrated circuit for the same, and transposition method 有权
标题翻译：换位操作装置，集成电路相同，换位方式
公开(公告)号：US09201899B2
公开(公告)日：2015-12-01
申请号：US13824865
申请日：2012-09-11
申请人： Takashi Nishimura , Hiroyuki Morishita
发明人： Takashi Nishimura , Hiroyuki Morishita
IPC分类号： G06F17/30 , G06F9/30
CPC分类号： G06F17/30244 , G06F9/30032 , G06F9/30036 , G06F9/30109
摘要： A transposition operation device includes: a register group storing a matrix of data such that elements are readable one at a time; an output data rearrangement unit rearranging elements in each row of the matrix so that elements in a same column of the matrix are in different columns of the matrix after rearrangement; a register access unit writing the matrix after rearrangement to the register group and reading the elements in the same column by using column position information indicating positions in the register group at which the elements in the same column are stored; an input data rearrangement unit rearranging the read elements; an operation unit performing an operation on the rearranged elements; and a transposition control unit generating rearrangement information and the column position information to control rearrangement, and performs transposition at high speed by performing rearrangement at the time of storing/reading data in/from the register group.
摘要翻译：移位操作装置包括：存储数据矩阵的寄存器组，使得元素一次可读; 输出数据重排单元重新排列矩阵的每行中的元素，使得矩阵的同一列中的元素在重新排列之后处于矩阵的不同列中; 寄存器访问单元，通过使用指示存储同一列中的元素的寄存器组中的位置的列位置信息，将重排后的矩阵写入寄存器组并读取同一列中的元素; 输入数据重排单元重新排列读取的元件; 对重新排列的元件执行操作的操作单元; 以及转置控制单元，其生成重排信息和列位置信息以控制重排，并且通过在从寄存器组中存储/读取数据时执行重排来高速执行转置。

3. 发明授权

US07926055B2 Processor capable of reconfiguring a logical circuit 有权
标题翻译：能够重新配置逻辑电路的处理器
公开(公告)号：US07926055B2
公开(公告)日：2011-04-12
申请号：US11574359
申请日：2006-04-12
申请人： Hiroyuki Morishita , Takashi Hashimoto , Tokuzo Kiyohara
发明人： Hiroyuki Morishita , Takashi Hashimoto , Tokuzo Kiyohara
IPC分类号： G06F9/46
CPC分类号： G06F15/7867 , G06F9/30076 , G06F9/3851 , G06F9/3867 , G06F9/3885 , G06F9/3897
摘要： The present invention provides a processor that cyclically executes a plurality of threads in accordance with an execution time allocated to each of the threads, comprising a reconfigurable integrated circuit. The processor stores circuit configuration information sets respectively corresponding to the plurality of threads, reconfigures a part of the integrated circuit based on the circuit configuration information sets, and sequentially executes each thread using the integrated circuit that has been reconfigured based on one of the configuration information sets that corresponds to the thread. While executing a given thread, the processor selects a thread to be executed next, and reconfigures a part of the integrated circuit where is not currently used for execution of the given thread, based on a circuit configuration information set corresponding to the selected thread.
摘要翻译：本发明提供了一种根据分配给每个线程的执行时间循环地执行多个线程的处理器，包括可重构集成电路。处理器存储分别对应于多个线程的电路配置信息集合，基于电路配置信息集重配置集成电路的一部分，并且使用基于配置信息之一重新配置的集成电路来顺序地执行每个线程设置对应于线程。在执行给定的线程的同时，处理器根据与所选择的线程对应的电路配置信息，选择要执行的线程，并重新配置当前不用于执行给定线程的集成电路的一部分。

4. 发明授权

US07716391B2 Data transfer apparatus, data transfer method, and program 有权
标题翻译：数据传输装置，数据传输方法和程序
公开(公告)号：US07716391B2
公开(公告)日：2010-05-11
申请号：US11382379
申请日：2006-05-09
申请人： Kazuya Furukawa , Nobuo Higaki , Hideyo Tsuruta , Kazushi Kurata , Shigeki Fujii , Kousuke Yoshioka , Hiroyuki Morishita
发明人： Kazuya Furukawa , Nobuo Higaki , Hideyo Tsuruta , Kazushi Kurata , Shigeki Fujii , Kousuke Yoshioka , Hiroyuki Morishita
IPC分类号： G06F3/00
CPC分类号： G06F3/0221 , G06F13/28 , Y02D10/14
摘要： A data transfer apparatus according to the present invention has; a DMAC and another DMAC which transfer data by direct memory access among a plurality of buses; a command queue which holds, as a queue, commands for instructing the data transfer; a bus information obtainment unit which obtains the commands from the command queue; a grouping unit which groups the held commands, based on a source and a destination designated in each of the obtained commands; a schedule unit which decides an order of issuing the commands sequentially from a group having more command, as a priority; and a selector which selects a command to be issued according to the decided order.
摘要翻译：根据本发明的数据传送装置具有： DMAC和另一个DMAC，其通过多个总线之间的直接存储器访问来传送数据; 作为队列保存用于指示数据传送的命令的命令队列; 总线信息获取单元，其从命令队列获取命令; 分组单元，其基于在每个所获得的命令中指定的源和目的地对保持的命令进行分组; 作为优先级，从具有更多命令的组中顺序地确定发出命令的顺序的调度单元; 以及选择器，其根据所决定的顺序选择要发出的命令。

5. 发明申请

US20070028055A1 Cache memory and cache memory control method 审中-公开
标题翻译：缓存内存和缓存内存控制方式
公开(公告)号：US20070028055A1
公开(公告)日：2007-02-01
申请号：US10571531
申请日：2004-08-23
申请人： Tetsuya Tanaka , Ryuta Nakanishi , Tokuzo Kiyohara , Hiroyuki Morishita , Keishi Chikamura
发明人： Tetsuya Tanaka , Ryuta Nakanishi , Tokuzo Kiyohara , Hiroyuki Morishita , Keishi Chikamura
IPC分类号： G06F12/00
CPC分类号： G06F12/127 , G06F12/124
摘要： A cache memory of the present invention includes: for each cache entry, way 0 to way 3 which hold use flags U indicating whether or not the use flags U have been accessed; and a control unit which: updates, when a cache entry is hit, a use flag U corresponding to the hit cache entry so that the use flag U indicates that the cache entry has been accessed; and reset, in the case where all other use flags in the same set indicates that the cache entries have been accessed herein, the all other use flags so that the use flags indicate that the cache entries have not been accessed; and select a cache entry to be replaced from among the cache entries corresponding to the use flags indicating that the cache entries have not been accessed.
摘要翻译：本发明的高速缓存存储器包括：对于每个高速缓存条目，方式0到路径3，其保持使用标志U，指示是否已经访问了使用标志U; 以及控制单元，其在高速缓存条目被命中时更新与所述命中高速缓存条目对应的使用标志U，使得所述使用标志U指示所述高速缓存条目已经被访问; 并且在同一集合中的所有其他使用标志指示已经在这里访问了高速缓存条目的情况下，复位所有其他使用标志，使得使用标志指示高速缓存条目未被访问; 并且从与指示高速缓存条目未被访问的使用标志相对应的高速缓存条目中选择要替换的高速缓存条目。

6. 发明授权

US06233948B1 Control apparatus for a plurality of cryopumps 有权
标题翻译：用于多个低温泵的控制装置
公开(公告)号：US06233948B1
公开(公告)日：2001-05-22
申请号：US09504385
申请日：2000-02-15
申请人： Hiroyuki Morishita , Satoru Uosaki
发明人： Hiroyuki Morishita , Satoru Uosaki
IPC分类号： B01D800
CPC分类号： F04B49/00 , F04B37/08 , F25B9/10 , F25B49/02 , F25B2309/002 , Y10S417/901
摘要： For simultaneously controlling a plurality of cryopumps, one processor and communication conversion sections of the respective cryopumps are connected to each other with a communication network. The processor and a host computer are connected to each other with an exclusive line. The processor controls the cryopumps in time division by performing data exchange with the communication conversion sections of the cryopumps by means of packet exchange, line exchange and the like via the communication network. Thus, the need of providing exclusive processors for the cryopumps, respectively, is eliminated, allowing a large extent of cost reduction as well as a wiring simplification to be realized.
摘要翻译：为了同时控制多个低温泵，各个低温泵的一个处理器和通信转换部分通过通信网络相互连接。处理器和主机通过专用线相互连接。处理器通过经由通信网络的分组交换，线路交换等与低温泵的通信转换部分进行数据交换来对时间分割进行控制。因此，分别为低温泵提供专用处理器的需要被消除，从而允许大量的成本降低以及实现布线简化。

7. 发明申请

US20140003742A1 TRANSPOSITION OPERATION DEVICE, INTEGRATED CIRCUIT FOR THE SAME, AND TRANSPOSITION METHOD 有权
标题翻译：传输操作装置，用于其的集成电路和传输方法
公开(公告)号：US20140003742A1
公开(公告)日：2014-01-02
申请号：US13824865
申请日：2012-09-11
申请人： Takashi Nishimura , Hiroyuki Morishita
发明人： Takashi Nishimura , Hiroyuki Morishita
IPC分类号： G06F17/30
CPC分类号： G06F17/30244 , G06F9/30032 , G06F9/30036 , G06F9/30109
摘要： A transposition operation device includes: a register group storing a matrix of data such that elements are readable one at a time; an output data rearrangement unit rearranging elements in each row of the matrix so that elements in a same column of the matrix are in different columns of the matrix after rearrangement; a register access unit writing the matrix after rearrangement to the register group and reading the elements in the same column by using column position information indicating positions in the register group at which the elements in the same column are stored; an input data rearrangement unit rearranging the read elements; an operation unit performing an operation on the rearranged elements; and a transposition control unit generating rearrangement information and the column position information to control rearrangement, and performs transposition at high speed by performing rearrangement at the time of storing/reading data in/from the register group.
摘要翻译：移位操作装置包括：存储数据矩阵的寄存器组，使得元素一次可读; 输出数据重排单元重新排列矩阵的每行中的元素，使得矩阵的同一列中的元素在重新排列之后处于矩阵的不同列中; 寄存器访问单元，通过使用指示存储同一列中的元素的寄存器组中的位置的列位置信息，将重排后的矩阵写入寄存器组并读取同一列中的元素; 输入数据重排单元重新排列读取的元件; 对重新排列的元件执行操作的操作单元; 以及转置控制单元，其生成重排信息和列位置信息以控制重排，并且通过在从寄存器组中存储/读取数据时执行重新排列而高速执行转置。

8. 发明申请

US20120060017A1 PROCESSOR 有权
标题翻译：处理器
公开(公告)号：US20120060017A1
公开(公告)日：2012-03-08
申请号：US13320668
申请日：2010-05-18
申请人： Hiroyuki Morishita
发明人： Hiroyuki Morishita
IPC分类号： G06F9/30 , G06F9/38
CPC分类号： G06F9/3851 , G06F9/3889
摘要： A processor including L computing units, L being an integer of 2 or greater, the processor comprising: an instruction buffer including M×Z instruction storage areas each storing one instruction, M instruction streams being input in a state of being distinguished from each other, each of the M instruction streams including Z instructions, M and Z each being an integer of 2 or greater, M×Z being equal to or greater than L; an order information holding unit holding order information that indicates an order of the M×Z instruction storage areas; an extraction unit operable to extract instructions from the M×Z instruction storage areas; and a control unit operable to cause the extraction unit to extract L instructions in executable state from the M×Z instruction storage areas in accordance with the order indicated by the order information, and input the instructions into different ones of the L computing units.
摘要翻译：一种处理器，包括L个计算单元，L为2或更大的整数，所述处理器包括：指令缓冲器，包括M×Z指令存储区域，每个指令存储区域存储一个指令，M个指令流以彼此区分的状态输入; 每个M个指令流包括Z指令，M和Z各自为2或更大的整数，M×Z等于或大于L; 订单信息保存单元，保存指示M×Z指令存储区域的顺序的订单信息; 提取单元，用于从M×Z指令存储区域中提取指令; 以及控制单元，其可操作以使得所述提取单元根据所述订单信息指示的顺序从所述M×Z指令存储区域提取处于可执行状态的L指令，并且将所述指令输入到所述L个计算单元中的不同的计算单元。

9. 发明申请

US20060124462A1 Method of coating with lead-free electrodeposition coating composition and coated article 失效
标题翻译：无铅电沉积涂料组合物和涂层制品的涂布方法
公开(公告)号：US20060124462A1
公开(公告)日：2006-06-15
申请号：US10547909
申请日：2004-03-03
申请人： Hiroyuki Morishita , Katsuyoshi Kaneko , Fumiaki Nisato , Toshiyuki Ishii
发明人： Hiroyuki Morishita , Katsuyoshi Kaneko , Fumiaki Nisato , Toshiyuki Ishii
IPC分类号： C25B7/00 , C09D5/44
CPC分类号： C25D13/10 , C09D5/4492 , Y10T428/12569 , Y10T428/12611 , Y10T428/12799 , Y10T428/31678
摘要： The present invention relates to a cationic electrodeposition coating composition substantially free of lead compounds, and more specifically to a method of coating an alloyed hot-dip galvanized steel plate with the composition and a coated article obtained by the method having edge portions and general surfaces excellent in corrosion resistance. The invention provides a method of coating an alloyed hotdip galvanized steel plate with a lead-free cationic electrodeposition coating composition containing a rust preventive pigment to form an electrodeposition coating film excellent in corrosion resistance, and a coated article obtained by the electrodeposition.
摘要翻译：本发明涉及一种基本上不含铅化合物的阳离子电沉积涂料组合物，更具体地涉及一种涂覆合金化的热浸镀锌钢板的方法，该组合物和通过该方法获得的涂层制品具有优异的边缘部分和一般表面耐腐蚀性。本发明提供了一种用含有防锈颜料的无铅阳离子电沉积涂料组合物涂覆合金化的热镀锌钢板的方法，以形成耐腐蚀性优异的电沉积涂膜，以及通过电沉积获得的涂层制品。

10. 发明授权

US06617030B2 Cationic electro-coating bath composition 有权
公开(公告)号：US06617030B2
公开(公告)日：2003-09-09
申请号：US10094628
申请日：2002-03-12
申请人： Hiroyuki Morishita , Yasuyuki Hirata , Shigeo Murofushi , Akira Tominaga
发明人： Hiroyuki Morishita , Yasuyuki Hirata , Shigeo Murofushi , Akira Tominaga
IPC分类号： B32B1508
CPC分类号： C09D5/4492 , C09D5/4457 , Y10T428/31529
摘要： This invention provides, at a low cost, a low-pollution type cationic electro-coating bath composition which contains neither lead nor chromium, and which comprises cationic electrodeposition paint and, contained therein, a bismuth oxide paste, the amount of the bismuth oxide paste being within a range of 0.1 to 0.3% by weight as metal bismuth on the basis of total solid content of said cationic electro-coating bath composition, and the bismuth oxide paste being prepared by dispersing bismuth oxide (B) in an organic acid-neutralized aqueous dispersion of diethanol amine-added alicyclic epoxy resin (A).

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