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1. 发明授权

US09008194B2 Low-power, high-speed transceiver 有权
标题翻译：低功耗，高速收发器
公开(公告)号：US09008194B2
公开(公告)日：2015-04-14
申请号：US14239535
申请日：2011-12-14
申请人： Hong June Park , Jong Hoon Kim , Soo Min Lee
发明人： Hong June Park , Jong Hoon Kim , Soo Min Lee
IPC分类号： H04B3/00 , H04B1/38 , H04B1/40 , H04L25/02 , H04L25/03 , H04L25/08
CPC分类号： H04B1/40 , H04L25/0278 , H04L25/0298 , H04L25/03057 , H04L25/03949 , H04L25/085 , H04L2025/0377
摘要： The present invention relates to a low-power and high-speed transmission and reception apparatus which reduces consumption power of a sending-end circuit by increasing a value of a termination resistor included in a sending-end circuit and a receiving-end circuit so that the value is greater than a characteristic impedance value of a transmission line.
摘要翻译：本发明涉及通过增加发送端电路和接收端电路中包含的终端电阻的值来降低发送端电路的消耗功率的低功率，高速的发送和接收装置，该值大于传输线的特征阻抗值。

2. 发明申请

US20140211834A1 LOW-POWER, HIGH-SPEED TRANSCEIVER 有权
标题翻译：低功耗，高速收发器
公开(公告)号：US20140211834A1
公开(公告)日：2014-07-31
申请号：US14239535
申请日：2011-12-14
申请人： Hong June Park , Jong Hoon Kim , Soo Min Lee
发明人： Hong June Park , Jong Hoon Kim , Soo Min Lee
IPC分类号： H04B1/40 , H04L25/03
CPC分类号： H04B1/40 , H04L25/0278 , H04L25/0298 , H04L25/03057 , H04L25/03949 , H04L25/085 , H04L2025/0377
摘要： The present invention relates to a low-power and high-speed transmission and reception apparatus which reduces consumption power of a sending-end circuit by increasing a value of a termination resistor included in a sending-end circuit and a receiving-end circuit so that the value is greater than a characteristic impedance value of a transmission line.
摘要翻译：本发明涉及通过增加发送端电路和接收端电路中包含的终端电阻的值来降低发送端电路的消耗功率的低功率，高速的发送和接收装置，该值大于传输线的特征阻抗值。

3. 发明授权

US08401098B2 Digital differential signal transmitter for low supply voltage 失效
标题翻译：用于低电源电压的数字差分信号发射器
公开(公告)号：US08401098B2
公开(公告)日：2013-03-19
申请号：US12503048
申请日：2009-07-14
申请人： Jun Hyun Bae , Hong June Park
发明人： Jun Hyun Bae , Hong June Park
IPC分类号： H04K1/10 , H04B3/46 , H03K7/08
CPC分类号： H04L25/085 , H04J3/0685 , H04L7/0091 , H04L25/0272 , H04L25/0278
摘要： A digital differential signal transmitter circuit for a low supply voltage. A phase correction circuit for correcting digital signals transmitted through two signal paths in such a way as to have a phase relationship of differential signals and duty cycle correction circuits for correcting the digital signals in such a way as to maintain signal integrity in spite of changes in process, supply voltage and temperature are installed on the two signal paths so that the distortion of digital differential signals is compensated for. Power consumption at a final output section of the transmitter circuit is reduced. Impedances of the transmitter circuit and transmission lines are matched so that the transmitter circuit can operate insensitively with respect to operation circumstances.
摘要翻译：用于低电源电压的数字差分信号发射电路。一种相位校正电路，用于校正通过两个信号路径发送的数字信号，以便具有用于校正数字信号的差分信号和占空比校正电路的相位关系，以便尽可能保持信号完整性过程，电源电压和温度安装在两个信号路径上，以便数字差分信号的失真得到补偿。发射机电路最终输出部分的功耗降低。发射机电路和传输线路的阻抗匹配，使得发射机电路相对于操作环境不灵敏地操作。

4. 发明申请

US20120280721A1 SQUELCH DETECTION CIRCUIT 有权
标题翻译：检测电路
公开(公告)号：US20120280721A1
公开(公告)日：2012-11-08
申请号：US13519316
申请日：2010-12-15
申请人： Hong June Park , Seong Hwan Jeon
发明人： Hong June Park , Seong Hwan Jeon
IPC分类号： H03K5/22
CPC分类号： H03K5/2445 , H04L5/1423
摘要： A squelch detection circuit for high-speed serial communication includes: an input level shifter configured to receive signals inputted through signal lines and shift the received signals to a predetermined potential level; a comparator configured to receive signals outputted from the input level shifter, and compares the received signals to determine whether data signals are noise or signal components; and a reset signal generator configured to receive the signals outputted from the input level shifter, convert the received signals into a single signal, and then generate a reset signal for an elastic buffer. The squelch detection circuit may detect a squelch state and provide a reset value for an elastic buffer in a USB 2.0 interface, and may reduce power consumption as much as possible in a suspend mode.
摘要翻译：一种用于高速串行通信的静噪检测电路包括：输入电平移位器，被配置为接收通过信号线输入的信号并将接收信号移位到预定电位电平; 比较器，被配置为接收从所述输入电平移位器输出的信号，并且比较所接收的信号以确定数据信号是噪声还是信号分量; 以及复位信号发生器，被配置为接收从输入电平移位器输出的信号，将接收的信号转换为单个信号，然后生成用于弹性缓冲器的复位信号。静噪检测电路可以检测静噪状态，并为USB 2.0接口中的弹性缓冲器提供复位值，并且可以在挂起模式下尽可能地减少功耗。

5. 发明授权

US08188768B2 Low power consumption low kick-back noise comparator circuit for analog-to-digital converter 有权
标题翻译：用于模数转换器的低功耗低反向噪声比较器电路
公开(公告)号：US08188768B2
公开(公告)日：2012-05-29
申请号：US12773537
申请日：2010-05-04
申请人： Jun Hyun Bae , Hong June Park
发明人： Jun Hyun Bae , Hong June Park
IPC分类号： H03K5/22
CPC分类号： H03K3/356139
摘要： The present invention is directed for a comparator circuit used in an analog-to-digital converter, and more particularly, for a low power consumption low kick-back noise comparator circuit for an analog-to-digital converter, which can significantly reduce kick-back noise generated in a signal input stage due to a signal regeneration method employed in a signal comparing operation and can efficiently reduce power consumption.
摘要翻译：本发明涉及一种在模数转换器中使用的比较器电路，更具体地说，涉及用于模数转换器的低功耗低反冲噪声比较器电路，由于在信号比较操作中采用的信号再生方法在信号输入级中产生的背噪声，并且可以有效地降低功耗。

6. 发明申请

US20100283511A1 LOW POWER CONSUMPTION LOW KICK-BACK NOISE COMPARATOR CIRCUIT FOR ANALOG-TO-DIGITAL CONVERTER 有权
标题翻译：低功耗低ICK K K NO E E TER TER TER TER TER TER TER TER TER TER TER TER TER TER TER TER TER TER
公开(公告)号：US20100283511A1
公开(公告)日：2010-11-11
申请号：US12773537
申请日：2010-05-04
申请人： Jun Hyun BAE , Hong June PARK
发明人： Jun Hyun BAE , Hong June PARK
IPC分类号： H03K5/153
CPC分类号： H03K3/356139
摘要： The present invention is directed for a comparator circuit used in an analog-to-digital converter, and more particularly, for a low power consumption low kick-back noise comparator circuit for an analog-to-digital converter, which can significantly reduce kick-back noise generated in a signal input stage due to a signal regeneration method employed in a signal comparing operation and can efficiently reduce power consumption.
摘要翻译：本发明涉及一种在模数转换器中使用的比较器电路，更具体地说，涉及用于模数转换器的低功耗低反冲噪声比较器电路，由于在信号比较操作中采用的信号再生方法在信号输入级中产生的背噪声，并且可以有效地降低功耗。

7. 发明授权

US07659791B2 Double comb guard trace pattern for reducing the far-end cross-talk and printed circuit board including the pattern 失效
标题翻译：双梳状保护迹线图案，用于减少远端串扰和印刷电路板，包括图案
公开(公告)号：US07659791B2
公开(公告)日：2010-02-09
申请号：US11850142
申请日：2007-09-05
申请人： Hong June Park , Kyoung Ho Lee , Hae Kang Jung
发明人： Hong June Park , Kyoung Ho Lee , Hae Kang Jung
IPC分类号： H01P3/08
CPC分类号： H05K1/0219 , H05K2201/09236 , H05K2201/09736 , H05K2201/09781
摘要： Provided is a guard trace pattern reducing far-end crosstalk and a printed circuit board having the guard trace pattern. The guard trace pattern includes a first guard trace pattern parallel with two signal lines and a plurality of second guard trace patterns perpendicular to the first guard trace pattern to increase mutual capacitance between the two signal lines and the guard trace pattern and increase mutual capacitance between the two signal lines. The printed circuit board includes the aforementioned guard trace pattern disposed between micro strip transmission lines. A characteristic impedance of the guard trace pattern is different from a characteristic impedance of the micro strip transmission lines, and resistances having the same value as a resistance component value of the characteristic impedance of the guard trace pattern are provided to both ends of the guard trace pattern.
摘要翻译：提供了减少远端串扰的保护迹线图案和具有保护迹线图案的印刷电路板。保护迹线图形包括与两条信号线平行的第一保护迹线图形和垂直于第一保护迹线图形的多个第二保护迹线图案，以增加两个信号线和保护迹线图案之间的互电容，并增加两个信号线之间的互电容两条信号线。印刷电路板包括设置在微带传输线之间的上述保护迹线图案。保护迹线图案的特性阻抗与微带传输线的特性阻抗不同，并且具有与保护迹线图案的特性阻抗的电阻分量值相同值的电阻提供给保护迹线的两端模式。

8. 发明申请

US20080252340A1 DELAY LOCKED LOOP (DLL) CIRCUITS HAVING AN EXPANDED OPERATION RANGE AND METHODS OF OPERATING THE SAME 审中-公开
标题翻译：具有扩展操作范围的延迟锁定环路（DLL）电路及其操作方法
公开(公告)号：US20080252340A1
公开(公告)日：2008-10-16
申请号：US12099323
申请日：2008-04-08
申请人： Hwan-seok Yeo , Jin-ho Seo , Hong-june Park , Jun-hyun Bae
发明人： Hwan-seok Yeo , Jin-ho Seo , Hong-june Park , Jun-hyun Bae
IPC分类号： H03L7/06
CPC分类号： H03L7/0814 , H03L7/091
摘要： Delay locked loop (DLL) circuits have a phase detector circuit that can detect a phase difference between an input clock signal and an output clock signal over a time period of 0T-2T. The delay applied to generate the output signal is adjusted based on the detected phase difference. A middle clock signal can be generated that has a phase that is between the input clock signal and the output clock signal. The phase detector circuit may be configured to detect the phase difference between the input clock signal and the output clock signal over the time period 0T-2T responsive to the middle clock signal.
摘要翻译：延迟锁定环（DLL）电路具有相位检测器电路，可在0T-2T的时间段内检测输入时钟信号和输出时钟信号之间的相位差。基于检测到的相位差来调整用于产生输出信号的延迟。可以产生具有在输入时钟信号和输出时钟信号之间的相位的中间时钟信号。相位检测器电路可以被配置为响应于中间时钟信号在时间段0T-2T上检测输入时钟信号和输出时钟信号之间的相位差。

9. 发明授权

US07339409B2 Slew rate controlled output driver for use in semiconductor device 失效
标题翻译：用于半导体器件的压摆率控制输出驱动器
公开(公告)号：US07339409B2
公开(公告)日：2008-03-04
申请号：US11020771
申请日：2004-12-21
申请人： Seok-Woo Choi , Hong-June Park
发明人： Seok-Woo Choi , Hong-June Park
IPC分类号： H03K5/12
CPC分类号： G11C7/02 , G11C7/04 , G11C7/1057 , G11C7/1084 , H03K17/164 , H03K19/01721 , H03K19/018521
摘要： An output driver for use in a semiconductor is capable of maintaining its slew rate constantly regardless of PVT(Process/Voltage/Temperature) variation. The output driver includes a pre-driving unit for pre-driving a data signal; a main driving unit for driving an output pad in response to the output signal of the pre-driving unit; and a slew rate modeling unit for generating a pre-driver bias signal to constantly maintain effective resistances of a pull-up path and a pull-down path of the pre-driving unit by modeling the pre-driving unit.
摘要翻译：用于半导体的输出驱动器能够恒定地保持其转换速率，而不管PVT（工艺/电压/温度）变化如何。输出驱动器包括用于预驱动数据信号的预驱动单元; 主驱动单元，用于响应于所述预驱动单元的输出信号来驱动输出焊盘; 以及压摆率建模单元，用于通过对所述预驱动单元进行建模来产生预驱动器偏置信号，以恒定地维持所述预驱动单元的上拉路径和下拉路径的有效电阻。

10. 发明申请

US20070170967A1 MULTI-PHASE CLOCK GENERATOR 失效
标题翻译：多相时钟发生器
公开(公告)号：US20070170967A1
公开(公告)日：2007-07-26
申请号：US11625541
申请日：2007-01-22
申请人： Seung Jun BAE , Hong June PARK
发明人： Seung Jun BAE , Hong June PARK
IPC分类号： H03K5/13
CPC分类号： H03K5/15013 , H03K5/1565 , H03K2005/00286 , H03L7/0814
摘要： Provided is a multi-phase clock generator which is not influenced by a mismatch and of which a maximum frequency is not limited. The multi-phase clock generator includes a first delay line, a second delay line, a phase detector, and an up/down counter. The first delay line generates a first clock signal by delaying an input clock for a first delay time. The second delay line generates a second clock signal by delaying the input clock for a second delay time in response to a control signal. The phase detector detects a phase difference between the first and second clock signals. The up/down counter generates the control signal in response to an output of the phase detector.
摘要翻译：提供了不受不匹配影响并且不限制最大频率的多相时钟发生器。多相时钟发生器包括第一延迟线，第二延迟线，相位检测器和上/下计数器。第一延迟线通过将输入时钟延迟第一延迟时间来产生第一时钟信号。第二延迟线响应于控制信号，通过将输入时钟延迟第二延迟时间来产生第二时钟信号。相位检测器检测第一和第二时钟信号之间的相位差。上/下计数器响应于相位检测器的输出而产生控制信号。

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