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1. 发明申请

US20100284489A1 DIGITAL DIFFERENTIAL SIGNAL TRANSMITTER FOR LOW SUPPLY VOLTAGE 失效
标题翻译：用于低电压的数字差分信号发生器
公开(公告)号：US20100284489A1
公开(公告)日：2010-11-11
申请号：US12503048
申请日：2009-07-14
申请人： Jun Hyun BAE , Hong June PARK
发明人： Jun Hyun BAE , Hong June PARK
IPC分类号： H04L25/03
CPC分类号： H04L25/085 , H04J3/0685 , H04L7/0091 , H04L25/0272 , H04L25/0278
摘要： A digital differential signal transmitter circuit for a low supply voltage. A phase correction circuit for correcting digital signals transmitted through two signal paths in such a way as to have a phase relationship of differential signals and duty cycle correction circuits for correcting the digital signals in such a way as to maintain signal integrity in spite of changes in process, supply voltage and temperature are installed on the two signal paths so that the distortion of digital differential signals is compensated for. Power consumption at a final output section of the transmitter circuit is reduced. Impedances of the transmitter circuit and transmission lines are matched so that the transmitter circuit can operate insensitively with respect to operation circumstances.
摘要翻译：用于低电源电压的数字差分信号发射电路。一种相位校正电路，用于校正通过两个信号路径发送的数字信号，以便具有用于校正数字信号的差分信号和占空比校正电路的相位关系，以便尽可能保持信号完整性过程，电源电压和温度安装在两个信号路径上，以便数字差分信号的失真得到补偿。发射机电路最终输出部分的功耗降低。发射机电路和传输线路的阻抗匹配，使得发射机电路相对于操作环境不灵敏地操作。

2. 发明授权

US08401098B2 Digital differential signal transmitter for low supply voltage 失效
标题翻译：用于低电源电压的数字差分信号发射器
公开(公告)号：US08401098B2
公开(公告)日：2013-03-19
申请号：US12503048
申请日：2009-07-14
申请人： Jun Hyun Bae , Hong June Park
发明人： Jun Hyun Bae , Hong June Park
IPC分类号： H04K1/10 , H04B3/46 , H03K7/08
CPC分类号： H04L25/085 , H04J3/0685 , H04L7/0091 , H04L25/0272 , H04L25/0278
摘要： A digital differential signal transmitter circuit for a low supply voltage. A phase correction circuit for correcting digital signals transmitted through two signal paths in such a way as to have a phase relationship of differential signals and duty cycle correction circuits for correcting the digital signals in such a way as to maintain signal integrity in spite of changes in process, supply voltage and temperature are installed on the two signal paths so that the distortion of digital differential signals is compensated for. Power consumption at a final output section of the transmitter circuit is reduced. Impedances of the transmitter circuit and transmission lines are matched so that the transmitter circuit can operate insensitively with respect to operation circumstances.
摘要翻译：用于低电源电压的数字差分信号发射电路。一种相位校正电路，用于校正通过两个信号路径发送的数字信号，以便具有用于校正数字信号的差分信号和占空比校正电路的相位关系，以便尽可能保持信号完整性过程，电源电压和温度安装在两个信号路径上，以便数字差分信号的失真得到补偿。发射机电路最终输出部分的功耗降低。发射机电路和传输线路的阻抗匹配，使得发射机电路相对于操作环境不灵敏地操作。

3. 发明授权

US08188768B2 Low power consumption low kick-back noise comparator circuit for analog-to-digital converter 有权
标题翻译：用于模数转换器的低功耗低反向噪声比较器电路
公开(公告)号：US08188768B2
公开(公告)日：2012-05-29
申请号：US12773537
申请日：2010-05-04
申请人： Jun Hyun Bae , Hong June Park
发明人： Jun Hyun Bae , Hong June Park
IPC分类号： H03K5/22
CPC分类号： H03K3/356139
摘要： The present invention is directed for a comparator circuit used in an analog-to-digital converter, and more particularly, for a low power consumption low kick-back noise comparator circuit for an analog-to-digital converter, which can significantly reduce kick-back noise generated in a signal input stage due to a signal regeneration method employed in a signal comparing operation and can efficiently reduce power consumption.
摘要翻译：本发明涉及一种在模数转换器中使用的比较器电路，更具体地说，涉及用于模数转换器的低功耗低反冲噪声比较器电路，由于在信号比较操作中采用的信号再生方法在信号输入级中产生的背噪声，并且可以有效地降低功耗。

4. 发明申请

US20100283511A1 LOW POWER CONSUMPTION LOW KICK-BACK NOISE COMPARATOR CIRCUIT FOR ANALOG-TO-DIGITAL CONVERTER 有权
标题翻译：低功耗低ICK K K NO E E TER TER TER TER TER TER TER TER TER TER TER TER TER TER TER TER TER TER
公开(公告)号：US20100283511A1
公开(公告)日：2010-11-11
申请号：US12773537
申请日：2010-05-04
申请人： Jun Hyun BAE , Hong June PARK
发明人： Jun Hyun BAE , Hong June PARK
IPC分类号： H03K5/153
CPC分类号： H03K3/356139
摘要： The present invention is directed for a comparator circuit used in an analog-to-digital converter, and more particularly, for a low power consumption low kick-back noise comparator circuit for an analog-to-digital converter, which can significantly reduce kick-back noise generated in a signal input stage due to a signal regeneration method employed in a signal comparing operation and can efficiently reduce power consumption.
摘要翻译：本发明涉及一种在模数转换器中使用的比较器电路，更具体地说，涉及用于模数转换器的低功耗低反冲噪声比较器电路，由于在信号比较操作中采用的信号再生方法在信号输入级中产生的背噪声，并且可以有效地降低功耗。

5. 发明申请

US20080252340A1 DELAY LOCKED LOOP (DLL) CIRCUITS HAVING AN EXPANDED OPERATION RANGE AND METHODS OF OPERATING THE SAME 审中-公开
标题翻译：具有扩展操作范围的延迟锁定环路（DLL）电路及其操作方法
公开(公告)号：US20080252340A1
公开(公告)日：2008-10-16
申请号：US12099323
申请日：2008-04-08
申请人： Hwan-seok Yeo , Jin-ho Seo , Hong-june Park , Jun-hyun Bae
发明人： Hwan-seok Yeo , Jin-ho Seo , Hong-june Park , Jun-hyun Bae
IPC分类号： H03L7/06
CPC分类号： H03L7/0814 , H03L7/091
摘要： Delay locked loop (DLL) circuits have a phase detector circuit that can detect a phase difference between an input clock signal and an output clock signal over a time period of 0T-2T. The delay applied to generate the output signal is adjusted based on the detected phase difference. A middle clock signal can be generated that has a phase that is between the input clock signal and the output clock signal. The phase detector circuit may be configured to detect the phase difference between the input clock signal and the output clock signal over the time period 0T-2T responsive to the middle clock signal.
摘要翻译：延迟锁定环（DLL）电路具有相位检测器电路，可在0T-2T的时间段内检测输入时钟信号和输出时钟信号之间的相位差。基于检测到的相位差来调整用于产生输出信号的延迟。可以产生具有在输入时钟信号和输出时钟信号之间的相位的中间时钟信号。相位检测器电路可以被配置为响应于中间时钟信号在时间段0T-2T上检测输入时钟信号和输出时钟信号之间的相位差。

6. 发明申请

US20080272815A1 DUTY CYCLE CORRECTION CIRCUITS INCLUDING A TRANSITION GENERATOR CIRCUIT FOR GENERATING TRANSITIONS IN A DUTY CYCLE CORRECTED SIGNAL RESPONSIVE TO AN INPUT SIGNAL AND A DELAYED VERSION OF THE INPUT SIGNAL AND METHODS OF OPERATING THE SAME 有权
标题翻译：占空比校正电路，包括用于在对输入信号进行的占空比校正信号中产生转换和输入信号的延迟版本及其操作方法产生转换的转换发生器电路
公开(公告)号：US20080272815A1
公开(公告)日：2008-11-06
申请号：US12112225
申请日：2008-04-30
申请人： Hwan-Seok Yeo , Jin-Ho Seo , Hong-June Park , Jun-Hyun Bae
发明人： Hwan-Seok Yeo , Jin-Ho Seo , Hong-June Park , Jun-Hyun Bae
IPC分类号： H03K3/017
CPC分类号： H03K5/1565
摘要： A duty cycle correction circuit is operated by maintaining a state of a duty cycle corrected signal, generating a first transition in the state of the duty cycle corrected signal responsive to an input signal, and generating a second transition in the state of the duty cycle corrected signal responsive to a delayed version of the input signal.
摘要翻译：通过保持占空比校正信号的状态来操作占空比校正电路，响应于输入信号产生占空比校正信号的状态的第一转变，并且在占空比校正状态下产生第二转变响应于延迟版本的输入信号的信号。

7. 发明申请

US20070008201A1 Bubble error rejecter in data converter 有权
标题翻译：数据转换器中的气泡错误拒绝
公开(公告)号：US20070008201A1
公开(公告)日：2007-01-11
申请号：US11451921
申请日：2006-06-13
申请人： Ho-Young Lee , Yong-Sang You , Hong-June Park , Jun-Hyun Bae , Young-Chan Jang
发明人： Ho-Young Lee , Yong-Sang You , Hong-June Park , Jun-Hyun Bae , Young-Chan Jang
IPC分类号： H03M1/10
CPC分类号： H03M1/0809 , H03M1/365
摘要： A bubble error rejecter includes a cascade of front and rear voting sections for correcting bubble errors spanning multiple bits from interpolation. The front voting section generates first correction codes from first thermometer codes determined from preamplified signals. The rear voting section generates second correction codes from the first correction codes and second thermometer codes determined from interpolation of the preamplified signals.
摘要翻译：泡沫误差拒绝器包括前级和后端投票部分的级联，用于校正跨内插多个位的气泡误差。前投票部分根据从预放大信号确定的第一温度计代码产生第一校正码。后方投票部从根据前置放大信号的内插确定的第一校正码和第二温度计代码生成第二校正码。

8. 发明授权

US07839193B2 Duty cycle correction circuits including a transition generator circuit for generating transitions in a duty cycle corrected signal responsive to an input signal and a delayed version of the input signal and methods of operating the same 有权
标题翻译：包括用于响应于输入信号和延迟版本的输入信号产生占空比校正信号中的转变的转换发生器电路的占空比校正电路及其操作方法
公开(公告)号：US07839193B2
公开(公告)日：2010-11-23
申请号：US12112225
申请日：2008-04-30
申请人： Hwan-seok Yeo , Jin-ho Seo , Hong-june Park , Jun-hyun Bae
发明人： Hwan-seok Yeo , Jin-ho Seo , Hong-june Park , Jun-hyun Bae
IPC分类号： H03K3/017
CPC分类号： H03K5/1565
摘要： A duty cycle correction circuit is operated by maintaining a state of a duty cycle corrected signal, generating a first transition in the state of the duty cycle corrected signal responsive to an input signal, and generating a second transition in the state of the duty cycle corrected signal responsive to a delayed version of the input signal.
摘要翻译：通过保持占空比校正信号的状态来操作占空比校正电路，响应于输入信号产生占空比校正信号的状态的第一转变，并且在占空比校正状态下产生第二转变响应于延迟版本的输入信号的信号。

9. 发明授权

US07327292B2 Bubble error rejecter in data converter 有权
标题翻译：数据转换器中的气泡错误拒绝
公开(公告)号：US07327292B2
公开(公告)日：2008-02-05
申请号：US11451921
申请日：2006-06-13
申请人： Ho-Young Lee , Yong-Sang You , Hong-June Park , Jun-Hyun Bae , Young-Chan Jang
发明人： Ho-Young Lee , Yong-Sang You , Hong-June Park , Jun-Hyun Bae , Young-Chan Jang
IPC分类号： H03M13/00
CPC分类号： H03M1/0809 , H03M1/365
摘要： A bubble error rejecter includes a cascade of front and rear voting sections for correcting bubble errors spanning multiple bits from interpolation. The front voting section generates first correction codes from first thermometer codes determined from preamplified signals. The rear voting section generates second correction codes from the first correction codes and second thermometer codes determined from interpolation of the preamplified signals.
摘要翻译：泡沫误差拒绝器包括前级和后端投票部分的级联，用于校正跨内插多个位的气泡误差。前投票部分根据从预放大信号确定的第一温度计代码产生第一校正码。后方投票部从根据前置放大信号的内插确定的第一校正码和第二温度计代码生成第二校正码。

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