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1. 外观设计

USD893625S1 Ink refill cartridge for writing instrument 有权
公开(公告)号：USD893625S1
公开(公告)日：2020-08-18
申请号：US29679284
申请日：2019-02-04
申请人： Howard H. Smith
设计人： Howard H. Smith
摘要： FIG. 1 is a top, left, rear perspective view of an ink refill cartridge for writing instrument showing my new design;
FIG. 2 is a left side elevational view thereof;
FIG. 3 is a right side elevational view thereof;
FIG. 4 is a top plan view thereof;
FIG. 5 is a bottom plan view thereof;
FIG. 6 is a rear elevational view thereof;
FIG. 7 is a front elevational view thereof; and,
FIG. 8 is a bottom, left, rear perspective view of thereof.

2. 发明授权

US07346877B2 Decoupling capacitance analysis method 有权
标题翻译：去耦电容分析方法
公开(公告)号：US07346877B2
公开(公告)日：2008-03-18
申请号：US11408217
申请日：2006-04-20
申请人： Christopher J. Berry , Howard H. Smith , Richard P. Underwood , Alan P. Wagstaff
发明人： Christopher J. Berry , Howard H. Smith , Richard P. Underwood , Alan P. Wagstaff
IPC分类号： G06F17/50
CPC分类号： G06F17/5036
摘要： This method for decoupling capacitance analysis improves upon existing techniques to attempt to give a more accurate representation of the power supply fluctuations on a chip while keeping runtime comparable. This method employs the following techniques; a) a method for descending through hierarchy and dividing the design into a variable sized grid; b) an algorithm to determine which grid locations of a design don't have enough decoupling capacitors for all of the devices in that grid location; c) an algorithm to determine which grid locations are subject to harmful neighboring effects; and d) a method to display the results of the calculations in a graphical manor to allow easy identification of problem areas.
摘要翻译：用于去耦电容分析的这种方法改进了现有技术，以试图给出对芯片上的电源波动的更准确的表示，同时保持运行时可比性。该方法采用以下技术; a）通过层级降级并将设计划分为可变尺寸网格的方法; b）确定设计的哪些网格位置对于该网格位置中的所有设备没有足够的去耦电容器的算法; c）确定哪些网格位置受到有害的相邻影响的算法; 以及d）以图形方式显示计算结果的方法，以便容易地识别问题区域。

3. 发明授权

US07319946B2 Method for on-chip signal integrity and noise verification using frequency dependent RLC extraction and modeling techniques 有权
标题翻译：使用频率相关RLC提取和建模技术的片上信号完整性和噪声验证方法
公开(公告)号：US07319946B2
公开(公告)日：2008-01-15
申请号：US10274861
申请日：2002-10-21
申请人： Michael A. Bowen , Alina Deutsch , Gerard V. Kopcsay , Byron L. Krauter , Barry J. Rubin , Howard H. Smith , David J. Widiger
发明人： Michael A. Bowen , Alina Deutsch , Gerard V. Kopcsay , Byron L. Krauter , Barry J. Rubin , Howard H. Smith , David J. Widiger
IPC分类号： G06F17/50 , G06G7/62 , G06G7/48
CPC分类号： G06F17/5036
摘要： New Frequency dependent RLC extraction and modeling for on chip integrity and noise verification employs: A) 2D scan line algorithm for the collection of adjacent signal and power conductor coordinates; B) In core pair-wise frequency Dependent RL extraction; C) In core equivalent circuit synthesis; D) caching and partitioning RL extraction techniques for run time efficiency; and E) Techniques for synthesizing stable circuits to represent frequency dependent RL circuits for non-mono tonic R12.
摘要翻译：新的频率相关RLC提取和片上完整性和噪声验证的建模采用：A）用于收集相邻信号和电源导体坐标的2D扫描线算法; B）在核心配对频率从属RL提取中; C）在核心等效电路合成中; D）缓存和分区RL提取技术，用于运行时效率; 和E）用于合成稳定电路以表示用于非单音增益R 12的频率相关RL电路的技术。

4. 发明授权

US06374394B1 Method to identify unit pins that are not optimally positioned in a hierarchically designed VLSI chip 失效
标题翻译：识别不是最佳定位在分层设计的VLSI芯片中的单元引脚的方法
公开(公告)号：US06374394B1
公开(公告)日：2002-04-16
申请号：US09422290
申请日：1999-10-21
申请人： Peter J. Camporese , Allan H. Dansky , Howard H. Smith
发明人： Peter J. Camporese , Allan H. Dansky , Howard H. Smith
IPC分类号： G06F1750
CPC分类号： G06F17/5072
摘要： A method for identifying unit pin positions initially assigned in a hierarchical VLSI design that, if implemented, would increase the net length of the net of which the unit pins are a part. To identify unit pins, where the unit pin position assigned by the unit designer turns out to be a poor choice of position when the unit is integrated into the top level design, a “flat” file is created of the completed VLSI design with the units positioned on the chip, including their pin placements as assigned by the unit designers. The flat file includes not only top level unit data and unit-to-unit net data, but also macro data and macro net data integral to each unit design. The flat design data file is used to generate two pin logs; one pin log includes the incremental lengths of each net including the incremental lengths associated with the unit pins (if any) assigned by the designers of the units. The other pin log is the same, except it does not include the unit pins and the incremental net length associated with the unit pins. A commercially available program, for example, a Minimum Spanning Tree (MST) program or a Steiner Minimal Tree program is run against every net; once against the nets in the pin log list that includes the pins assigned by the designers of the units, and once against the nets in the pin log list that does not include assigned unit pins. The output of interest of the MST (or similar program) run against the net files with and without pin assignments is a text file containing the net names, number of pins per net with and without unit pins and the difference between the net lengths with and without unit pin assignments. If the difference exceeds a threshold value, that net is identified so that the unit pins can be reassigned by the unit designer or designers.
摘要翻译：一种用于识别最初在分层VLSI设计中分配的单元销位置的方法，如果被实现，将增加单元引脚作为一部分的网的净长度。为了识别单元引脚，当单元集成到顶级设计中时，由单元设计人员分配的单元销位置变为不良位置的选择，将创建具有单元的完成的VLSI设计的“平面”文件位于芯片上，包括由单元设计师分配的针位置。平面文件不仅包括顶层单元数据和单元到单元净数据，而且还包括每个单元设计的宏数据和宏网数据。平面设计数据文件用于生成两个引脚日志; 一个针脚日志包括每个网络的增量长度，包括与单元设计者分配的单位引脚（如果有的话）相关联的增量长度。另一个引脚日志是相同的，除了它不包括单位引脚和与单元引脚相关联的增量净长度。针对每个网络运行市售程序，例如最小生成树（MST）或Steiner最小树程序; 一次针对引脚日志列表中的网络，其中包括由单元的设计者分配的引脚，并且一次针对不包括分配的单元引脚的引脚日志列表中的网络。 MST（或类似程序）对带有和不带引脚分配的网络文件的兴趣的输出是一个文本文件，其中包含网络名称，每个带有和不带有单元引脚的网络引脚数，以及与/ 没有单位引脚分配。如果差异超过阈值，则识别该网络，使得单元引脚可由单元设计者或设计者重新分配。

5. 发明授权

US07971171B2 Method and system for electromigration analysis on signal wiring 有权
标题翻译：信号线路电迁移分析方法与系统
公开(公告)号：US07971171B2
公开(公告)日：2011-06-28
申请号：US12123769
申请日：2008-05-20
申请人： Joachim Keinert , Howard H. Smith , Patrick M. Williams
发明人： Joachim Keinert , Howard H. Smith , Patrick M. Williams
IPC分类号： G06F17/50
CPC分类号： G06F17/5036
摘要： The invention relates to an electromigration analysis method and a system for analyzing one or more nets in a digital integrated circuit design that are at risk of electromigration. The method comprises the steps of providing at least one interconnect between a driver cell and at least one load cell; applying same extracted netlist data for noise and/or timing analysis and for electromigration analysis; modeling the driver cell by a train of trapezoidal voltage pulses transmitted from the driver cell to the one or more load cells through the at least one interconnect; extracting at least a slew rate of a driver voltage signal and/or timing information from a noise and/or timing analysis for the one or more nets; and comparing a locally measured current density in the at least one interconnect to an effective local maximum current density limit of the at least one interconnect.
摘要翻译：本发明涉及电迁移分析方法和用于分析处于电迁移风险的数字集成电路设计中的一个或多个网络的系统。该方法包括以下步骤：在驱动器单元和至少一个称重传感器之间提供至少一个互连; 应用相同的提取网表数据进行噪声和/或定时分析和电迁移分析; 通过所述至少一个互连通过从所述驱动器单元传输到所述一个或多个称重传感器的一串梯形电压脉冲对所述驱动器单元进行建模; 从所述一个或多个网络的噪声和/或定时分析中提取至少一个驱动器电压信号和/或定时信息的转换速率; 以及将所述至少一个互连中的局部测量的电流密度与所述至少一个互连的有效局部最大电流密度极限进行比较。

6. 发明授权

US07844435B2 Integrated circuit chip having on-chip signal integrity and noise verification using frequency dependent RLC extraction and modeling techniques 有权
标题翻译：具有片上信号完整性和使用频率相关RLC提取和建模技术的噪声验证的集成电路芯片
公开(公告)号：US07844435B2
公开(公告)日：2010-11-30
申请号：US11942270
申请日：2007-11-19
申请人： Michael A. Bowen , Alina Deutsch , Gerard V. Kopcsay , Byron L. Krauter , Barry J. Rubin , Howard H. Smith , David J. Widiger
发明人： Michael A. Bowen , Alina Deutsch , Gerard V. Kopcsay , Byron L. Krauter , Barry J. Rubin , Howard H. Smith , David J. Widiger
IPC分类号： G06F17/50 , G06G7/62 , G06G7/48
CPC分类号： G06F17/5036
摘要： An integrated circuit chip has new Frequency dependent RLC extraction and modeling providing on chip integrity and noise verification and the extraction and modeling employs: A) 2D scan line algorithm for the collection of adjacent signal and power conductor coordinates; B) In core pair-wise frequency Dependent RL extraction; C) In core equivalent circuit synthesis; D) caching and partitioning RL extraction techniques for run time efficiency; and E) Techniques for synthesizing stable circuits to represent frequency dependent RL circuits for non-mono tonic R12.
摘要翻译：集成电路芯片具有新的频率相关RLC提取和建模，提供片上完整性和噪声验证，提取和建模采用：A）用于收集相邻信号和电源导线坐标的2D扫描线算法; B）在核心配对频率从属RL提取中; C）在核心等效电路合成中; D）缓存和分区RL提取技术，用于运行时效率; 和E）用于合成稳定电路以表示用于非单音补音R12的频率相关RL电路的技术。

7. 发明申请

US20090013290A1 Method and System for Electromigration Analysis on Signal Wiring 有权
标题翻译：信号接线电迁移分析方法与系统
公开(公告)号：US20090013290A1
公开(公告)日：2009-01-08
申请号：US12123769
申请日：2008-05-20
申请人： Joachim Keinert , Howard H. Smith , Patrick M. Williams
发明人： Joachim Keinert , Howard H. Smith , Patrick M. Williams
IPC分类号： G06F17/50
CPC分类号： G06F17/5036
摘要： The invention relates to an electromigration analysis method and a system for analyzing one or more nets in a digital integrated circuit design that are at risk of electromigration. The method comprises the steps of providing at least one interconnect between a driver cell and at least one load cell; applying same extracted netlist data for noise and/or timing analysis and for electromigration analysis; modeling the driver cell by a train of trapezoidal voltage pulses transmitted from the driver cell to the one or more load cells through the at least one interconnect; extracting at least a slew rate of a driver voltage signal (UD) and/or timing information from a noise and/or timing analysis for the one or more nets; and comparing a locally measured current density (if,rms,R32) in the at least one interconnect to an effective local maximum current density limit (irms,max) of the at least one interconnect.
摘要翻译：本发明涉及电迁移分析方法和用于分析处于电迁移风险的数字集成电路设计中的一个或多个网络的系统。该方法包括以下步骤：在驱动器单元和至少一个称重传感器之间提供至少一个互连; 应用相同的提取网表数据进行噪声和/或定时分析和电迁移分析; 通过所述至少一个互连通过从所述驱动器单元传输到所述一个或多个称重传感器的一串梯形电压脉冲对所述驱动器单元进行建模; 从所述一个或多个网络的噪声和/或定时分析中提取至少一个驱动器电压信号（UD）的转换速率和/或定时信息; 以及将所述至少一个互连中的局部测量的电流密度（if，rms，R32）与所述至少一个互连的有效局部最大电流密度极限（irms，max）进行比较。

8. 发明授权

US06618844B2 Method for evaluating decoupling capacitor placement for VLSI chips 失效
公开(公告)号：US06618844B2
公开(公告)日：2003-09-09
申请号：US09896270
申请日：2001-06-29
申请人： Allan H. Dansky , Wiren D. Becker , Howard H. Smith , Peter J. Camporese , Kwok Fai Eng , Dale E. Hoffman , Bhupindra Singh
发明人： Allan H. Dansky , Wiren D. Becker , Howard H. Smith , Peter J. Camporese , Kwok Fai Eng , Dale E. Hoffman , Bhupindra Singh
IPC分类号： G06F1750
CPC分类号： G06F17/5072 , G06F17/5036
摘要： A method of evaluating decoupling capacitor placement for Very Large Scale Integrated Chips (VLSI) is disclosed. Included in the method is an analysis of the usage for each decoupling capacitor, the distance from the devices, and the locations of the devices and decoupling capacitors. Also addressed are the orientations and size of the components.

9. 发明授权

US3991466A Dual purpose spoon and oyster knife 失效
标题翻译：双用途勺子和牡蛎刀
公开(公告)号：US3991466A
公开(公告)日：1976-11-16
申请号：US656655
申请日：1976-02-09
申请人： Howard H. Smith
发明人： Howard H. Smith
IPC分类号： A47G21/06 , B26B11/00 , A22C29/00
CPC分类号： A47G21/065
摘要： A utensil for opening an oyster which also serves to cut the oyster umbilical cord and lift the oyster out of its shell. The utensil is fitted with a handle to which the blade is fixed, with the blade being formed of metal, preferably stainless steel. The blade is shaped with a curved spoon section serrated at opposed sides of the spoon for the severing of the oyster umbilical cord, with a knife section projecting along the axis of the blade, from the spoon.
摘要翻译：用于打开牡蛎的器具，其还用于切割牡蛎脐带并将牡蛎从其壳中提起。该器具装有刀片固定的手柄，刀片由金属制成，优选为不锈钢。叶片成形为具有锯齿形的勺子部分，其在勺子的相对侧锯齿，以便切割牡蛎脐带，刀片部分沿着刀片的轴线从勺子突出。

10. 发明授权

US07269806B2 Decoupling capacitance analysis method 失效
标题翻译：去耦电容分析方法
公开(公告)号：US07269806B2
公开(公告)日：2007-09-11
申请号：US11408228
申请日：2006-04-20
申请人： Christopher J. Berry , Howard H. Smith , Richard P. Underwood , Alan P. Wagstaff
发明人： Christopher J. Berry , Howard H. Smith , Richard P. Underwood , Alan P. Wagstaff
IPC分类号： G06F17/50
CPC分类号： G06F17/5036
摘要： This method for decoupling capacitance analysis improves upon existing techniques to attempt to give a more accurate representation of the power supply fluctuations on a chip while keeping runtime comparable. This method employs the following techniques; a) a method for descending through hierarchy and dividing the design into a variable sized grid; b) an algorithm to determine which grid locations of a design don't have enough decoupling capacitors for all of the devices in that grid location; c) an algorithm to determine which grid locations are subject to harmful neighboring effects; and d) a method to display the results of the calculations in a graphical manor to allow easy identification of problem areas.
摘要翻译：用于去耦电容分析的这种方法改进了现有技术，以试图给出对芯片上的电源波动的更准确的表示，同时保持运行时可比性。该方法采用以下技术; a）通过层级降级并将设计划分为可变尺寸网格的方法; b）确定设计的哪些网格位置对于该网格位置中的所有设备没有足够的去耦电容器的算法; c）确定哪些网格位置受到有害的相邻影响的算法; 以及d）以图形方式显示计算结果的方法，以便容易地识别问题区域。

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