专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明授权

US07678692B2 Fabrication method for a damascene bit line contact plug 有权
标题翻译：镶嵌位线接触插头的制造方法
公开(公告)号：US07678692B2
公开(公告)日：2010-03-16
申请号：US11564238
申请日：2006-11-28
申请人： Yi-Nan Chen , Jeng-Ping Lin , Chih-Ching Lin , Hui-Min Mao
发明人： Yi-Nan Chen , Jeng-Ping Lin , Chih-Ching Lin , Hui-Min Mao
IPC分类号： H01L21/4763
CPC分类号： H01L21/76897 , H01L21/76885 , H01L27/105 , H01L27/1052 , H01L27/10888
摘要： A fabrication method for a damascene bit line contact plug. A semiconductor substrate has a first gate conductive structure, a second gate conductive structure and a source/drain region formed therebetween. A first conductive layer is formed in a space between the first gate conductive structure and the second gate conductive structure to be electrically connected to the source/drain region. An inter-layer dielectric with a planarized surface is formed to cover the first conductive layer, the first gate conductive structure, and the second gate conductive structure. A bit line contact hole is formed in the inter-layer dielectric to expose the top of the first conductive layer. A second conductive layer is formed in the bit line contact hole, in which the combination of the second conductive layer and the first conductive layer serves as a damascene bit line contact plug.
摘要翻译：镶嵌位线接触插头的制造方法。半导体衬底具有形成在其间的第一栅极导电结构，第二栅极导电结构和源极/漏极区。第一导电层形成在第一栅极导电结构和第二栅极导电结构之间的空间中，以电连接到源极/漏极区。形成具有平坦化表面的层间电介质以覆盖第一导电层，第一栅极导电结构和第二栅极导电结构。在层间电介质中形成位线接触孔，露出第一导电层的顶部。第二导电层形成在位线接触孔中，其中第二导电层和第一导电层的组合用作镶嵌位线接触插塞。

2. 发明授权

US07211483B2 Memory device with vertical transistors and deep trench capacitors and method of fabricating the same 有权
标题翻译：具有垂直晶体管和深沟槽电容器的存储器件及其制造方法
公开(公告)号：US07211483B2
公开(公告)日：2007-05-01
申请号：US11068173
申请日：2005-02-28
申请人： Yi-Nan Chen , Hui-Min Mao , Chih-Yuan Hsiao , Ming-Cheng Chang
发明人： Yi-Nan Chen , Hui-Min Mao , Chih-Yuan Hsiao , Ming-Cheng Chang
IPC分类号： H01L21/8242
CPC分类号： H01L27/10864 , H01L27/10867
摘要： A memory device with vertical transistors and deep trench capacitors. The device includes a substrate containing at least one deep trench and a capacitor deposited in the lower portion of the deep trench. A conducting structure, having a first conductive layer and a second conductive layer, is deposited on the trench capacitor. A ring shaped insulator is deposited on the sidewall and between the substrate and the first conductive layer. The first conductive layer is surrounded by the ring shaped insulator, and the second conductive layer is deposited on the first conductive layer and the ring shaped insulator. A diffusion barrier between the second conductive layer and the substrate of the deep trench is deposited on one side of the sidewall of the deep trench. A TTO is deposited on the conducting structure. A control gate is deposited on the TTO.
摘要翻译：具有垂直晶体管和深沟槽电容器的存储器件。该器件包括含有至少一个深沟槽和沉积在深沟槽的下部的电容器的衬底。具有第一导电层和第二导电层的导电结构沉积在沟槽电容器上。环形绝缘体沉积在侧壁上以及衬底和第一导电层之间。第一导电层被环形绝缘体包围，并且第二导电层沉积在第一导电层和环形绝缘体上。在深沟槽的侧壁的一侧上沉积第二导电层和深沟槽的衬底之间的扩散阻挡层。 TTO沉积在导电结构上。控制门被存放在TTO上。

3. 发明授权

US07135783B2 Contact etching utilizing partially recessed hard mask 有权
标题翻译：接触蚀刻利用部分凹陷的硬掩模
公开(公告)号：US07135783B2
公开(公告)日：2006-11-14
申请号：US10923585
申请日：2004-08-20
申请人： Wen-Kuei Hsieh , Hui-Min Mao , Yi-Nan Chen
发明人： Wen-Kuei Hsieh , Hui-Min Mao , Yi-Nan Chen
IPC分类号： H01L23/544 , H01L23/48 , H01L23/52
CPC分类号： H01L23/544 , H01L21/31144 , H01L21/76802 , H01L23/485 , H01L2924/0002 , H01L2924/00
摘要： A method for forming contact holes using a partially recessed hard mask. A substrate with a device region and an alignment region having an opening therein, acting as an alignment mark, is provided. A dielectric layer is formed overlying the substrate and fills the opening. A polysilicon layer is formed on the dielectric layer, with over the opening on the alignment region comprising a recessed region and on the device region comprising a plurality of holes therein to expose the underlying dielectric layer. The exposed dielectric layer on the device region is etched to form contact holes therein.
摘要翻译：使用部分凹入的硬掩模形成接触孔的方法。提供具有装置区域和其中具有开口的对准区域的基板，用作对准标记。形成覆盖在基板上并填充开口的电介质层。在电介质层上形成多晶硅层，其中对准区域上的开口包括凹陷区域，并且在其上包括多个孔的器件区域上露出下面的介电层。蚀刻器件区域上的暴露的电介质层以在其中形成接触孔。

4. 发明授权

US07105453B2 Method for forming contact holes 有权
标题翻译：形成接触孔的方法
公开(公告)号：US07105453B2
公开(公告)日：2006-09-12
申请号：US10783467
申请日：2004-02-20
申请人： Yi-Nan Chen , Tse-Yao Huang , Hui-Min Mao
发明人： Yi-Nan Chen , Tse-Yao Huang , Hui-Min Mao
IPC分类号： H01L21/302 , H01L21/3065
CPC分类号： H01L21/76844 , H01L21/76805 , H01L21/76816 , H01L21/76897
摘要： A method of forming contact holes. A substrate on which a plurality of gate structures is formed is provided, wherein the gate structure comprises a gate, a gate capping layer, and a gate spacer. An insulating layer is formed on the gate structures and fills between the gate structures. The insulating layer is etched using the gate capping layers, the gate spacers, and the substrate as stop layers to form first contact holes between the gate structures to expose the substrate and the gate spacers and form second contact holes overlying each gate structure to expose the gate capping layers. A protective spacer is formed over each sidewall of the first contact holes and the second contact holes. The gate capping layer under each gate contact hole is etched using the protective spacer as a stop layer to expose the gate. The protective spacers are removed.
摘要翻译：一种形成接触孔的方法。提供形成有多个栅极结构的基板，其中栅极结构包括栅极，栅极覆盖层和栅极间隔物。在栅极结构上形成绝缘层，并填充在栅极结构之间。使用栅极覆盖层，栅极间隔物和衬底作为停止层来蚀刻绝缘层，以在栅极结构之间形成第一接触孔，以暴露衬底和栅极间隔物，并形成覆盖每个栅极结构的第二接触孔，以暴露出门盖层。在第一接触孔和第二接触孔的每个侧壁上形成保护隔离物。在每个栅极接触孔下方的栅极覆盖层使用保护隔板作为停止层进行蚀刻，以露出栅极。去除保护性间隔物。

5. 发明申请

US20060118886A1 Method of forming bit line contact via 审中-公开
标题翻译：形成位线接触通孔的方法
公开(公告)号：US20060118886A1
公开(公告)日：2006-06-08
申请号：US11338330
申请日：2006-01-23
申请人： Tzu-Ching Tsai , Yi-Nan Chen , Hui-Min Mao
发明人： Tzu-Ching Tsai , Yi-Nan Chen , Hui-Min Mao
IPC分类号： H01L29/772
CPC分类号： H01L21/76897 , H01L21/76829 , H01L21/76895
摘要： A method of forming a bit line contact via. The method includes providing a substrate having a transistor with a gate electrode, drain region, and source region, forming a conductive layer overlying the drain region, conformally forming an insulating barrier layer overlying the substrate, blanketly forming a dielectric layer overlying the insulating barrier layer, and forming a via through the dielectric layer and insulating barrier layer, exposing the conductive layer.
摘要翻译：形成位线接触通孔的方法。该方法包括提供具有晶体管的衬底，该晶体管具有栅极，漏极区和源极区，形成覆盖漏极区的导电层，保形地形成覆盖衬底的绝缘阻挡层，覆盖在绝缘阻挡层上的绝缘层并且通过介电层和绝缘阻挡层形成通孔，暴露导电层。

6. 发明授权

US06909136B2 Trench-capacitor DRAM cell having a folded gate conductor 有权
标题翻译：具有折叠栅极导体的沟槽电容器DRAM单元
公开(公告)号：US06909136B2
公开(公告)日：2005-06-21
申请号：US10604344
申请日：2003-07-14
申请人： Yinan Chen , Ming-Cheng Chang , Jeng-Ping Lin , Tse-Yao Huang , Change-Rong Wu , Hui-Min Mao
发明人： Yinan Chen , Ming-Cheng Chang , Jeng-Ping Lin , Tse-Yao Huang , Change-Rong Wu , Hui-Min Mao
IPC分类号： H01L21/108 , H01L21/334 , H01L21/8242 , H01L27/108 , H01L29/94
CPC分类号： H01L27/10864 , H01L27/10832 , H01L29/66181 , H01L29/945
摘要： A novel trench-capacitor DRAM cell structure is disclosed. The trench-capacitor DRAM cell of this invention includes an active area island having a horizontal semiconductor surface and a vertical sidewall contiguous with the horizontal semiconductor surface. A pass transistor is disposed at the corner of the active area island. The pass transistor includes a folded gate conductor strip extending from the horizontal semiconductor surface to the vertical sidewall of the active area island, a source formed in the horizontal semiconductor surface, a drain formed in the vertical sidewall, and a gate oxide layer underneath the folded gate conductor strip. The source and drain define a folded channel. The trench-capacitor DRAM cell further includes a trench capacitor that is insulated from the folded gate conductor strip by a trench top oxide (TTO) layer and is coupled to the pass transistor via the drain.
摘要翻译：公开了一种新颖的沟槽电容器DRAM单元结构。本发明的沟槽电容器DRAM单元包括具有水平半导体表面的有源区域岛和与水平半导体表面邻接的垂直侧壁。传输晶体管设置在有源区域岛的拐角处。传输晶体管包括从水平半导体表面延伸到有源区岛的垂直侧壁的折叠栅极导体条，形成在水平半导体表面中的源，在垂直侧壁中形成的漏极和在折叠的下面的栅极氧化物层栅极导体条。源极和漏极限定折叠通道。沟槽电容器DRAM单元还包括沟槽电容器，其通过沟槽顶部氧化层（TTO）层与折叠的栅极导体条绝缘，并且经由漏极耦合到传输晶体管。

7. 发明申请

US20050012131A1 TRENCH-CAPACITOR DRAM CELL HAVING A FOLDED GATE CONDUCTOR 有权
标题翻译：具有折叠门控导体的TRENCH-CAPACITOR DRAM单元
公开(公告)号：US20050012131A1
公开(公告)日：2005-01-20
申请号：US10604344
申请日：2003-07-14
申请人： Yinan Chen , Ming-Cheng Chang , Jeng-Ping Lin , Tse-Yao Huang , Chang-Rong Wu , Hui-Min Mao
发明人： Yinan Chen , Ming-Cheng Chang , Jeng-Ping Lin , Tse-Yao Huang , Chang-Rong Wu , Hui-Min Mao
IPC分类号： H01L21/108 , H01L21/334 , H01L21/8242 , H01L27/108 , H01L29/94
CPC分类号： H01L27/10864 , H01L27/10832 , H01L29/66181 , H01L29/945
摘要： A novel trench-capacitor DRAM cell structure is disclosed. The trench-capacitor DRAM cell of this invention includes an active area island having a horizontal semiconductor surface and a vertical sidewall contiguous with the horizontal semiconductor surface. A pass transistor is disposed at the corner of the active area island. The pass transistor includes a folded gate conductor strip extending from the horizontal semiconductor surface to the vertical sidewall of the active area island, a source formed in the horizontal semiconductor surface, a drain formed in the vertical sidewall, and a gate oxide layer underneath the folded gate conductor strip. The source and drain define a folded channel. The trench-capacitor DRAM cell further includes a trench capacitor that is insulated from the folded gate conductor strip by a trench top oxide (TTO) layer and is coupled to the pass transistor via the drain.
摘要翻译：公开了一种新颖的沟槽电容器DRAM单元结构。本发明的沟槽电容器DRAM单元包括具有水平半导体表面的有源区域岛和与水平半导体表面邻接的垂直侧壁。传输晶体管设置在有源区域岛的拐角处。传输晶体管包括从水平半导体表面延伸到有源区岛的垂直侧壁的折叠栅极导体条，形成在水平半导体表面中的源，在垂直侧壁中形成的漏极和在折叠的下面的栅极氧化物层栅极导体条。源极和漏极限定折叠通道。沟槽电容器DRAM单元还包括沟槽电容器，其通过沟槽顶部氧化层（TTO）层与折叠的栅极导体条绝缘，并且经由漏极耦合到传输晶体管。

8. 发明申请

US20050001256A1 Memory device with vertical transistors and deep trench capacitors and method of fabricating the same 有权
公开(公告)号：US20050001256A1
公开(公告)日：2005-01-06
申请号：US10691173
申请日：2003-10-22
申请人： Yi-Nan Chen , Hui-Min Mao , Chih-Yuan Hsiao , Ming-Cheng Chang
发明人： Yi-Nan Chen , Hui-Min Mao , Chih-Yuan Hsiao , Ming-Cheng Chang
IPC分类号： H01L21/8242 , H01L27/108 , H01L29/76 , H01L31/119
CPC分类号： H01L27/10864 , H01L27/10867
摘要： A memory device with vertical transistors and deep trench capacitors. The device includes a substrate containing at least one deep trench and a capacitor deposited in the lower portion of the deep trench. A conducting structure, having a first conductive layer and a second conductive layer, is deposited on the trench capacitor. A ring shaped insulator is deposited on the sidewall and between the substrate and the first conductive layer. The first conductive layer is surrounded by the ring shaped insulator, and the second conductive layer is deposited on the first conductive layer and the ring shaped insulator. A diffusion barrier between the second conductive layer and the substrate of the deep trench is deposited on one side of the sidewall of the deep trench. A TTO is deposited on the conducting structure. A control gate is deposited on the TTO.

9. 发明授权

US06790765B1 Method for forming contact 有权
标题翻译：形成接触的方法
公开(公告)号：US06790765B1
公开(公告)日：2004-09-14
申请号：US10720275
申请日：2003-11-25
申请人： Tse-Yao Huang , Yi-Nan Chen , Hui-Min Mao
发明人： Tse-Yao Huang , Yi-Nan Chen , Hui-Min Mao
IPC分类号： H01L214763
CPC分类号： H01L21/76897 , H01L27/1052 , H01L27/11521
摘要： A method for forming contacts on a semiconductor device is provided. The method includes steps of forming an opening on a gate contact area, depositing a dielectric layer on a bit-line contact area and the opening, coating a photoresist to etch the dielectric layer, removing the photoresist and finally forming a conductive layer on a bit-line contact opening and a gate contact opening.
摘要翻译：提供了一种用于在半导体器件上形成接触的方法。该方法包括以下步骤：在栅极接触区域上形成开口，在位线接触区域上沉积介电层和开口，涂覆光致抗蚀剂以蚀刻电介质层，去除光致抗蚀剂并最终在一个位上形成导电层线接触开口和门接触开口。

10. 发明授权

US06790735B2 Method of forming source/drain regions in semiconductor devices 有权
公开(公告)号：US06790735B2
公开(公告)日：2004-09-14
申请号：US10449297
申请日：2003-05-29
申请人： Hui-Min Mao , Sheng-Tsung Chen , Yi-Nan Chen , Bo-Ching Jiang , Chih-Yuan Hsiao
发明人： Hui-Min Mao , Sheng-Tsung Chen , Yi-Nan Chen , Bo-Ching Jiang , Chih-Yuan Hsiao
IPC分类号： H01L21336
CPC分类号： H01L27/10894 , H01L27/105 , H01L27/11 , H01L29/6653 , H01L29/6656 , H01L29/6659 , H01L29/7833
摘要： A method of forming source/drain regions in semiconductor devices. First, a substrate having at least one gate structure is provided. Next, first, second, and third insulating spacers are successively formed over the sidewall of the gate structure. Subsequently, ion implantation is performed on the substrate on both sides of the gate structure using the third insulating spacer as a mask to form first doping regions. After the third insulating spacer is removed, ion implantation is performed on the substrate on both sides of the gate structure using the second insulating spacer as a mask to form second doping regions serving as source/drain regions with the first doping regions. Finally, after the second insulating spacer is removed, ion implantation is performed on the substrate on both sides of the gate structure using the first insulating spacer as a mask to form third doping regions, thereby preventing punchthrough.

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式