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1. 发明授权

US10515806B2 Semiconductor device packages and stacked package assemblies including high density interconnections 有权
公开(公告)号：US10515806B2
公开(公告)日：2019-12-24
申请号：US16297477
申请日：2019-03-08
申请人： Advanced Semiconductor Engineering, Inc.
发明人： John Richard Hunt , William T. Chen , Chih-Pin Hung , Chen-Chao Wang
IPC分类号： H01L23/48 , H01L21/108 , H01L23/00 , H01L23/04 , H01L21/768 , H01L23/485 , H01L25/065 , H01L21/683 , H01L23/538 , H01L23/16 , H01L21/56 , H01L27/108 , H01L23/528 , H01L23/31
摘要： A semiconductor device package includes: (1) an electronic device including an active surface and a contact pad adjacent to the active surface; and (2) a redistribution stack including a dielectric layer disposed over the active surface and defining a first opening exposing at least a portion of the contact pad; and a redistribution layer (RDL) disposed over the dielectric layer and including a first trace, wherein the first trace includes a first portion extending over the dielectric layer along a first longitudinal direction adjacent to the first opening, and a second portion disposed in the first opening and extending between the first portion of the first trace and the exposed portion of the contact pad, wherein the second portion of the first trace has a maximum width along a first transverse direction orthogonal to the first longitudinal direction, and the maximum width of the second portion of the first trace is no greater than 3 times of a width of the first portion of the first trace, wherein the second portion of the first trace is disposed between and spaced from opposing sidewalls of the dielectric layer defining the first opening.

2. 发明授权

US09978757B2 Semiconductor device 有权
公开(公告)号：US09978757B2
公开(公告)日：2018-05-22
申请号：US14837177
申请日：2015-08-27
申请人： Semiconductor Energy Laboratory Co., Ltd.
发明人： Shunpei Yamazaki , Jun Koyama , Kiyoshi Kato
IPC分类号： H01L21/8239 , H01L21/8242 , H01L27/115 , H01L23/528 , H01L27/108 , H01L27/1156 , H01L27/11517 , H01L27/12 , H01L49/02 , H01L29/24 , H01L29/78 , H01L29/786 , H01L27/105 , H01L21/108 , G11C16/04 , H01L21/285 , H01L29/66
CPC分类号： H01L27/115 , G11C16/0416 , H01L21/28518 , H01L23/528 , H01L27/10805 , H01L27/10855 , H01L27/11517 , H01L27/1156 , H01L27/1207 , H01L27/1225 , H01L27/1255 , H01L28/40 , H01L29/24 , H01L29/6659 , H01L29/78 , H01L29/7869 , H01L2924/0002 , H01L2924/00
摘要： A first transistor including a channel formation region, a first gate insulating layer, a first gate electrode, and a first source electrode and a first drain electrode; a second transistor including an oxide semiconductor layer, a second source electrode and a second drain electrode, a second gate insulating layer, and a second gate electrode; and a capacitor including one of the second source electrode and the second drain electrode, the second gate insulating layer, and an electrode provided to overlap with one of the second source electrode and the second drain electrode over the second gate insulating layer are provided. The first gate electrode and one of the second source electrode and the second drain electrode are electrically connected to each other.

3. 发明申请

US20180047571A1 SEMICONDUCTOR DEVICE PACKAGES AND STACKED PACKAGE ASSEMBLIES INCLUDING HIGH DENSITY INTERCONNECTIONS 审中-公开
公开(公告)号：US20180047571A1
公开(公告)日：2018-02-15
申请号：US15615665
申请日：2017-06-06
申请人： Advanced Semiconductor Engineering, Inc.
发明人： John Richard HUNT , William T. Chen , Chih-Pin HUNG , Chen-Chao WANG
IPC分类号： H01L21/108 , H01L25/065 , H01L21/56 , H01L23/00 , H01L23/528 , H01L23/485 , H01L23/04 , H01L23/48 , H01L21/768 , H01L27/108
CPC分类号： H01L21/108 , H01L21/56 , H01L21/561 , H01L21/568 , H01L21/6835 , H01L21/76801 , H01L23/04 , H01L23/16 , H01L23/3128 , H01L23/48 , H01L23/485 , H01L23/5283 , H01L23/5389 , H01L24/13 , H01L24/16 , H01L24/19 , H01L24/20 , H01L24/45 , H01L24/73 , H01L24/81 , H01L24/92 , H01L24/96 , H01L24/97 , H01L25/0657 , H01L27/10829 , H01L2221/68345 , H01L2221/68359 , H01L2221/68372 , H01L2224/0401 , H01L2224/04105 , H01L2224/12105 , H01L2224/131 , H01L2224/13147 , H01L2224/16227 , H01L2224/16235 , H01L2224/16237 , H01L2224/24137 , H01L2224/24195 , H01L2224/73253 , H01L2224/73267 , H01L2224/81005 , H01L2224/92244 , H01L2224/96 , H01L2224/97 , H01L2225/1023 , H01L2225/1035 , H01L2225/1041 , H01L2225/1058 , H01L2924/15192 , H01L2924/15311 , H01L2924/18161 , H01L2924/18162 , H01L2924/014 , H01L2924/00014 , H01L2224/81
摘要： A semiconductor device package includes an electronic device and a redistribution stack. The redistribution stack includes a dielectric layer disposed over an active surface of the electronic device and defining an opening exposing at least a portion of a contact pad of the electronic device. The redistribution stack also includes a redistribution layer disposed over the dielectric layer and including a trace. A first portion of the trace extends over the dielectric layer along a longitudinal direction adjacent to the opening, and a second portion of the trace is disposed in the opening and extends between the first portion of the trace and the exposed portion of the contact pad. The second portion of the trace has a maximum width along a transverse direction orthogonal to the longitudinal direction, and the maximum width of the second portion of the trace is no greater than about 3 times of a width of the first portion of the trace.

4. 发明授权

US08581315B2 Semiconductor device having cylindrical lower electrode of capacitor and manufacturing method thereof 失效
标题翻译：具有圆筒形电容器下部电极的半导体器件及其制造方法
公开(公告)号：US08581315B2
公开(公告)日：2013-11-12
申请号：US13366391
申请日：2012-02-06
申请人： Satoru Isogai , Takahiro Kumauchi
发明人： Satoru Isogai , Takahiro Kumauchi
IPC分类号： H01L21/108
CPC分类号： H01L28/60 , H01L27/10817 , H01L27/10852 , H01L28/91
摘要： To provide a semiconductor device including: plural capacitors each including a cylindrical lower electrode having an internal wall and an external wall, and an upper electrode that covers the external wall of the lower electrode via a capacitance dielectric film; and a supporting film having a buried portion buried in an internal region surrounded by the internal wall of the lower electrode, and a supporting portion a part of which is positioned within the internal region and remaining parts of which are positioned at outside of the internal region. The supporting portion sandwiches an upper end of the lower electrode at both ends of the upper end by covering the internal wall and the external wall of the upper end of the lower electrode.
摘要翻译：提供一种半导体器件，包括：多个电容器，每个电容器包括具有内壁和外壁的圆筒形下电极和经由电容电介质膜覆盖下电极的外壁的上电极; 以及支撑膜，其具有掩埋在由所述下部电极的内壁包围的内部区域中的掩埋部，以及支撑部，其一部分位于所述内部区域内，其余部分位于所述内部区域的外侧。支撑部分通过覆盖下电极的上壁和外壁的内壁和下壁的外壁来夹住下端电极在上端两端的上端。

5. 发明授权

US07285813B2 Metal-insulator-metal capacitor and method for manufacturing the same 有权
标题翻译：金属绝缘体金属电容器及其制造方法
公开(公告)号：US07285813B2
公开(公告)日：2007-10-23
申请号：US11265574
申请日：2005-11-02
申请人： Sang-Hoon Park
发明人： Sang-Hoon Park
IPC分类号： H01L21/108
CPC分类号： H01L21/76838 , H01L21/76807 , H01L27/1085 , H01L28/60
摘要： A capacitor has a lower electrode formed on an insulation layer, a dielectric layer formed on the lower electrode, an upper electrode layer formed on the dielectric layer, and a first protection layer pattern formed on the upper electrode layer. The upper electrode layer is etched using the first protection layer pattern to form an upper electrode. A second protection layer is formed enclosing the dielectric layer, the upper electrode and the first protection layer pattern.
摘要翻译：电容器具有形成在绝缘层上的下电极，形成在下电极上的电介质层，形成在电介质层上的上电极层，以及形成在上电极层上的第一保护层图案。使用第一保护层图案蚀刻上电极层以形成上电极。形成包围电介质层，上电极和第一保护层图案的第二保护层。

6. 发明授权

US5292683A Method of isolating semiconductor devices and arrays of memory integrated circuitry 失效
标题翻译：隔离半导体器件和存储器集成电路阵列的方法
公开(公告)号：US5292683A
公开(公告)日：1994-03-08
申请号：US71752
申请日：1993-06-09
申请人： Charles H. Dennison , Trung T. Doan
发明人： Charles H. Dennison , Trung T. Doan
IPC分类号： H01L21/76 , H01L21/108 , H01L21/762 , H01L21/8234 , H01L21/8242 , H01L27/108 , H01L29/78 , H01L21/304
CPC分类号： H01L27/10852 , H01L21/76224 , H01L21/823481 , Y10S148/05
摘要： A semiconductor processing device isolation method includes: a) providing non-LOCOS insulating device isolation blocks by trench and refill technique on a substrate to define recessed moat volume therebetween; b) providing gate dielectric within the moat volume; c) providing a layer of electrically conductive material over the substrate and gate dielectric to a thickness sufficient to completely fill the moat volume between adjacent isolation blocks; d) chemical-mechanical polishing the layer of electrically conductive material to provide a planarized upper electrically conductive material surface; e) photopatterning and etching the layer of electrically conductive material to provide an electrically conductive runner which overlies a plurality of the isolation blocks and to selectively remove the electrically conductive material from within selected regions of moat volume to define field effect transistor gates within the moat volume; and f) providing conductivity enhancing impurity through the selected regions of moat volume into the substrate to define source/drain regions adjacent the field effect transistor gates. The invention also includes an array of memory integrated circuitry.
摘要翻译：半导体处理器件隔离方法包括：a）通过沟槽和再填充技术在衬底上提供非LOCOS绝缘器件隔离块，以在其间限定凹陷的沟槽体积; b）在护城河容积内提供栅极电介质; c）在衬底和栅极电介质上提供一层导电材料，其厚度足以完全填充相邻隔离块之间的护城河体积; d）化学机械抛光导电材料层以提供平坦化的上导电材料表面; e）对导电材料层进行光图案化和蚀刻，以提供覆盖在多个隔离块上的导电浇道，并且选择性地从导流槽体积的选定区域内去除导电材料，以在护城河体积内限定场效应晶体管栅极 ; 以及f）通过所选择的沟槽体积的区域提供导电性增强杂质到衬底中以限定与场效应晶体管栅极相邻的源极/漏极区域。本发明还包括一组存储器集成电路。

7. 发明授权

US2908592A Method of producing a selenium rectifier 失效
标题翻译：硒精整炉的生产方法
公开(公告)号：US2908592A
公开(公告)日：1959-10-13
申请号：US55842356
申请日：1956-01-11
申请人： INT STANDARD ELECTRIC CORP
发明人： JOSEF STROSCHE HERMANN KARL
IPC分类号： D04B35/10 , D06B3/04 , H01L21/08 , H01L21/10 , H01L21/103 , H01L21/108 , H01L21/12 , H01L25/07 , H01L29/00
CPC分类号： D06B3/04 , D06B2700/25 , H01L21/08 , H01L21/10 , H01L21/101 , H01L21/103 , H01L21/108 , H01L21/12 , H01L25/074 , H01L29/00 , H01L2924/0002 , Y10S62/20 , Y10T428/12535 , Y10T428/12681 , Y10T428/12708 , H01L2924/00

8. 发明授权

US2903632A Selenium cells 失效
公开(公告)号：US2903632A
公开(公告)日：1959-09-08
申请号：US74255758
申请日：1958-06-17
申请人： GEN ELECTRIC
发明人： PEROTTE LAURENCE F
IPC分类号： H01L21/108
CPC分类号： H01L21/108 , H01L21/02521

9. 发明授权

US2881371A Power transmission 失效
公开(公告)号：US2881371A
公开(公告)日：1959-04-07
申请号：US66121557
申请日：1957-05-23
申请人： VICKERS INC
发明人： CALDWELL PAUL N
IPC分类号： H01L21/108
CPC分类号： H01L21/108 , H01L21/02521 , H01L21/02625 , H01L21/02631 , H01L21/02667

10. 发明授权

US2832923A High voltage rectifier 失效
标题翻译：高压整流器
公开(公告)号：US2832923A
公开(公告)日：1958-04-29
申请号：US47189954
申请日：1954-11-29
申请人： ITT
发明人： WILLIAM LEWANDA
IPC分类号： H01L21/108
CPC分类号： H01L21/108

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