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1. 发明授权

US09479431B1 Route prediction in packet switched networks 有权
公开(公告)号：US09479431B1
公开(公告)日：2016-10-25
申请号：US14854286
申请日：2015-09-15
申请人： Ian Rudolf Bratt , Carl G. Ramey , Matthew Mattina
发明人： Ian Rudolf Bratt , Carl G. Ramey , Matthew Mattina
IPC分类号： H04L12/28 , H04L12/703 , H04L12/751 , H04L12/707 , H04L12/933
CPC分类号： G06F9/5022 , G06F9/4825 , G06F9/4881 , G06F9/544 , G06F11/1482 , G06F12/00 , G06F12/02 , G06F12/0806 , G06F12/0808 , G06F12/0844 , G06F12/0848 , G06F12/0864 , G06F12/0891 , G06F12/10 , G06F12/1027 , G06F12/12 , G06F12/121 , G06F12/123 , G06F13/4068 , G06F13/4221 , G06F15/16 , G06F15/8023 , G06F21/79 , G06F2212/502 , G06F2212/601 , H04L45/08 , H04L45/22 , H04L45/28 , H04L47/823 , H04L49/109
摘要： Communicating among nodes in a network includes: sending a packet from an origin node to a destination node over a route including plural nodes. At each node in the route, routing of the packet is initiated according to a predicted path concurrently with verifying the correctness of the predicted path based on analyzing route information in the packet. In response to results of verifying the correctness of the predicted path, the routing of the packet is completed according to the predicted path or initiating a routing of the packet according to an actual path based on the route information in the packet.

2. 发明授权

US09135215B1 Route prediction in packet switched networks 有权
标题翻译：分组交换网络中的路由预测
公开(公告)号：US09135215B1
公开(公告)日：2015-09-15
申请号：US12886163
申请日：2010-09-20
申请人： Ian Rudolf Bratt , Carl G. Ramey , Matthew Mattina
发明人： Ian Rudolf Bratt , Carl G. Ramey , Matthew Mattina
IPC分类号： H04L12/28 , G06F15/80 , H04L12/911
CPC分类号： G06F9/5022 , G06F9/4825 , G06F9/4881 , G06F9/544 , G06F11/1482 , G06F12/00 , G06F12/02 , G06F12/0806 , G06F12/0808 , G06F12/0844 , G06F12/0848 , G06F12/0864 , G06F12/0891 , G06F12/10 , G06F12/1027 , G06F12/12 , G06F12/121 , G06F12/123 , G06F13/4068 , G06F13/4221 , G06F15/16 , G06F15/8023 , G06F21/79 , G06F2212/502 , G06F2212/601 , H04L45/08 , H04L45/22 , H04L45/28 , H04L47/823 , H04L49/109
摘要： Communicating among nodes in a network includes: sending a packet from an origin node to a destination node over a route including plural nodes. At each node in the route, routing of the packet is initiated according to a predicted path concurrently with verifying the correctness of the predicted path based on analyzing route information in the packet. In response to results of verifying the correctness of the predicted path, the routing of the packet is completed according to the predicted path or initiating a routing of the packet according to an actual path based on the route information in the packet.
摘要翻译：在网络中的节点之间进行通信包括：通过包括多个节点的路由将分组从原始节点发送到目的地节点。在路由中的每个节点，基于分组中的路由信息，根据预测路径同时发起分组的路由，同时验证预测路径的正确性。响应于验证预测路径的正确性的结果，根据预测路径完成分组的路由，或者基于分组中的路由信息根据实际路径发起分组的路由。

3. 发明授权

US08934347B1 Low latency dynamic route selection 有权
标题翻译：低延迟动态路由选择
公开(公告)号：US08934347B1
公开(公告)日：2015-01-13
申请号：US12886346
申请日：2010-09-20
申请人： Ian Rudolf Bratt , Carl G. Ramey , Matthew Mattina
发明人： Ian Rudolf Bratt , Carl G. Ramey , Matthew Mattina
IPC分类号： G06F11/00
CPC分类号： G06F9/5022 , G06F9/4825 , G06F9/4881 , G06F9/544 , G06F11/1482 , G06F12/00 , G06F12/02 , G06F12/0806 , G06F12/0808 , G06F12/0844 , G06F12/0848 , G06F12/0864 , G06F12/0891 , G06F12/10 , G06F12/1027 , G06F12/12 , G06F12/121 , G06F12/123 , G06F13/4068 , G06F13/4221 , G06F15/16 , G06F15/8023 , G06F21/79 , G06F2212/502 , G06F2212/601 , H04L45/08 , H04L45/22 , H04L45/28 , H04L47/823 , H04L49/109
摘要： Communicating among cores in a computing system comprising a plurality of cores, each core comprising a processor and a switch, includes: routing a packet from a core or from a device coupled to at least one core to a destination over a route including one or more cores, with an order of dimensions associated with the route being selected dynamically upon construction of the packet; routing the packet to a first core in the route over the first selected dimension; and routing the packet from the first core to the destination over the second dimension.
摘要翻译：在包括多个核心的计算系统中的核心之间进行通信，每个核心包括处理器和交换机，包括：通过包括一个或多个路由的路由将来自核心或从耦合到至少一个核心的设备的分组路由到目的地核心，在构建分组时具有与路线相关联的维度顺序被动态地选择; 将所述分组路由到所述路由中的所述第一选定维度上的第一核心; 并且在第二维度上将分组从第一核心路由到目的地。

4. 发明授权

US08151088B1 Configuring routing in mesh networks 有权
标题翻译：配置网状网络中的路由
公开(公告)号：US08151088B1
公开(公告)日：2012-04-03
申请号：US12169456
申请日：2008-07-08
申请人： Liewei Bao , Ian Rudolf Bratt
发明人： Liewei Bao , Ian Rudolf Bratt
IPC分类号： G06F15/76 , G06F15/16 , G06F15/173
CPC分类号： G06F15/17312
摘要： A plurality of processor tiles are provided, each processor tile including a processor core. An interconnection network interconnects the processor cores and enables transfer of data among the processor cores. The interconnection network has a plurality of dimensions and is configurable to transmit data from an initial processor core or an input/output device to an intermediate processor core based on a first dimension ordering policy, and from the intermediate processor core to a destination processor core. The first dimension ordering policy specifies an ordering of the dimensions of the interconnection network when routing data through the interconnection network.
摘要翻译：提供多个处理器片，每个处理器片包括处理器核。互连网络将处理器核心互连，并实现处理器内核之间的数据传输。互连网络具有多个维度并且可配置为基于第一维排序策略以及从中间处理器核向目的地处理器核心将初始处理器内核或输入/输出设备的数据传输到中间处理器核心。第一维排序策略指定当通过互连网络路由数据时互连网络的维度的顺序。

5. 发明授权

US10073778B1 Caching in multicore and multiprocessor architectures 有权
公开(公告)号：US10073778B1
公开(公告)日：2018-09-11
申请号：US15368947
申请日：2016-12-05
申请人： Ian Rudolf Bratt , Matthew Mattina
发明人： Anant Agarwal , Ian Rudolf Bratt , Matthew Mattina
IPC分类号： G06F12/08 , G06F12/0817 , G06F12/0811 , G06F12/084 , G06F12/1081 , G06F13/40
CPC分类号： G06F12/0817 , G06F12/0811 , G06F12/0815 , G06F12/084 , G06F12/1081 , G06F13/4022 , G06F2212/60 , G06F2212/621
摘要： A multicore processor comprises a plurality of cache memories, and a plurality of processor cores, each associated with one of the cache memories. Each of at least some of the cache memories is configured to maintain at least a portion of the cache memory in which each cache line is dynamically managed as either local to the associated processor core or shared among multiple processor cores.

6. 发明授权

US09213652B1 Managing cache access and streaming data 有权
标题翻译：管理缓存访问和流数据
公开(公告)号：US09213652B1
公开(公告)日：2015-12-15
申请号：US12886365
申请日：2010-09-20
申请人： Chyi-Chang Miao , Christopher D. Metcalf , Ian Rudolf Bratt , Carl G. Ramey
发明人： Chyi-Chang Miao , Christopher D. Metcalf , Ian Rudolf Bratt , Carl G. Ramey
IPC分类号： G06F12/12 , G06F12/08
CPC分类号： G06F9/5022 , G06F9/4825 , G06F9/4881 , G06F9/544 , G06F11/1482 , G06F12/00 , G06F12/02 , G06F12/0806 , G06F12/0808 , G06F12/0844 , G06F12/0848 , G06F12/0864 , G06F12/0891 , G06F12/10 , G06F12/1027 , G06F12/12 , G06F12/121 , G06F12/123 , G06F13/4068 , G06F13/4221 , G06F15/16 , G06F15/8023 , G06F21/79 , G06F2212/502 , G06F2212/601 , H04L45/08 , H04L45/22 , H04L45/28 , H04L47/823 , H04L49/109
摘要： Managing data in a computing system comprising one or more cores includes: providing a cache in each of one or more of the cores that includes multiple storage locations; storing data of a first type of multiple types of data in a selected storage location of a first cache of a first core that is selected according to status information associated with the first cache, and updating the status information; and storing data of a second type of the multiple types of data in a storage location within a subset of fewer than all of the storage locations of the first cache and managing the status information to ensure that subsequent data of the second type received by the first core for storage in the first cache is stored in the storage location within the subset.
摘要翻译：在包括一个或多个核心的计算系统中管理数据包括：在包括多个存储位置的一个或多个核心的每一个中提供高速缓存; 将第一种类型的数据的数据存储在根据与第一高速缓存相关联的状态信息选择的第一核心的第一高速缓存的选定存储位置中，并更新状态信息; 以及将所述多种类型的数据的第二类型的数据存储在所述第一高速缓存的少于所有存储位置的子集的子集内的存储位置中，并且管理所述状态信息，以确保由所述第一高速缓存器接收到的所述第二类型的后续数据存储在第一缓存中的核心存储在子集内的存储位置。

7. 发明授权

US08737392B1 Configuring routing in mesh networks 有权
标题翻译：配置网状网络中的路由
公开(公告)号：US08737392B1
公开(公告)日：2014-05-27
申请号：US13278663
申请日：2011-10-21
申请人： Liewei Bao , Ian Rudolf Bratt
发明人： Liewei Bao , Ian Rudolf Bratt
IPC分类号： H04L12/50
CPC分类号： H04L45/126
摘要： A processor includes a plurality of processor tiles, each tile including a processor core, and an interconnection network interconnects the processor cores and enables transfer of data among the processor cores. The interconnection network has a plurality of dimensions in which an ordering of dimensions for routing data is configurable.
摘要翻译：处理器包括多个处理器片，每个片包括处理器核，并且互连网互连处理器核并且使得能够在处理器核之间传送数据。互连网络具有多个维度，其中用于路由数据的维度的排序是可配置的。

8. 发明授权

US08521963B1 Managing cache coherence 有权
标题翻译：管理缓存一致性
公开(公告)号：US08521963B1
公开(公告)日：2013-08-27
申请号：US12886376
申请日：2010-09-20
申请人： Chyi-Chang Miao , Christopher D. Metcalf , Ian Rudolf Bratt , Carl G. Ramey
发明人： Chyi-Chang Miao , Christopher D. Metcalf , Ian Rudolf Bratt , Carl G. Ramey
IPC分类号： G06F12/00
CPC分类号： G06F9/5022 , G06F9/4825 , G06F9/4881 , G06F9/544 , G06F11/1482 , G06F12/00 , G06F12/02 , G06F12/0806 , G06F12/0808 , G06F12/0844 , G06F12/0848 , G06F12/0864 , G06F12/0891 , G06F12/10 , G06F12/1027 , G06F12/12 , G06F12/121 , G06F12/123 , G06F13/4068 , G06F13/4221 , G06F15/16 , G06F15/8023 , G06F21/79 , G06F2212/502 , G06F2212/601 , H04L45/08 , H04L45/22 , H04L45/28 , H04L47/823 , H04L49/109
摘要： Managing data in a computing system comprising multiple cores includes: assigning a first set of data to caches within cores of a first subset of fewer than all of the cores in the computing system, and assigning a second set of data to caches within cores of a second subset of at least some remaining cores in the computing system not already assigned; and maintaining cache coherence among caches of respective cores in the first subset in response to data stored in at least one of the cores in the first subset being modified, and maintaining cache coherence among caches of respective cores in the second subset in response to data stored in at least one of the cores in the second subset being modified.
摘要翻译：在包括多个核心的计算系统中管理数据包括：将第一组数据分配给计算系统中少于所有核心的第一子集的核心内的高速缓存，以及将第二组数据分配给计算系统中尚未分配的至少一些剩余核心的第二子集; 以及响应于存储在所述第一子集中的至少一个核心中的数据被修改，并且响应于所存储的数据而保持所述第二子集中的相应核心的高速缓存之间的高速缓存一致性，以及在所述第一子集中的相应核心的高速缓存之间维持高速缓存一致性在第二子集中的至少一个核心被修改。

9. 发明授权

US08050256B1 Configuring routing in mesh networks 有权
标题翻译：配置网状网络中的路由
公开(公告)号：US08050256B1
公开(公告)日：2011-11-01
申请号：US12169436
申请日：2008-07-08
申请人： Leiwei Bao , Ian Rudolf Bratt
发明人： Leiwei Bao , Ian Rudolf Bratt
IPC分类号： H04L12/50
CPC分类号： H04L45/126
摘要： A processor includes a plurality of processor tiles, each tile including a processor core, and an interconnection network interconnects the processor cores and enables transfer of data among the processor cores. The interconnection network has a plurality of dimensions in which an ordering of dimensions for routing data is configurable.
摘要翻译：处理器包括多个处理器片，每个片包括处理器核，并且互连网互连处理器核并且使得能够在处理器核之间传送数据。互连网络具有多个维度，其中用于路由数据的维度的排序是可配置的。

10. 发明授权

US10282338B1 Configuring routing in mesh networks 有权
公开(公告)号：US10282338B1
公开(公告)日：2019-05-07
申请号：US15201754
申请日：2016-07-05
申请人： Liewei Bao , Ian Rudolf Bratt
发明人： Liewei Bao , Ian Rudolf Bratt
IPC分类号： G06F3/00 , G06F13/40 , G06F13/42
摘要： A plurality of processor tiles are provided, each processor tile including a processor core. An interconnection network interconnects the processor cores and enables transfer of data among the processor cores. An extension network connects input/output ports of the interconnection network to input/output ports of one or more peripheral devices, each input/output port of the interconnection network being associated with one of the processor tiles such that each input/output port of the interconnection network sends input data to the corresponding processor tile and receives output data from the corresponding processor tile. The extension network is configurable such that a mapping between input/output ports of the interconnection network and input/output ports of the one or more peripheral devices is configurable.

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