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1. 发明授权

US08737392B1 Configuring routing in mesh networks 有权
标题翻译：配置网状网络中的路由
公开(公告)号：US08737392B1
公开(公告)日：2014-05-27
申请号：US13278663
申请日：2011-10-21
申请人： Liewei Bao , Ian Rudolf Bratt
发明人： Liewei Bao , Ian Rudolf Bratt
IPC分类号： H04L12/50
CPC分类号： H04L45/126
摘要： A processor includes a plurality of processor tiles, each tile including a processor core, and an interconnection network interconnects the processor cores and enables transfer of data among the processor cores. The interconnection network has a plurality of dimensions in which an ordering of dimensions for routing data is configurable.
摘要翻译：处理器包括多个处理器片，每个片包括处理器核，并且互连网互连处理器核并且使得能够在处理器核之间传送数据。互连网络具有多个维度，其中用于路由数据的维度的排序是可配置的。

2. 发明申请

US20220104793A1 METHODS AND APPARATUSES FOR AZIMUTHAL SUMMING OF ULTRASOUND DATA 有权
公开(公告)号：US20220104793A1
公开(公告)日：2022-04-07
申请号：US17493775
申请日：2021-10-04
申请人： Nevada J. Sanchez , Liewei Bao , Tyler S. Ralston
发明人： Nevada J. Sanchez , Liewei Bao , Tyler S. Ralston
IPC分类号： A61B8/00 , G01S15/89
摘要： Aspects of the technology described herein related to controlling, using control circuitry, modulation circuitry to modulate and delay first ultrasound data generated by first ultrasound transducers positioned at a first azimuthal position of an ultrasound transducer array of an ultrasound device and second ultrasound data generated by second ultrasound transducers positioned at a second azimuthal position of the ultrasound transducer array of the ultrasound device, such that the first ultrasound data is delayed by a first delay amount and the second ultrasound data is delayed by a second delay amount that is different from the first delay amount. The first and second ultrasound data received from the modulation circuitry may be filtered and summed. The ultrasound transducer array, the control circuitry, the modulation circuitry, the filtering circuitry, and the summing circuitry may be integrated onto a semiconductor chip or one or more semiconductor chips packaged together.

3. 发明授权

US10282338B1 Configuring routing in mesh networks 有权
公开(公告)号：US10282338B1
公开(公告)日：2019-05-07
申请号：US15201754
申请日：2016-07-05
申请人： Liewei Bao , Ian Rudolf Bratt
发明人： Liewei Bao , Ian Rudolf Bratt
IPC分类号： G06F3/00 , G06F13/40 , G06F13/42
摘要： A plurality of processor tiles are provided, each processor tile including a processor core. An interconnection network interconnects the processor cores and enables transfer of data among the processor cores. An extension network connects input/output ports of the interconnection network to input/output ports of one or more peripheral devices, each input/output port of the interconnection network being associated with one of the processor tiles such that each input/output port of the interconnection network sends input data to the corresponding processor tile and receives output data from the corresponding processor tile. The extension network is configurable such that a mapping between input/output ports of the interconnection network and input/output ports of the one or more peripheral devices is configurable.

4. 发明授权

US09753854B1 Memory controller load balancing with configurable striping domains 有权
公开(公告)号：US09753854B1
公开(公告)日：2017-09-05
申请号：US14747044
申请日：2015-06-23
申请人： Liewei Bao
发明人： Liewei Bao
IPC分类号： G06F12/00 , G06F12/0844 , G06F12/02 , G06F12/0846
CPC分类号： G06F9/5022 , G06F9/4825 , G06F9/4881 , G06F9/544 , G06F11/1482 , G06F12/00 , G06F12/02 , G06F12/0806 , G06F12/0808 , G06F12/0844 , G06F12/0848 , G06F12/0864 , G06F12/0891 , G06F12/10 , G06F12/1027 , G06F12/12 , G06F12/121 , G06F12/123 , G06F13/4068 , G06F13/4221 , G06F15/16 , G06F15/8023 , G06F21/79 , G06F2212/502 , G06F2212/601 , H04L45/08 , H04L45/22 , H04L45/28 , H04L47/823 , H04L49/109
摘要： Managing data in a computing system comprising a plurality of cores includes: assigning an address within a memory address space for access by one of a plurality of memory controllers coupled to different respective cores based on a designated portion of the address. The designated portion is selected to exclude one or more highest order bits and bits that correspond to a cache line associated with the memory address. In response to a memory access request at one of the cores to access data stored at the address, the system determines which of the plurality of memory controllers to which the memory access request is to be directed based on the designated portion of the address.

5. 发明授权

US06701422B2 Memory control system with incrementer for generating speculative addresses 失效
标题翻译：带增量器的存储器控制系统，用于产生推测地址
公开(公告)号：US06701422B2
公开(公告)日：2004-03-02
申请号：US09823160
申请日：2001-03-29
申请人： Liewei Bao
发明人： Liewei Bao
IPC分类号： G06F1206
CPC分类号： G06F12/0215
摘要： A memory controller includes an incrementer for predicting a next address to be asserted by a processor. The incrementer, structurally a counter, is configurable to wrap at a wrap boundary and to indicate when a predicted address crosses a page boundary if the memory is in page mode. This incrementer provides accurate predictions even where successor addresses are on different pages or, in the case of address loops, even in some cases in which the successor address is not consecutive. Thus, the number of accurate address predictions is increased, enhancing overall performance. The invention has particular applicability to signal processing applications with instructions loops that cross one or more page boundaries.
摘要翻译：存储器控制器包括用于预测由处理器断言的下一个地址的增量器。增量器，结构上是一个计数器，可配置为在包装边界包装，并指示当存储器处于页面模式时，预测地址何时跨越页面边界。即使在后续地址在不同的页面上，或者在地址循环的情况下，即使在某些情况下，后继地址不是连续的，该增量器也提供准确的预测。因此，准确地址预测的数量增加，从而提高整体性能。本发明特别适用于具有跨越一个或多个页面边界的指令循环的信号处理应用。

6. 发明授权

US09384165B1 Configuring routing in mesh networks 有权
标题翻译：配置网状网络中的路由
公开(公告)号：US09384165B1
公开(公告)日：2016-07-05
申请号：US13278676
申请日：2011-10-21
申请人： Liewei Bao , Ian Rudolf Bratt
发明人： Liewei Bao , Ian Rudolf Bratt
IPC分类号： G06F13/14 , G06F15/78
CPC分类号： G06F15/7867 , G06F15/16 , G06F15/17381 , H04L45/14
摘要： A plurality of processor tiles are provided, each processor tile including a processor core. An interconnection network interconnects the processor cores and enables transfer of data among the processor cores. An extension network connects input/output ports of the interconnection network to input/output ports of one or more peripheral devices, each input/output port of the interconnection network being associated with one of the processor tiles such that each input/output port of the interconnection network sends input data to the corresponding processor tile and receives output data from the corresponding processor tile. The extension network is configurable such that a mapping between input/output ports of the interconnection network and input/output ports of the one or more peripheral devices is configurable.
摘要翻译：提供多个处理器片，每个处理器片包括处理器核。互连网络将处理器核心互连，并实现处理器内核之间的数据传输。扩展网络将互连网络的输入/输出端口连接到一个或多个外围设备的输入/输出端口，互连网络的每个输入/输出端口与处理器瓦片之一相关联，使得每个输入/输出端口互连网络将输入数据发送到相应的处理器磁贴，并从相应的处理器磁贴接收输出数据。扩展网络是可配置的，使得互连网络的输入/输出端口与一个或多个外围设备的输入/输出端口之间的映射是可配置的。

7. 发明授权

US09063825B1 Memory controller load balancing with configurable striping domains 有权
标题翻译：内存控制器负载平衡与可配置条带化域
公开(公告)号：US09063825B1
公开(公告)日：2015-06-23
申请号：US12886136
申请日：2010-09-20
申请人： Liewei Bao
发明人： Liewei Bao
IPC分类号： G06F12/00 , G06F12/02 , G06F12/08 , G06F9/54
CPC分类号： G06F9/5022 , G06F9/4825 , G06F9/4881 , G06F9/544 , G06F11/1482 , G06F12/00 , G06F12/02 , G06F12/0806 , G06F12/0808 , G06F12/0844 , G06F12/0848 , G06F12/0864 , G06F12/0891 , G06F12/10 , G06F12/1027 , G06F12/12 , G06F12/121 , G06F12/123 , G06F13/4068 , G06F13/4221 , G06F15/16 , G06F15/8023 , G06F21/79 , G06F2212/502 , G06F2212/601 , H04L45/08 , H04L45/22 , H04L45/28 , H04L47/823 , H04L49/109
摘要： Managing data in a computing system comprising a plurality of cores includes: assigning an address within a memory address space for access by one of a plurality of memory controllers coupled to different respective cores based on a designated portion of the address. The designated portion is selected to exclude one or more highest order bits and bits that correspond to a cache line associated with the memory address. In response to a memory access request at one of the cores to access data stored at the address, the system determines which of the plurality of memory controllers to which the memory access request is to be directed based on the designated portion of the address.
摘要翻译：在包括多个核心的计算系统中管理数据包括：基于地址的指定部分，在耦合到不同的相应核心的多个存储器控制器之一之间分配存储器地址空间内的地址以进行访问。选择指定部分以排除与存储器地址相关联的高速缓存行对应的一个或多个最高位和位。响应于在一个核心处的存储器访问请求以访问存储在地址处的数据，系统基于地址的指定部分确定存储器访问请求将被引导到的多个存储器控制器中的哪一个。

8. 发明授权

US08738860B1 Computing in parallel processing environments 有权
标题翻译：在并行处理环境中进行计算
公开(公告)号：US08738860B1
公开(公告)日：2014-05-27
申请号：US13280927
申请日：2011-10-25
申请人： Patrick Robert Griffin , Mathew Hostetter , Anant Agarwal , Chyi-Chang Miao , Christopher D. Metcalf , Bruce Edwards , Carl G. Ramey , Mark B. Rosenbluth , David M. Wentzlaff , Christopher J. Jackson , Ben Harrison , Kenneth M. Steele , John Amann , Shane Bell , Richard Conlin , Kevin Joyce , Christine Deignan , Liewei Bao , Matthew Mattina , Ian Rudolf Bratt , Richard Schooler
发明人： Patrick Robert Griffin , Mathew Hostetter , Anant Agarwal , Chyi-Chang Miao , Christopher D. Metcalf , Bruce Edwards , Carl G. Ramey , Mark B. Rosenbluth , David M. Wentzlaff , Christopher J. Jackson , Ben Harrison , Kenneth M. Steele , John Amann , Shane Bell , Richard Conlin , Kevin Joyce , Christine Deignan , Liewei Bao , Matthew Mattina , Ian Rudolf Bratt , Richard Schooler
IPC分类号： G06F12/08
CPC分类号： G06F12/0897 , G06F12/0811 , G06F12/0813 , G06F12/1441
摘要： A computing system comprises one or more cores. Each core comprises a processor. In some implementations, each processor is coupled to a communication network among the cores. In some implementations, a switch in each core includes switching circuitry to forward data received over data paths from other cores to the processor and to switches of other cores, and to forward data received from the processor to switches of other cores.
摘要翻译：计算系统包括一个或多个核心。每个核心包括处理器。在一些实现中，每个处理器耦合到核心之间的通信网络。在一些实现中，每个核心中的交换机包括交换电路，用于将通过数据路径从其他核到达处理器的数据路径接收的数据转发到其他核心的交换机，并将从处理器接收的数据转发到其他核心的交换机。

9. 发明授权

US06543030B1 Computer-implemented conversion of combination-logic module for improving timing characteristics of incorporating integrated circuit design 失效
标题翻译：组合逻辑模块的计算机实现转换，用于提高集成电路设计的时序特性
公开(公告)号：US06543030B1
公开(公告)日：2003-04-01
申请号：US09307165
申请日：1999-05-07
申请人： Liewei Bao , Timothy A. Pontius
发明人： Liewei Bao , Timothy A. Pontius
IPC分类号： G06F1750
CPC分类号： G06F17/505 , G06F7/00
摘要： The timing characteristics of an integrated circuit design with an original combination-logic module can be potentially improved by moving an input signal with problematic timing in the original module so that it controls an output multiplexer in a revised module. The revised module includes two submodules. The first submodule provides the desired logic result where the late signal is low; the second submodule provides the desired logic result where the late signal is high. The multiplexer is controlled by the late signal so that its output is the desired logic result under steady-state conditions. If there are other input signals requiring timing advancement, the method can be reiterated. The method can be iterated until specifications are met or it is clear that the method cannot meet specifications by additional iterations.
摘要翻译：具有原始组合逻辑模块的集成电路设计的定时特性可以通过在原始模块中移动具有有问题的定时的输入信号来进行改进，从而其在修改的模块中控制输出多路复用器。修改后的模块包括两个子模块。第一个子模块提供期望的逻辑结果，其中后期信号较低; 第二子模块提供期望的逻辑结果，其中后期信号为高。多路复用器由延迟信号控制，使得其输出在稳态条件下是期望的逻辑结果。如果存在需要定时提前的其他输入信号，则可以重申该方法。该方法可以重复，直到满足规范或者清楚该方法不能通过附加迭代满足规范。

10. 发明授权

US07370152B2 Memory controller with prefetching capability 有权
标题翻译：带预取功能的内存控制器
公开(公告)号：US07370152B2
公开(公告)日：2008-05-06
申请号：US10881413
申请日：2004-06-29
申请人： Steven C. Woo , Bradley A. May , Liewei Bao
发明人： Steven C. Woo , Bradley A. May , Liewei Bao
IPC分类号： G06F12/00
CPC分类号： G06F13/1642 , G06F12/0862 , G06F2212/6022
摘要： A memory controller monitors requests from one or more computer subsystems and issues one or more prefetch commands if the memory controller detects that the memory system is idle after a period of activity, or if a prefetch buffer read hit occurs. In some embodiments, results of a prefetching operations are stored in a prefetch buffer configured to provide an automatic aging mechanism, which evicts prefetched data from time to time. The prefetched data in the prefetch buffer is released and sent back to the requester in order with respect to previous memory access requests.
摘要翻译：如果存储器控制器在一段活动之后检测到存储器系统空闲，或者如果发生预取缓冲器读取命中，则存储器控制器监视来自一个或多个计算机子系统的请求并发出一个或多个预取命令。在一些实施例中，预取操作的结果被存储在预取缓冲器中，该预取缓冲器被配置为提供自动老化机制，其不时地推移预取的数据。预取缓冲器中的预取数据被释放，并相对于先前的存储器访问请求被发送回请求者。

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