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1. 发明申请

US20130242669A1 END-OF-LIFE RELIABILITY FOR NON-VOLATILE MEMORY CELLS 有权
标题翻译：非挥发性记忆细胞的终生可靠性
公开(公告)号：US20130242669A1
公开(公告)日：2013-09-19
申请号：US13423229
申请日：2012-03-18
申请人： Ilan BLOOM , Alexander KUSHNARENKO
发明人： Ilan BLOOM , Alexander KUSHNARENKO
IPC分类号： G11C16/28 , G11C16/04
CPC分类号： G11C16/06 , G11C16/28 , G11C16/3404 , G11C16/3418 , G11C16/349
摘要： A memory chip includes a memory array and a two-dimensional sensing system. The array includes a multiplicity of memory cells connected in rows by word lines and in columns by bit lines. The sensing system moves a read point two-dimensionally within a two-dimensional read space as the two-dimensional read space shrinks and shifts over the life of the chip.
摘要翻译：存储芯片包括存储器阵列和二维感测系统。该阵列包括多个存储单元，其以字线和列逐行的方式连接。当二维读取空间缩小并且在芯片的寿命期间移动时，感测系统在二维读取空间内二维地移动读取点。

2. 发明授权

US08264884B2 Methods, circuits and systems for reading non-volatile memory cells 有权
标题翻译：用于读取非易失性存储单元的方法，电路和系统
公开(公告)号：US08264884B2
公开(公告)日：2012-09-11
申请号：US12310354
申请日：2007-09-16
申请人： Ilan Bloom , Eduardo Maayan
发明人： Ilan Bloom , Eduardo Maayan
IPC分类号： G11C11/34
CPC分类号： G11C16/28 , G11C11/5671 , G11C16/0466 , G11C16/0491
摘要： The present invention includes methods, circuits and systems for reading non-volatile memory (“NVM”) cells, including multi-level NVM cells. According to some embodiments of the present invention, there may be provided a NVM cell threshold voltage detection circuit adapted to detect an approximate threshold voltage associated with a charge storage region of a NVM cell, where the NVM cell may be a single or a multi-charge storage region cell. A decoder circuit may be adapted to decode and/or indicate the logical state of a NVM cell charge storage region by mapping or converting a detected approximate threshold voltage of the charge storage region into a logical state value.
摘要翻译：本发明包括用于读取包括多级NVM单元的非易失性存储器（“NVM”）单元的方法，电路和系统。根据本发明的一些实施例，可以提供一种NVM单元阈值电压检测电路，其适于检测与NVM单元的电荷存储区域相关联的近似阈值电压，其中NVM单元可以是单个或多个，电荷存储区域单元。解码器电路可以通过将检测到的电荷存储区域的近似阈值电压映射或转换为逻辑状态值来解码和/或指示NVM单元电荷存储区域的逻辑状态。

3. 发明授权

US07804126B2 Dense non-volatile memory array and method of fabrication 有权
标题翻译：密集的非易失性存储器阵列和制造方法
公开(公告)号：US07804126B2
公开(公告)日：2010-09-28
申请号：US11489237
申请日：2006-07-18
申请人： Boaz Eitan , Ilan Bloom , Rustom Irani
发明人： Boaz Eitan , Ilan Bloom , Rustom Irani
IPC分类号： H01L29/792
CPC分类号： H01L27/115 , H01L21/0337 , H01L21/0338 , H01L21/28123 , H01L21/31144 , H01L21/32139 , H01L27/0207 , H01L27/11519 , H01L27/11521 , H01L27/11568 , H01L29/792 , H01L29/7923 , H01L2924/0002 , H01L2924/00
摘要： A non-volatile memory array has word lines spaced a sub-F (sub-minimum feature size F) width apart and bit lines generally perpendicular to the word lines. The present invention also includes a method for word-line patterning of a non-volatile memory array which includes generating sub-F word lines from mask generated elements with widths of at least a minimum feature size F.
摘要翻译：非易失性存储器阵列具有间隔开的子F（子最小特征尺寸F）的字线和通常垂直于字线的位线。本发明还包括用于非易失性存储器阵列的字线图案化的方法，其包括从具有至少最小特征尺寸F的宽度的掩模生成的元件生成子F字线。

4. 发明申请

US20090323423A1 METHODS, CIRCUITS AND SYSTEMS FOR READING NON-VOLATILE MEMORY CELLS 有权
标题翻译：用于读取非易失性记忆细胞的方法，电路和系统
公开(公告)号：US20090323423A1
公开(公告)日：2009-12-31
申请号：US12310354
申请日：2007-09-16
申请人： Ilan Bloom , Eduardo Maayan
发明人： Ilan Bloom , Eduardo Maayan
IPC分类号： G11C16/04 , G11C7/10 , G11C8/00
CPC分类号： G11C16/28 , G11C11/5671 , G11C16/0466 , G11C16/0491
摘要： The present invention includes methods, circuits and systems for reading non-volatile memory (“NVM”) cells, including multi-level NVM cells. According to some embodiments of the present invention, there may be provided a NVM cell threshold voltage detection circuit adapted to detect an approximate threshold voltage associated with a charge storage region of a NVM cell, where the NVM cell may be a single or a multi-charge storage region cell. A decoder circuit may be adapted to decode and/or indicate the logical state of a NVM cell charge storage region by mapping or converting a detected approximate threshold voltage of the charge storage region into a logical state value.
摘要翻译：本发明包括用于读取包括多级NVM单元的非易失性存储器（“NVM”）单元的方法，电路和系统。根据本发明的一些实施例，可以提供一种NVM单元阈值电压检测电路，其适于检测与NVM单元的电荷存储区域相关联的近似阈值电压，其中NVM单元可以是单个或多个，电荷存储区域单元。解码器电路可以通过将检测到的电荷存储区域的近似阈值电压映射或转换为逻辑状态值来解码和/或指示NVM单元电荷存储区域的逻辑状态。

5. 发明申请

US20060084219A1 Advanced NROM structure and method of fabrication 审中-公开
标题翻译：先进的NROM结构和制作方法
公开(公告)号：US20060084219A1
公开(公告)日：2006-04-20
申请号：US11247733
申请日：2005-10-11
申请人： Eli Lusky , Assaf Shappir , Ilan Bloom , Boaz Eitan
发明人： Eli Lusky , Assaf Shappir , Ilan Bloom , Boaz Eitan
IPC分类号： H01L21/8238 , H01L21/3205
CPC分类号： H01L27/115 , H01L27/11568 , H01L29/40117 , H01L29/66833
摘要： A method for creating a non-volatile memory array includes generating polysilicon columns on top of an oxide-nitride-oxide (ONO) layer, creating spacing elements on the sides of the polysilicon columns, implanting bit lines into the substrate at least between the spacing elements, depositing oxide filler over the bit lines, depositing a second polysilicon layer over the array and etching the second polysilicon layer into word lines and the polysilicon columns between the word lines.
摘要翻译：用于产生非易失性存储器阵列的方法包括在氧化物 - 氮化物 - 氧化物（ONO）层的顶部产生多晶硅柱，在多晶硅柱的侧面上产生间隔元件，将位线至少在间隔在位线上沉积氧化物填料，在阵列上沉积第二多晶硅层，并将第二多晶硅层蚀刻成字线和字线之间的多晶硅柱。

6. 发明申请

US20060056240A1 Method, circuit and system for erasing one or more non-volatile memory cells 有权
标题翻译：用于擦除一个或多个非易失性存储单元的方法，电路和系统
公开(公告)号：US20060056240A1
公开(公告)日：2006-03-16
申请号：US10537857
申请日：2005-04-03
申请人： Assaf Shappir , Ilan Bloom , Boaz Eitan
发明人： Assaf Shappir , Ilan Bloom , Boaz Eitan
IPC分类号： G11C16/04
CPC分类号： G11C16/14 , G11C16/16
摘要： The present invention is a method circuit and system for erasing one or more non-volatile memory (“NVM”) cells in an NVM array. One or more NVM cells of a memory array may be erased using an erase pulse produced by a controller and/or erase pulse source adapted to induce and/or invoke a substantially stable channel current in the one or more NVM cells during an erasure procedure. The voltage profile of an erase pulse may be predefined or the voltage profile of the erase pulse may be dynamically adjusted based on feedback from a current sensor during an erase procedure
摘要翻译：本发明是用于擦除NVM阵列中的一个或多个非易失性存储器（“NVM”）单元的方法电路和系统。可以使用由控制器产生的擦除脉冲和/或擦除脉冲源来擦除存储器阵列中的一个或多个NVM单元，该擦除脉冲适于在擦除过程期间诱导和/或调用一个或多个NVM单元中的基本上稳定的通道电流。可以预定义擦除脉冲的电压分布，或者可以在擦除过程期间基于来自电流传感器的反馈动态地调整擦除脉冲的电压分布

7. 发明授权

US06627555B2 Method and circuit for minimizing the charging effect during manufacture of semiconductor devices 有权
标题翻译：用于在半导体器件制造期间最小化充电效应的方法和电路
公开(公告)号：US06627555B2
公开(公告)日：2003-09-30
申请号：US09777234
申请日：2001-02-05
申请人： Boaz Eitan , Ilan Bloom
发明人： Boaz Eitan , Ilan Bloom
IPC分类号： H01L2198
CPC分类号： H01L27/0266 , H01L21/3065 , H01L21/31116 , H01L27/0251
摘要： A protection device which is active during the manufacturing process of a semiconductor chip includes a protection transistor and an antenna. The protection transistor is connected between a metal line having devices to be protected electrically connected thereto and a ground supply, where the metal line is connected to devices to be protected. The antenna is formed of the same metal layer as the metal line and controls the operation of the protection transistor during the manufacturing process. The antenna is connected to a gate of the protection transistor. Optically, there is a metal ring around the antenna which is connected to a drain of the protection transistor via the same metal layer as the metal line. During normal operation of the chip, the protection transistor is either active for other purposes or is turned off. Turning off is provided either by a line formed of a second metal layer that is connected between the antenna and ground, or by a reversed biased diode and a parallel capacitor that are connected between the gate of the protection transistor and ground. The present invention includes the method of manufacturing the protection device.
摘要翻译：在半导体芯片的制造过程中有效的保护装置包括保护晶体管和天线。保护晶体管连接在具有被保护电气连接的器件的金属线和接地电源之间，其中金属线连接到待保护的器件。天线由与金属线相同的金属层形成，并且在制造过程中控制保护晶体管的操作。天线连接到保护晶体管的栅极。在光纤上，天线周围有金属环，其通过与金属线相同的金属层连接到保护晶体管的漏极。在芯片的正常操作期间，保护晶体管对于其它目的而言是活动的或被关闭。通过由连接在天线和地之间的第二金属层形成的线或由连接在保护晶体管的栅极和地之间的反向偏置二极管和并联电容器来提供关断。本发明包括制造保护装置的方法。

8. 发明授权

US06490204B2 Programming and erasing methods for a reference cell of an NROM array 失效
标题翻译： NROM阵列的参考单元的编程和擦除方法
公开(公告)号：US06490204B2
公开(公告)日：2002-12-03
申请号：US09827596
申请日：2001-04-05
申请人： Ilan Bloom , Eduardo Maayan , Boaz Eitan
发明人： Ilan Bloom , Eduardo Maayan , Boaz Eitan
IPC分类号： G11C1604
CPC分类号： G11C11/5671 , G11C16/0475 , G11C16/10 , G11C16/14 , G11C16/28 , G11C16/3468 , G11C16/3481 , G11C2211/5634
摘要： A method for programming a reference cell of a memory array includes the steps of programming the reference cell with large programming steps until a threshold voltage level of the reference cell is above an interim target level and programming said reference cell with small programming steps until the threshold voltage level is above a final target level.
摘要翻译：用于对存储器阵列的参考单元进行编程的方法包括以下步骤：用大的编程步骤对参考单元进行编程，直到参考单元的阈值电压高于临时目标电平，并以小编程步骤对所述参考单元进行编程，直到阈值电压水平高于最终目标水平。

9. 发明授权

US07652930B2 Method, circuit and system for erasing one or more non-volatile memory cells 有权
标题翻译：用于擦除一个或多个非易失性存储单元的方法，电路和系统
公开(公告)号：US07652930B2
公开(公告)日：2010-01-26
申请号：US10537857
申请日：2005-04-03
申请人： Assaf Shappir , Ilan Bloom , Boaz Eitan
发明人： Assaf Shappir , Ilan Bloom , Boaz Eitan
IPC分类号： G11C11/34
CPC分类号： G11C16/14 , G11C16/16
摘要： The present invention is a method circuit and system for erasing one or more non-volatile memory (“NVM”) cells in an NVM array. One or more NVM cells of a memory array may be erased using an erase pulse produced by a controller and/or erase pulse source adapted to induce and/or invoke a substantially stable channel current in the one or more NVM cells during an erasure procedure. The voltage profile of an erase pulse may be predefined or the voltage profile of the erase pulse may be dynamically adjusted based on feedback from a current sensor during an erase procedure.
摘要翻译：本发明是用于擦除NVM阵列中的一个或多个非易失性存储器（“NVM”）单元的方法电路和系统。可以使用由控制器产生的擦除脉冲和/或擦除脉冲源来擦除存储器阵列中的一个或多个NVM单元，该擦除脉冲适于在擦除过程期间诱导和/或调用一个或多个NVM单元中的基本上稳定的通道电流。可以预定义擦除脉冲的电压分布，或者可以在擦除过程期间基于来自电流传感器的反馈动态地调整擦除脉冲的电压分布。

10. 发明授权

US07638835B2 Double density NROM with nitride strips (DDNS) 有权
标题翻译：双重密度NROM与氮化物条（DDNS）
公开(公告)号：US07638835B2
公开(公告)日：2009-12-29
申请号：US11646430
申请日：2006-12-28
申请人： Rustom Irani , Boaz Eitan , Ilan Bloom , Assaf Shappir
发明人： Rustom Irani , Boaz Eitan , Ilan Bloom , Assaf Shappir
IPC分类号： H01L29/792
CPC分类号： H01L27/11568 , H01L21/28282 , H01L27/105 , H01L27/11573
摘要： An NVM cell such as an NROM cell is formed using a portion of one ONO stack and an adjacent portion of a neighboring NROM stack. A gate structure is formed between (and atop) the two ONO portions, or “strips” (or “stripes”). This provides having two physically separated charge storage regions (nitride “strips”, or “stripes”) in each memory cell.
摘要翻译：使用一个ONO堆栈的一部分和相邻NROM堆栈的相邻部分来形成诸如NROM单元的NVM单元。在（和顶部）两个ONO部分或“条带”（或“条纹”）之间形成栅极结构。这提供了在每个存储单元中具有两个物理分离的电荷存储区域（氮化物“条带”或“条纹”）。

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