专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明授权

US08796811B2 Hybrid substrateless device with enhanced tuning efficiency 有权
标题翻译：具有增强调谐效率的混合无基底器件
公开(公告)号：US08796811B2
公开(公告)日：2014-08-05
申请号：US13205745
申请日：2011-08-09
申请人： Ivan Shubin , Ashok V. Krishnamoorthy , John E. Cunningham
发明人： Ivan Shubin , Ashok V. Krishnamoorthy , John E. Cunningham
IPC分类号： H01L27/12 , H01L21/50 , G02B6/10 , H01L27/146 , H01L27/148
CPC分类号： H01L27/1465 , H01L21/187 , H01L27/14661 , H01L27/1467 , H01L27/14881 , H01L2224/16225 , H01L2224/32225 , H01L2224/73204 , H01L2224/73253 , H01L2924/00
摘要： In a hybrid integrated module, a semiconductor die is mechanically coupled face-to-face to an integrated device in which the substrate has been removed. For example, the integrated circuit may include an optical device fabricated on a silicon-on-insulator (SOI) wafer in which the backside silicon handler has been completely removed, thereby facilitating improved device performance and highly efficient thermal tuning of the operating wavelength of the optical device. Moreover, the semiconductor die may be a VLSI chip that provides power, and serves as a mechanical handler and/or an electrical driver. The thermal tuning efficiency of the substrateless optical device may be enhanced by over 100× relative to an optical device with an intact substrate, and by 5× relative to an optical device in which the substrate has only been removed in proximity to the optical device.
摘要翻译：在混合集成模块中，将半导体管芯面对面地机械耦合到已经去除衬底的集成器件。例如，集成电路可以包括制造在绝缘体上硅（SOI）晶片上的光学器件，其中背面硅处理器已经被完全去除，从而有助于改进器件性能和高效率地调谐工作波长光学装置。此外，半导体管芯可以是提供电力并用作机械处理器和/或电驱动器的VLSI芯片。相对于具有完整衬底的光学器件，无基底光学器件的热调谐效率可以提高超过100倍，并且相对于其中衬底仅在光学器件附近被去除的光学器件可以提高5倍。

2. 发明授权

US08742576B2 Maintaining alignment in a multi-chip module using a compressible structure 有权
标题翻译：使用可压缩结构在多芯片模块中保持对准
公开(公告)号：US08742576B2
公开(公告)日：2014-06-03
申请号：US13397593
申请日：2012-02-15
申请人： Hiren D. Thacker , Hyung Suk Yang , Ivan Shubin , John E. Cunningham
发明人： Hiren D. Thacker , Hyung Suk Yang , Ivan Shubin , John E. Cunningham
IPC分类号： H01L23/48 , H01L23/498 , H01L21/50
CPC分类号： H01L25/0652 , H01L23/48 , H01L24/16 , H01L24/72 , H01L24/73 , H01L24/90 , H01L24/91 , H01L25/50 , H01L2224/131 , H01L2224/16227 , H01L2224/73201 , H01L2224/73251 , H01L2224/81138 , H01L2224/81815 , H01L2224/9211 , H01L2225/06517 , H01L2225/06527 , H01L2225/06531 , H01L2225/06562 , H01L2225/06593 , H01L2924/15153 , H01L2924/157 , H01L2924/15787 , H01L2924/15788 , H01L2924/1579 , H01L2924/3511 , H01L2924/37001 , H01L2924/00 , H01L2924/014 , H01L2224/16 , H01L2224/72 , H01L2224/81 , H01L2224/90 , H01L2924/00014 , H01L2924/00012
摘要： An MCM includes a two-dimensional array of facing chips, including island chips and bridge chips that communicate with each other using overlapping connectors. In order to maintain the relative vertical spacing of these connectors, compressible structures are in cavities in a substrate, which house the bridge chips, provide a compressive force on back surfaces of the bridge chips. These compressible structures include a compliant material with shape and volume compression. In this way, the MCM may ensure that facing surfaces of the island chips and the bridge chips, as well as connectors on these surfaces, are approximately coplanar without bending the bridge chips.
摘要翻译： MCM包括面向芯片的二维阵列，包括使用重叠连接器彼此通信的岛芯片和桥芯片。为了保持这些连接器的相对垂直间隔，可压缩结构位于衬底中的空腔中，其容纳桥芯片，在桥芯片的后表面上提供压缩力。这些可压缩结构包括具有形状和体积压缩的柔性材料。以这种方式，MCM可以确保岛芯片和桥芯片的面对表面以及这些表面上的连接器在不弯曲桥接芯片的情况下大致共面。

3. 发明授权

US08600201B2 Optical device with enhanced mechanical strength 有权
标题翻译：具有增强机械强度的光学装置
公开(公告)号：US08600201B2
公开(公告)日：2013-12-03
申请号：US13032561
申请日：2011-02-22
申请人： Hiren D. Thacker , Ivan Shubin , John E. Cunningham
发明人： Hiren D. Thacker , Ivan Shubin , John E. Cunningham
IPC分类号： G02B6/12
CPC分类号： G02B6/12007
摘要： An optical device implemented on a substrate (such as silicon) is described. This optical device includes a wavelength-sensitive optical component with a high thermal resistance to a surrounding external environment and a low thermal resistance to a localized thermal-tuning mechanism (such as a heater), which modifies a temperature of the wavelength-sensitive optical component, thereby specifying an operating wavelength of the wavelength-sensitive optical component. In particular, the thermal resistance associated with a thermal dissipation path from the thermal-tuning mechanism to the external environment via the substrate is increased by removing a portion of the substrate to create a gap that is proximate to the thermal-tuning mechanism and the wavelength-sensitive optical component. Furthermore, the optical device includes a binder material mechanically coupled to the substrate and proximate to the gap, thereby maintaining a mechanical strength of the optical device.
摘要翻译：描述了在衬底（例如硅）上实现的光学器件。该光学器件包括对周围的外部环境具有高热阻的波长敏感的光学部件和对局部的热调谐机构（例如加热器）的低热阻，其改变了波长敏感光学部件的温度从而指定波长敏感光学部件的工作波长。特别地，通过去除衬底的一部分以产生靠近热调谐机构的间隙和波长的距离，与通过衬底从热调谐机构到外部环境的散热路径相关联的热阻增加敏感光学部件。此外，光学装置包括机械耦合到基板并且靠近间隙的粘合剂材料，从而保持光学装置的机械强度。

4. 发明申请

US20130015578A1 INTERCONNECTION AND ASSEMBLY OF THREE-DIMENSIONAL CHIP PACKAGES 有权
标题翻译：三维芯片包装的互连和组装
公开(公告)号：US20130015578A1
公开(公告)日：2013-01-17
申请号：US13182220
申请日：2011-07-13
申请人： Hiren D. Thacker , John E. Cunningham , Ivan Shubin , Ashok V. Krishnamoorthy
发明人： Hiren D. Thacker , John E. Cunningham , Ivan Shubin , Ashok V. Krishnamoorthy
IPC分类号： H01L23/498 , H01L21/50 , H01L23/48
CPC分类号： H01L25/0657 , H01L24/13 , H01L24/16 , H01L24/32 , H01L24/73 , H01L24/81 , H01L25/18 , H01L25/50 , H01L2224/13005 , H01L2224/13017 , H01L2224/13027 , H01L2224/13109 , H01L2224/13111 , H01L2224/13147 , H01L2224/14181 , H01L2224/14183 , H01L2224/16105 , H01L2224/16108 , H01L2224/16111 , H01L2224/16225 , H01L2224/16227 , H01L2224/32145 , H01L2224/481 , H01L2224/48227 , H01L2224/73103 , H01L2224/81138 , H01L2224/81899 , H01L2225/06551 , H01L2225/06555 , H01L2225/06593 , H01L2924/01327 , H01L2924/07802 , H01L2924/12042 , H01L2924/01082 , H01L2924/00014 , H01L2924/01047 , H01L2924/01029 , H01L2924/00012 , H01L2924/00
摘要： In a chip package, semiconductor dies in a vertical stack of semiconductor dies or chips (which is referred to as a ‘plank stack’) are aligned by positive features that are mechanically coupled to negative features recessed below the surfaces of adjacent semiconductor dies. Moreover, the chip package includes an interposer plate at approximately a right angle to the plank stack, which is electrically coupled to the semiconductor dies along an edge of the plank stack. In particular, electrical pads proximate to a surface of the interposer plate (which are along a stacking direction of the plank stack) are electrically coupled to pads that are proximate to edges of the semiconductor dies by an intervening conductive material, such as solder balls or spring connectors. Note that the chip package may facilitate high-bandwidth communication of signals between the semiconductor dies and the interposer plate.
摘要翻译：在芯片封装中，半导体管芯或芯片（被称为板堆叠）的垂直堆叠中的半导体管芯通过机械耦合到相邻半导体管芯的表面下方的负特性的正特性对准。此外，芯片封装包括与板堆叠大致成直角的插入板，其沿着板堆的边缘电耦合到半导体管芯。特别地，靠近插入板的表面（沿着板堆叠的堆叠方向）的电焊盘通过中间导电材料（例如焊料球）电耦合到靠近半导体管芯的边缘的焊盘，弹簧连接器。注意，芯片封装可以促进半导体管芯和插入板之间的信号的高带宽通信。

5. 发明申请

US20130003310A1 CHIP PACKAGE TO SUPPORT HIGH-FREQUENCY PROCESSORS 有权
标题翻译：芯片包支持高频处理器
公开(公告)号：US20130003310A1
公开(公告)日：2013-01-03
申请号：US13171072
申请日：2011-06-28
申请人： Kannan Raj , Ivan Shubin , John E. Cunningham
发明人： Kannan Raj , Ivan Shubin , John E. Cunningham
IPC分类号： H05K7/00 , H05K7/20
CPC分类号： H05K7/1092 , H01L23/5384 , H01L25/18 , H01L2224/16225 , H01L2224/73253 , H01L2924/10253 , H01L2924/15311 , H01L2924/00
摘要： A chip package includes a processor, an interposer chip and a voltage regulator module (VRM). The interposer chip is electrically coupled to the processor by first electrical connectors proximate to a surface of the interposer chip. Moreover, the interposer chip includes second electrical connectors proximate to another surface of the interposer chip, which are electrically coupled to the first electrical connectors by through-substrate vias (TSVs) in the interposer chip. Note that the second electrical connectors can electrically couple the interposer chip to a circuit board. Furthermore, the VRM is electrically coupled to the processor by the interposer chip, and is proximate to the processor in the chip package, thereby reducing voltage droop. For example, the VRM may be electrically coupled to the surface of the interposer chip, and may be adjacent to the processor. Alternatively, the VRM may be electrically coupled to the other surface of the interposer chip.
摘要翻译：芯片封装包括处理器，插入器芯片和电压调节器模块（VRM）。插入器芯片通过靠近插入器芯片的表面的第一电连接器电耦合到处理器。此外，插入器芯片包括靠近插入器芯片的另一表面的第二电连接器，其通过插入器芯片中的贯穿衬底通孔（TSV）电耦合到第一电连接器。注意，第二电连接器可以将插入器芯片电连接到电路板。此外，VRM通过插入器芯片电耦合到处理器，并且靠近芯片封装中的处理器，从而降低电压下降。例如，VRM可以电耦合到插入器芯片的表面，并且可以与处理器相邻。或者，VRM可以电耦合到插入器芯片的另一表面。

6. 发明申请

US20120266464A1 MULTI-CHIP MODULE WITH MULTI-LEVEL INTERPOSER 有权
标题翻译：具有多级插补器的多芯片模块
公开(公告)号：US20120266464A1
公开(公告)日：2012-10-25
申请号：US13517591
申请日：2012-06-13
申请人： Eugene M. Chow , John E. Cunningham , James G. Mitchell , Ivan Shubin
发明人： Eugene M. Chow , John E. Cunningham , James G. Mitchell , Ivan Shubin
IPC分类号： H01K3/10
CPC分类号： H01L23/49811 , H01L21/4853 , H01L21/6835 , H01L23/13 , H01L23/147 , H01L23/15 , H01L23/49827 , H01L23/544 , H01L24/13 , H01L24/16 , H01L24/81 , H01L25/0652 , H01L2221/68309 , H01L2221/68345 , H01L2223/54426 , H01L2223/54473 , H01L2224/13 , H01L2224/13016 , H01L2224/131 , H01L2224/136 , H01L2224/16237 , H01L2224/81005 , H01L2224/81007 , H01L2224/81136 , H01L2224/81138 , H01L2224/81141 , H01L2224/81191 , H01L2224/81192 , H01L2224/81801 , H01L2224/81901 , H01L2924/0001 , H01L2924/01006 , H01L2924/01033 , H01L2924/01075 , H01L2924/01327 , H01L2924/014 , H01L2924/12042 , H01L2924/14 , H01L2924/15156 , H01L2924/15787 , Y10T29/49165 , Y10T29/49204 , Y10T29/49895 , Y10T29/49947 , H01L2924/00012 , H01L2224/13099 , H01L2924/00
摘要： A multi-level interposer plate and a multi-chip module (MCM) that includes the multi-level interposer plate are described. First surfaces and second surfaces in different regions of the multi-level interposer plate have associated, different thicknesses. Moreover, first micro-spring connectors and second micro-spring connectors are respectively disposed on the first surfaces and the second surfaces. In the MCM, a given one of the first surfaces of the multi-level interposer plate faces a bridge chip in a first layer in an array of chips in the MCM so that first connectors, disposed on the bridge chip, mechanically and electrically couple to the first micro-spring connectors. Similarly, a given one of the second surfaces of the multi-level interposer plate faces an island chip in a second layer in the array of chips so that second connectors, disposed on the island chip, mechanically and electrically couple to the second micro-spring connectors.
摘要翻译：描述了包括多层插入板的多层插入板和多芯片模块（MCM）。多层插入板的不同区域中的第一表面和第二表面具有相关联的不同厚度。此外，第一微弹簧连接器和第二微弹簧连接器分别设置在第一表面和第二表面上。在MCM中，多级插入板的给定的一个第一表面面向MCM中芯片阵列的第一层中的桥式芯片，使得设置在桥式芯片上的第一连接器机械地和电耦合到第一个微型弹簧连接器。类似地，多层插入板的给定的一个第二表面面向芯片阵列中的第二层中的岛状芯片，使得设置在岛状芯片上的第二连接器机械地和电耦合到第二微型弹簧连接器

7. 发明申请

US20120213467A1 OPTICAL DEVICE WITH ENHANCED MECHANICAL STRENGTH 有权
标题翻译：具有增强机械强度的光学装置
公开(公告)号：US20120213467A1
公开(公告)日：2012-08-23
申请号：US13032561
申请日：2011-02-22
申请人： Hiren D. Thacker , Ivan Shubin , John E. Cunningham
发明人： Hiren D. Thacker , Ivan Shubin , John E. Cunningham
IPC分类号： G02B6/12 , B05D5/00
CPC分类号： G02B6/12007
摘要： An optical device implemented on a substrate (such as silicon) is described. This optical device includes a wavelength-sensitive optical component with a high thermal resistance to a surrounding external environment and a low thermal resistance to a localized thermal-tuning mechanism (such as a heater), which modifies a temperature of the wavelength-sensitive optical component, thereby specifying an operating wavelength of the wavelength-sensitive optical component. In particular, the thermal resistance associated with a thermal dissipation path from the thermal-tuning mechanism to the external environment via the substrate is increased by removing a portion of the substrate to create a gap that is proximate to the thermal-tuning mechanism and the wavelength-sensitive optical component. Furthermore, the optical device includes a binder material mechanically coupled to the substrate and proximate to the gap, thereby maintaining a mechanical strength of the optical device.
摘要翻译：描述了在衬底（例如硅）上实现的光学器件。该光学器件包括对周围的外部环境具有高热阻的波长敏感的光学部件和对局部的热调谐机构（例如加热器）的低热阻，其改变了波长敏感光学部件的温度从而指定波长敏感光学部件的工作波长。特别地，通过去除衬底的一部分以产生靠近热调谐机构的间隙和波长的距离，与通过衬底从热调谐机构到外部环境的散热路径相关联的热阻增加敏感光学部件。此外，光学装置包括机械耦合到基板并且靠近间隙的粘合剂材料，从而保持光学装置的机械强度。

8. 发明授权

US08014636B2 Electrical contacts on top of waveguide structures for efficient optical modulation in silicon photonic devices 有权
标题翻译：波导结构顶部的电触点用于硅光子器件中的有效光调制
公开(公告)号：US08014636B2
公开(公告)日：2011-09-06
申请号：US12389608
申请日：2009-02-20
申请人： Ivan Shubin , Guoliang Li , John E. Cunningham , Ashok Krishnamoorthy , Xuezhe Zheng
发明人： Ivan Shubin , Guoliang Li , John E. Cunningham , Ashok Krishnamoorthy , Xuezhe Zheng
IPC分类号： G02F1/035 , H01L29/06 , H04B10/04
CPC分类号： G02F1/025 , B82Y20/00 , G02F1/01708 , G02F2001/0157 , G02F2201/12 , Y10S977/742
摘要： A phase modulation waveguide structure includes one of a semiconductor and a semiconductor-on-insulator substrate, a doped semiconductor layer formed over the one of a semiconductor and a semiconductor-on-insulator substrate, the doped semiconductor portion including a waveguide rib protruding from a surface thereof not in contact with the one of a semiconductor and a semiconductor-on-insulator substrate, and an electrical contact on top of the waveguide rib. The electrical contact is formed of a material with an optical refractive index close to that of a surrounding oxide layer that surrounds the waveguide rib and the electrical contact and lower than the optical refractive index of the doped semiconductor layer. During propagation of an optical mode within the waveguide structure, the electrical contact isolates the optical mode between the doped semiconductor layer and a metal electrode contact on top of the electrical contact.
摘要翻译：相位调制波导结构包括半导体和绝缘体上半导体衬底之一，在半导体和绝缘体上半导体衬底之上形成的掺杂半导体层，掺杂半导体部分包括从其表面不与半导体和绝缘体上半导体衬底之一接触，并且在波导肋的顶部上的电接触。电接触由光学折射率接近包围波导肋和电接触并且低于掺杂半导体层的光折射率的周围氧化物层的材料形成。在波导结构内的光学模式的传播期间，电接触将掺杂半导体层和电接触顶部上的金属电极接触之间的光学模式隔离开。

9. 发明授权

US09281268B2 Method for fabricating multi-chip module with multi-level interposer 有权
标题翻译：用多层插入器制造多芯片模块的方法
公开(公告)号：US09281268B2
公开(公告)日：2016-03-08
申请号：US13517591
申请日：2012-06-13
申请人： Eugene M. Chow , John E. Cunningham , James G. Mitchell , Ivan Shubin
发明人： Eugene M. Chow , John E. Cunningham , James G. Mitchell , Ivan Shubin
IPC分类号： H05K3/20 , H01L23/498 , H01L21/48 , H01L21/683 , H01L23/13 , H01L23/14 , H01L23/544 , H01L23/00 , H01L25/065 , H01L23/15
CPC分类号： H01L23/49811 , H01L21/4853 , H01L21/6835 , H01L23/13 , H01L23/147 , H01L23/15 , H01L23/49827 , H01L23/544 , H01L24/13 , H01L24/16 , H01L24/81 , H01L25/0652 , H01L2221/68309 , H01L2221/68345 , H01L2223/54426 , H01L2223/54473 , H01L2224/13 , H01L2224/13016 , H01L2224/131 , H01L2224/136 , H01L2224/16237 , H01L2224/81005 , H01L2224/81007 , H01L2224/81136 , H01L2224/81138 , H01L2224/81141 , H01L2224/81191 , H01L2224/81192 , H01L2224/81801 , H01L2224/81901 , H01L2924/0001 , H01L2924/01006 , H01L2924/01033 , H01L2924/01075 , H01L2924/01327 , H01L2924/014 , H01L2924/12042 , H01L2924/14 , H01L2924/15156 , H01L2924/15787 , Y10T29/49165 , Y10T29/49204 , Y10T29/49895 , Y10T29/49947 , H01L2924/00012 , H01L2224/13099 , H01L2924/00
摘要： A multi-level interposer plate and a multi-chip module (MCM) that includes the multi-level interposer plate are described. First surfaces and second surfaces in different regions of the multi-level interposer plate have associated, different thicknesses. Moreover, first micro-spring connectors and second micro-spring connectors are respectively disposed on the first surfaces and the second surfaces. In the MCM, a given one of the first surfaces of the multi-level interposer plate faces a bridge chip in a first layer in an array of chips in the MCM so that first connectors, disposed on the bridge chip, mechanically and electrically couple to the first micro-spring connectors. Similarly, a given one of the second surfaces of the multi-level interposer plate faces an island chip in a second layer in the array of chips so that second connectors, disposed on the island chip, mechanically and electrically couple to the second micro-spring connectors.
摘要翻译：描述了包括多层插入板的多层插入板和多芯片模块（MCM）。多层插入板的不同区域中的第一表面和第二表面具有相关联的不同厚度。此外，第一微弹簧连接器和第二微弹簧连接器分别设置在第一表面和第二表面上。在MCM中，多级插入板的给定的一个第一表面面向MCM中芯片阵列的第一层中的桥式芯片，使得设置在桥式芯片上的第一连接器机械地和电耦合到第一个微型弹簧连接器。类似地，多层插入板的给定的一个第二表面面向芯片阵列中的第二层中的岛状芯片，使得设置在岛状芯片上的第二连接器机械地和电耦合到第二微型弹簧连接器

10. 发明授权

US09164231B2 Ultra-compact photodetector on an optical waveguide 有权
标题翻译：在光波导上的超小型光电探测器
公开(公告)号：US09164231B2
公开(公告)日：2015-10-20
申请号：US13205484
申请日：2011-08-08
申请人： Ivan Shubin , John E. Cunningham
发明人： Ivan Shubin , John E. Cunningham
IPC分类号： G02B6/12 , G02B6/42 , G02B6/122
CPC分类号： G02B6/12004 , G02B6/1228 , G02B6/4214
摘要： An integrated circuit is described. This integrated circuit includes an optical waveguide defined in a semiconductor layer, and an optical detector disposed on top of the optical waveguide. Moreover, the optical waveguide has an end with a reflecting facet. For example, the reflective facet may be defined using an anisotropic etch of the semiconductor layer. This reflecting facet reflects light propagating in a plane of the optical waveguide out of the plane into the optical detector, thereby providing a photodetector with high optical responsivity, including an extremely low dark current (and, thus, high photosensitivity) and an extremely small capacitance (and, thus, high electrical bandwidth).
摘要翻译：描述了集成电路。该集成电路包括限定在半导体层中的光波导和设置在光波导顶部的光学检测器。此外，光波导具有具有反射面的端部。例如，反射小面可以使用半导体层的各向异性蚀刻来定义。该反射面反射在平面内的光波导的平面内传播的光进入光检测器，从而提供具有高光学响应性的光电检测器，其包括极低的暗电流（并且因此具有高的光敏性）和极小的电容（并因此具有高的电气带宽）。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式