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1. 发明授权

US08975568B2 Image sensors having variable voltage-current characteristics and methods of operating the same 有权
公开(公告)号：US08975568B2
公开(公告)日：2015-03-10
申请号：US12805723
申请日：2010-08-17
申请人： Ho-jung Kim , U-in Chung , Jai-kwang Shin , Sun-il Kim , I-hun Song , Chang-jung Kim , Sang-hun Jeon
发明人： Ho-jung Kim , U-in Chung , Jai-kwang Shin , Sun-il Kim , I-hun Song , Chang-jung Kim , Sang-hun Jeon
IPC分类号： H01J27/00 , H04N9/04 , H04N5/3745 , H01L27/146
摘要： Image sensors and methods of operating the same. An image sensor includes a pixel array including a plurality of pixels. Each of the plurality of pixels includes a photo sensor, the voltage-current characteristics of which vary according to energy of incident light, and that generates a sense current determined by the energy of the incident light; a reset unit that is activated to generate a reference current, according to a reset signal for resetting at least one of the plurality of pixels; and a conversion unit that converts the sense current and the reference current into a sense voltage and a reference voltage, respectively.

2. 发明授权

US08816396B2 E-mode high electron mobility transistor and method of manufacturing the same 有权
标题翻译： E型高电子迁移率晶体管及其制造方法
公开(公告)号：US08816396B2
公开(公告)日：2014-08-26
申请号：US13222322
申请日：2011-08-31
申请人： In-jun Hwang , Jong-seob Kim , Hyuk-soon Choi , Ki-ha Hong , Jai-kwang Shin , Jae-joon Oh
发明人： In-jun Hwang , Jong-seob Kim , Hyuk-soon Choi , Ki-ha Hong , Jai-kwang Shin , Jae-joon Oh
IPC分类号： H01L29/778
CPC分类号： H01L29/7786 , H01L29/2003 , H01L29/201 , H01L29/66462
摘要： According to an example embodiment, a high electron mobility transistor (HEMT) includes a substrate, a buffer layer on the substrate, a channel layer on the buffer layer, and a barrier structure on the channel layer. The buffer layer includes a 2-dimensional electron gas (2DEG). A polarization of the barrier structure varies in a region corresponding to a gate electrode. The HEMT further includes and the gate electrode, a source electrode, and a drain electrode on the barrier structure.
摘要翻译：根据示例性实施例，高电子迁移率晶体管（HEMT）包括衬底，衬底上的缓冲层，缓冲层上的沟道层以及沟道层上的势垒结构。缓冲层包括二维电子气（2DEG）。势垒结构的极化在对应于栅电极的区域中变化。 HEMT还包括栅电极，源电极和屏障结构上的漏电极。

3. 发明授权

US08796737B2 High electron mobility transistors and methods of manufacturing the same 有权
标题翻译：高电子迁移率晶体管及其制造方法
公开(公告)号：US08796737B2
公开(公告)日：2014-08-05
申请号：US13307769
申请日：2011-11-30
申请人： In-jun Hwang , Jai-kwang Shin , Jae-joon Oh , Jong-bong Ha , Hyuk-soon Choi , Ki-ha Hong
发明人： In-jun Hwang , Jai-kwang Shin , Jae-joon Oh , Jong-bong Ha , Hyuk-soon Choi , Ki-ha Hong
IPC分类号： H01L29/66 , H01L21/338
CPC分类号： H01L29/7787 , H01L29/1066 , H01L29/2003 , H01L29/205 , H01L29/4236 , H01L29/432 , H01L29/66462
摘要： High electron mobility transistors (HEMTs) and methods of manufacturing the same. A HEMT may include a channel layer and a channel supply layer, and the channel supply layer may be a multilayer structure. The channel supply layer may include an etch stop layer and an upper layer on the etch stop layer. A recess region may be in the upper layer. The recess region may be a region recessed to an interface between the upper layer and the etch stop layer. A gate electrode may be on the recess region.
摘要翻译：高电子迁移率晶体管（HEMT）及其制造方法。 HEMT可以包括沟道层和沟道供应层，并且沟道供应层可以是多层结构。沟道供应层可以包括蚀刻停止层和蚀刻停止层上的上层。凹部区域可以在上层。凹陷区域可以是凹陷到上层和蚀刻停止层之间的界面的区域。栅电极可以在凹陷区域上。

4. 发明申请

US20130200427A1 TRANSISTORS AND METHODS OF MANUFACTURING THE SAME 有权
标题翻译：晶体管及其制造方法
公开(公告)号：US20130200427A1
公开(公告)日：2013-08-08
申请号：US13550032
申请日：2012-07-16
申请人： Hyung-su Jeong , Jai-kwang Shin , Nam-young Lee , Ji-hoon Lee , Min-kwon Cho , Yong-cheol Choi , Hyuk-soon Choi
发明人： Hyung-su Jeong , Jai-kwang Shin , Nam-young Lee , Ji-hoon Lee , Min-kwon Cho , Yong-cheol Choi , Hyuk-soon Choi
IPC分类号： H01L29/739 , H01L21/331
CPC分类号： H01L29/36 , H01L29/6634 , H01L29/7397
摘要： A transistor includes a device portion and a collector layer. The device portion is in a first side of a semiconductor substrate, and includes a gate and an emitter. The collector layer is on a second side of the semiconductor substrate, which is opposite to the first side. The collector layer is an impurity-doped epitaxial layer and has a doping profile with a non-normal distribution.
摘要翻译：晶体管包括器件部分和集电极层。器件部分位于半导体衬底的第一侧，并且包括栅极和发射极。集电极层位于半导体衬底的与第一侧相对的第二侧上。集电极层是杂质掺杂的外延层，并具有非正态分布的掺杂分布。

5. 发明授权

US08497703B2 Reconfigurable logic devices 有权
标题翻译：可重构逻辑器件
公开(公告)号：US08497703B2
公开(公告)日：2013-07-30
申请号：US13080938
申请日：2011-04-06
申请人： Ho-jung Kim , Jai-kwang Shin , Hyun-sik Choi
发明人： Ho-jung Kim , Jai-kwang Shin , Hyun-sik Choi
IPC分类号： G06F7/38
CPC分类号： H03K19/17752 , H03K19/17756
摘要： Example embodiments provide a reconfigurable logic device including at least two logic blocks having a first logic block and a second logic block, a global wire group including at least a plurality of first global wires connected to the first logic block and a plurality of second global wires connected to the second logic block, and a global controller including a plurality of first nonvolatile memory devices associated with at least one first global wire and one second global wire, the global controller configured to selectively couple the pluralities of first and second global wires based on first data stored in the associated first nonvolatile memory devices.
摘要翻译：示例性实施例提供了一种可重新配置逻辑设备，其包括具有第一逻辑块和第二逻辑块的至少两个逻辑块，包括连接到第一逻辑块的至少多个第一全局线的全局线组和多个第二全局线连接到第二逻辑块，以及全局控制器，其包括与至少一个第一全局线和一个第二全局线相关联的多个第一非易失性存储器件，所述全局控制器被配置为基于多个第一和第二全局线，存储在相关联的第一非易失性存储器件中的第一数据。

6. 发明授权

US08385098B2 Ferroelectric memory devices and operating methods thereof 有权
标题翻译：铁电存储器件及其操作方法
公开(公告)号：US08385098B2
公开(公告)日：2013-02-26
申请号：US12923131
申请日：2010-09-03
申请人： Ki-ha Hong , Jeong-seob Kim , Jai-kwang Shin
发明人： Ki-ha Hong , Jeong-seob Kim , Jai-kwang Shin
IPC分类号： G11C11/22
CPC分类号： G11C11/22 , G11C11/223 , H01L21/28291 , H01L27/11597 , H01L27/1203 , H01L29/1606 , H01L29/78391
摘要： A ferroelectric memory device having a NAND array of a plurality of ferroelectric memory cells includes: a fully depleted channel layer; a gate electrode layer; and a ferroelectric layer located between the channel layer and the gate electrode layer. The data of the plurality of ferroelectric memory cells is erased by applying a first erase voltage to a bit line and a common source line and applying a second erase voltage to a string selection line and a ground selection line.
摘要翻译：具有多个铁电存储单元的NAND阵列的铁电存储器件包括：完全耗尽的沟道层; 栅电极层; 以及位于沟道层和栅电极层之间的铁电层。通过对位线和公共源极线施加第一擦除电压并向串选择线和地选择线施加第二擦除电压来擦除多个铁电存储单元的数据。

7. 发明授权

US08269293B2 Spin transistor and method of operating the same 有权
标题翻译：旋转晶体管及其操作方法
公开(公告)号：US08269293B2
公开(公告)日：2012-09-18
申请号：US12742221
申请日：2008-11-04
申请人： Ki-Ha Hong , Sung-Hoon Lee , Jong-Seob Kim , Jai-Kwang Shin
发明人： Ki-Ha Hong , Sung-Hoon Lee , Jong-Seob Kim , Jai-Kwang Shin
IPC分类号： H01L29/82
CPC分类号： H01L29/66984 , B82Y25/00 , H01F1/401 , H01F1/404 , H01F10/1933 , H01F10/1936 , H01F10/3254 , H01F10/3295 , H01L29/82
摘要： Disclosed are a spin transistor and a method of operating the spin transistor. The disclosed spin transistor includes a channel formed of a magnetic material selectively passing a spin-polarized electron having a specific direction, a source formed of a magnetic material, a drain, and a gate electrode. When a predetermined voltage is applied to the gate electrode, the channel selectively passes a spin-polarized electron having a specific direction and thus, the spin transistor is selectively turned on.
摘要翻译：公开了自旋晶体管和操作自旋晶体管的方法。所公开的自旋晶体管包括由选择性地通过具有特定方向的自旋极化电子的磁性材料形成的沟道，由磁性材料形成的源极，漏极和栅电极。当预定电压施加到栅电极时，沟道选择性地通过具有特定方向的自旋极化电子，因此自旋晶体管选择性地导通。

8. 发明授权

US08263449B2 Method of manufacturing high electron mobility transistor 有权
标题翻译：制造高电子迁移率晶体管的方法
公开(公告)号：US08263449B2
公开(公告)日：2012-09-11
申请号：US13017361
申请日：2011-01-31
申请人： Ki-ha Hong , U-In Chung , Jai-kwang Shin , Jae-joon Oh , Jong-seob Kim , Hyuk-soon Choi , In-jun Hwang
发明人： Ki-ha Hong , U-In Chung , Jai-kwang Shin , Jae-joon Oh , Jong-seob Kim , Hyuk-soon Choi , In-jun Hwang
IPC分类号： H01L21/338
CPC分类号： H01L29/402 , H01L29/0891 , H01L29/66462 , H01L29/7786
摘要： A method of manufacturing a High Electron Mobility Transistor (HEMT) may include forming first and second material layers having different lattice constants on a substrate, forming a source, a drain, and a gate on the second material layer, and changing the second material layer between the gate and the drain into a different material layer, or changing a thickness of the second material layer, or forming a p-type semiconductor layer on the second material layer. The change in the second material layer may occur in an entire region of the second material layer between the gate and the drain, or only in a partial region of the second material layer adjacent to the gate. The p-type semiconductor layer may be formed on an entire top surface of the second material layer between the gate and the drain, or only on a partial region of the top surface adjacent to the gate.
摘要翻译：制造高电子迁移率晶体管（HEMT）的方法可以包括在衬底上形成具有不同晶格常数的第一和第二材料层，在第二材料层上形成源极，漏极和栅极，以及改变第二材料层在栅极和漏极之间形成不同的材料层，或改变第二材料层的厚度，或在第二材料层上形成p型半导体层。第二材料层的变化可以在栅极和漏极之间的第二材料层的整个区域中发生，或者仅在与栅极相邻的第二材料层的部分区域中发生。 p型半导体层可以形成在栅极和漏极之间的第二材料层的整个顶表面上，或者仅形成在与栅极相邻的顶表面的部分区域上。

9. 发明授权

US08203863B2 Nonvolatile memory cells and nonvolatile memory devices including the same 有权
标题翻译：非易失性存储器单元和包括其的非易失性存储器件
公开(公告)号：US08203863B2
公开(公告)日：2012-06-19
申请号：US12801533
申请日：2010-06-14
申请人： Ho-jung Kim , In-kyeong Yoo , Jai-kwang Shin , Chang-jung Kim , Myoung-jae Lee , Ki-ha Hong
发明人： Ho-jung Kim , In-kyeong Yoo , Jai-kwang Shin , Chang-jung Kim , Myoung-jae Lee , Ki-ha Hong
IPC分类号： G11C11/00 , G11C8/00
CPC分类号： G11C8/08 , G11C5/063 , G11C11/21 , G11C13/0004 , G11C13/0007 , G11C13/0023 , G11C13/003 , G11C13/0069 , G11C15/04 , G11C2013/0073 , G11C2213/33 , G11C2213/71 , G11C2213/76 , H01L27/2409 , H01L27/2481 , H01L27/249 , H01L45/04 , H01L45/147 , H01L45/148
摘要： A nonvolatile memory cell may include a bidirectional switch having a first threshold voltage when a forward current is applied to the bidirectional switch and a second threshold voltage when a reverse current is applied to the bidirectional switch; and a variable resistor connected to the bidirectional switch in series. A state of resistance of the variable resistor may be controlled according to voltage applied to the variable resistor. A sum of a magnitude of the first threshold voltage and a magnitude of the second threshold voltage may be greater than a write voltage that is used to perform a write operation on the variable resistor.
摘要翻译：当向双向开关施加正向电流时，非易失性存储单元可以包括具有第一阈值电压的双向开关，当向双向开关施加反向电流时，非易失性存储单元可包括第二阈值电压; 以及串联连接到双向开关的可变电阻器。可变电阻器的电阻状态可以根据施加到可变电阻器的电压来控制。第一阈值电压的大小和第二阈值电压的大小的和可以大于用于对可变电阻器执行写入操作的写入电压。

10. 发明申请

US20120139069A1 STORAGE NODES, MAGNETIC MEMORY DEVICES, AND METHODS OF MANUFACTURING THE SAME 有权
标题翻译：存储编号，磁记录装置及其制造方法
公开(公告)号：US20120139069A1
公开(公告)日：2012-06-07
申请号：US13313361
申请日：2011-12-07
申请人： Kwang-seok Kim , U-In Chung , Jai-kwang Shin , Kee-won Kim , Sung-chul Lee , Ung-hwan Pi
发明人： Kwang-seok Kim , U-In Chung , Jai-kwang Shin , Kee-won Kim , Sung-chul Lee , Ung-hwan Pi
IPC分类号： H01L29/82 , H01L21/04
CPC分类号： H01L27/228 , G11C11/161 , H01L29/82 , H01L43/08 , H01L43/12
摘要： A storage node of a magnetic memory device includes: a lower magnetic layer, a tunnel barrier layer formed on the lower magnetic layer, and a free magnetic layer formed on the tunnel barrier. The free magnetic layer has a magnetization direction that is switchable in response to a spin current. The free magnetic layer has a cap structure surrounding at least one material layer on which the free magnetic layer is formed.
摘要翻译：磁存储器件的存储节点包括：下磁层，形成在下磁层上的隧道势垒层和形成在隧道势垒上的自由磁层。自由磁性层具有响应于自旋电流而可切换的磁化方向。自由磁性层具有围绕形成有自由磁性层的至少一个材料层的盖结构。

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