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1. 发明授权

US08656198B2 Method and apparatus for memory power management 有权
标题翻译：用于存储器电源管理的方法和装置
公开(公告)号：US08656198B2
公开(公告)日：2014-02-18
申请号：US12767460
申请日：2010-04-26
申请人： Alexander Branover , Maurice B. Steinman , Anthony Asaro , James B. Fry
发明人： Alexander Branover , Maurice B. Steinman , Anthony Asaro , James B. Fry
IPC分类号： G06F1/00
CPC分类号： G06F1/3203 , G06F1/3275 , G06F1/3287 , G11C5/148 , Y02D10/13 , Y02D10/14 , Y02D10/171 , Y02D50/20
摘要： A method for power management is disclosed. The method may include monitoring requests for access to a memory of a memory subsystem by one or more processor cores; and monitoring requests for access to the memory conveyed by an input/output (I/O) unit. The method may further include determining if at least a first amount of time has elapsed since any one of the processor cores has asserted a memory access request and determining if at least a second amount of time has elapsed since the I/O unit has conveyed a memory access request. A first signal may be asserted if the first and second amounts of time have elapsed. A memory subsystem may be transitioned from operating in a full power state to a first low power state responsive to assertion of the first signal.
摘要翻译：公开了一种用于电力管理的方法。该方法可以包括监视由一个或多个处理器核访问存储器子系统的存储器的请求; 以及监视对由输入/输出（I / O）单元传送的存储器的访问请求。该方法还可以包括确定是否已经过去了至少第一时间量，因为处理器核心已经确定了存储器访问请求并且确定自I / O单元是否已经传送了至少第二时间量内存访问请求。如果第一和第二时间量已经过去，则可以断言第一信号。存储器子系统可以响应于第一信号的断言而从全功率状态工作转变到第一低功率状态。

2. 发明授权

US06347154B1 Configurable horizontal scaler for video decoding and method therefore 有权
标题翻译：因此，可配置的水平缩放器用于视频解码和方法
公开(公告)号：US06347154B1
公开(公告)日：2002-02-12
申请号：US09288433
申请日：1999-04-08
申请人： Marinko Karanovic , James B. Fry
发明人： Marinko Karanovic , James B. Fry
IPC分类号： G06K936
CPC分类号： H04N7/01 , H04N19/46 , H04N19/59 , H04N19/80
摘要： A method and apparatus for performing scaling functions on a video signal is presented, where the scaling functions include a change in data rate of the signal. This is accomplished by performing the data rate conversion within a horizontal scaler of a video decoder. Filtering operations in the horizontal scaler are adjusted in order to take advantage of the data rate differential. Qualifier signals accompany portions of the video signal to indicate whether or not a particular portion of the signal is valid. These qualifiers are interpreted within the circuit to identify the portions that should be dropped, and the portions to be included in the output signal. In addition, registers within the horizontal scaler are used to store data corresponding to blanking regions within the input video signal, where data included in these blanking regions must be passed to the output signal in its entirety. The qualifiers corresponding to this portion of the data stream are all set to the valid level, indicating that none of the blanking region data is to be discarded.
摘要翻译：呈现用于对视频信号进行缩放函数的方法和装置，其中缩放函数包括信号的数据速率的变化。这通过在视频解码器的水平缩放器内执行数据速率转换来实现。调整水平缩放器中的过滤操作，以便利用数据速率差异。限定符信号伴随着视频信号的一部分，以指示信号的特定部分是否有效。这些限定符在电路内被解释，以识别应该丢弃的部分，以及要包括在输出信号中的部分。此外，水平缩放器内的寄存器用于存储对应于输入视频信号内的消隐区域的数据，其中包括在这些消隐区域中的数据必须被全部传递到输出信号。与数据流的这一部分相对应的限定符都被设置为有效级别，表示不排除任何消隐区域数据。

3. 发明授权

US07768507B2 Methods and apparatus for driving a display device 有权
标题翻译：用于驱动显示装置的方法和装置
公开(公告)号：US07768507B2
公开(公告)日：2010-08-03
申请号：US11164308
申请日：2005-11-17
申请人： James B. Fry
发明人： James B. Fry
IPC分类号： G06F3/038
CPC分类号： G09G5/006
摘要： According to the present disclosure, a transmitter for transmitting control characters to a display device over an interface includes a transmitter portion configured to transmit a control character having a plurality of bit values to the display device. The transmitter also includes logic configured to determine values of the bits in the control character and construct a corresponding plurality of rebalancing control characters based on the determination of the values of the plurality of bits in the control character to have bit values selected such that the combination of the control character and rebalancing control character is DC balanced. As such, the transmitter provides DC balance correction to non-DC balanced control characters in such a way as to allow DVI and HDMI to operate properly on an AC-coupled connection.
摘要翻译：根据本公开，用于通过接口向控制字符发送控制字符的发送器包括被配置为向显示设备发送具有多个位值的控制字符的发送器部分。发射机还包括被配置为基于控制字符中的多个比特的确定来确定控制字符中的比特的值并构造相应的多个重新平衡控制字符的逻辑，以使得选择的比特值使得该组合的控制角色和重新平衡控制角色是直流均衡的。因此，发射机以非直流平衡控制字符提供DC平衡校正，以使得DVI和HDMI能够在AC耦合的连接上正常工作。

4. 发明申请

US20110264934A1 METHOD AND APPARATUS FOR MEMORY POWER MANAGEMENT 有权
标题翻译：用于存储电源管理的方法和装置
公开(公告)号：US20110264934A1
公开(公告)日：2011-10-27
申请号：US12767460
申请日：2010-04-26
申请人： Alexander Branover , Maurice B. Steinman , Anthony Asaro , James B. Fry
发明人： Alexander Branover , Maurice B. Steinman , Anthony Asaro , James B. Fry
IPC分类号： G06F1/32
CPC分类号： G06F1/3203 , G06F1/3275 , G06F1/3287 , G11C5/148 , Y02D10/13 , Y02D10/14 , Y02D10/171 , Y02D50/20
摘要： A method for power management is disclosed. The method may include monitoring requests for access to a memory of a memory subsystem by one or more processor cores; and monitoring requests for access to the memory conveyed by an input/output (I/O) unit. The method may further include determining if at least a first amount of time has elapsed since any one of the processor cores has asserted a memory access request and determining if at least a second amount of time has elapsed since the I/O unit has conveyed a memory access request. A first signal may be asserted if the first and second amounts of time have elapsed. A memory subsystem may be transitioned from operating in a full power state to a first low power state responsive to assertion of the first signal.
摘要翻译：公开了一种用于电力管理的方法。该方法可以包括监视由一个或多个处理器核访问存储器子系统的存储器的请求; 以及监视对由输入/输出（I / O）单元传送的存储器的访问请求。该方法还可以包括确定是否已经过去了至少第一时间量，因为处理器核心已经确定了存储器访问请求并且确定自I / O单元是否已经传送了至少第二时间量内存访问请求。如果第一和第二时间量已经过去，则可以断言第一信号。存储器子系统可以响应于第一信号的断言而从全功率状态工作转变到第一低功率状态。

5. 发明授权

US07096303B1 Method and apparatus for configuring an integrated bus 有权
标题翻译：用于配置集成总线的方法和装置
公开(公告)号：US07096303B1
公开(公告)日：2006-08-22
申请号：US09586868
申请日：2000-06-05
申请人： Gordon Caruk , Kuldip Sahdra , Arkadi Avrukin , Michael Frank , Jamil Ahmed , James B. Fry , Sasa Marinkovic
发明人： Gordon Caruk , Kuldip Sahdra , Arkadi Avrukin , Michael Frank , Jamil Ahmed , James B. Fry , Sasa Marinkovic
IPC分类号： G06F13/36
CPC分类号： G06F13/4027
摘要： A configurable bus interface circuit includes an internal bus bridge and an internal circuit. The configurable bus interface circuit also includes an internal I/O circuit couplable to an external circuit, via the internal bus bridge. The configurable bus interface circuit electrically isolates the internal circuit to avoid the propagation of signals between the internal I/O circuit and the external circuit.
摘要翻译：可配置的总线接口电路包括内部总线桥和内部电路。可配置总线接口电路还包括可通过内部总线桥接器连接到外部电路的内部I / O电路。可配置总线接口电路将内部电路电隔离，以避免内部I / O电路和外部电路之间的信号传播。

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