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1. 发明授权

US08230378B2 Method for IC wiring yield optimization, including wire widening during and after routing 有权
标题翻译： IC布线产量优化方法，包括布线期间和之后的线宽
公开(公告)号：US08230378B2
公开(公告)日：2012-07-24
申请号：US12572297
申请日：2009-10-02
申请人： John M. Cohn , Jason D. Hibbeler , Gustavo E. Tellez
发明人： John M. Cohn , Jason D. Hibbeler , Gustavo E. Tellez
IPC分类号： G06F17/50
CPC分类号： G06F17/5077
摘要： Disclosed are embodiments of a method, service, and computer program product for performing yield-aware IC routing for a design. The method performs an initial global routing which satisfies wiring congestion constraints. Next, the method performs wire spreading and wire widening on the global route, layer by layer, based on, for example, a quadratic congestion optimization. Following this, timing closure is performed on the global route using results of the wire spreading and wire widening. Post-routing wiring width and wire spreading adjustments are made using the critical area yield model. In addition, the method allows for the optimization of already-routed data.
摘要翻译：公开了用于为设计执行屈服感知IC路由的方法，服务和计算机程序产品的实施例。该方法执行满足布线拥塞约束的初始全局路由。接下来，该方法基于例如二次拥塞优化来逐层地在全局路由上执行线扩展和线拓宽。之后，使用电线扩展和线宽加工的结果，在全局路线上执行定时关闭。使用关键区域产量模型进行布线后布线宽度和布线调整。此外，该方法允许优化已经路由的数据。

2. 发明申请

US20120137262A1 METHOD FOR COMPUTING THE SENSITIVITY OF A VLSI DESIGN TO BOTH RANDOM AND SYSTEMATIC DEFECTS USING A CRITICAL AREA ANALYSIS TOOL 失效
标题翻译：使用关键区域分析工具计算VLSI设计对两个随机和系统缺陷的灵敏度的方法
公开(公告)号：US20120137262A1
公开(公告)日：2012-05-31
申请号：US13368413
申请日：2012-02-08
申请人： Jeanne P. Bickford , Jason D. Hibbeler , Juergen Koehl
发明人： Jeanne P. Bickford , Jason D. Hibbeler , Juergen Koehl
IPC分类号： G06F17/50
CPC分类号： G06F17/5081
摘要： A method of estimating integrated circuit yield comprises providing an integrated circuit layout and a set of systematic defects based on a manufacturing process. Next, the method represents a systematic defect by modifying structures in the integrated circuit layout to create modified structures. More specifically, for short-circuit-causing defects, the method pre-expands the structures when the structures comprise a higher systematic defect sensitivity level, and pre-shrinks the structures when the structures comprise a lower systematic defect sensitivity level. Following this, a critical area analysis is performed on the integrated circuit layout using the modified structures, wherein dot-throwing, geometric expansion, or Voronoi diagrams are used. The method then computes a fault density value, random defects and systematic defects are computed. The fault density value is subsequently compared to a predetermined value, wherein the predetermined value is determined using test structures and/or yield data from a target manufacturing process.
摘要翻译：估计集成电路产量的方法包括基于制造过程提供集成电路布局和一组系统缺陷。接下来，该方法通过修改集成电路布局中的结构以产生修改的结构来表示系统缺陷。更具体地，对于短路导致的缺陷，当结构包括较高的系统缺陷灵敏度水平时，该方法预扩展结构，并且当结构包括较低的系统缺陷灵敏度水平时，预结构。接下来，使用改进的结构对集成电路布局进行关键区域分析，其中使用点投掷，几何展开或Voronoi图。然后，该方法计算故障密度值，计算随机缺陷和系统缺陷。随后将故障密度值与预定值进行比较，其中使用来自目标制造过程的测试结构和/或屈服数据确定预定值。

3. 发明申请

US20110166686A1 AUTOMATED SENSITIVITY DEFINITION AND CALIBRATION FOR DESIGN FOR MANUFACTURING TOOLS 有权
标题翻译：用于制造工具的自动灵敏度定义和校准
公开(公告)号：US20110166686A1
公开(公告)日：2011-07-07
申请号：US12652409
申请日：2010-01-05
申请人： James A. Culp , Jason D. Hibbeler , Lars W. Liebmann , Tina Wagner
发明人： James A. Culp , Jason D. Hibbeler , Lars W. Liebmann , Tina Wagner
IPC分类号： G06F17/50 , G06G7/66 , G06N5/02
CPC分类号： G06F17/5081 , G06F2217/12 , Y02P90/265
摘要： A method of automatic calibration of a design for manufacturing (DfM) simulation tool includes providing, as a first input, one or more defined rules for each of one or more semiconductor device levels to be simulated by the tool, and providing, as a second input, a plurality of defined feature size threshold ranges and increments for use in histogram generation of a number of failures with respect to a reference circuit; providing, as a third input, the reference circuit; executing the defined rules for the semiconductor device levels to be simulated, and outputting a fail count for the reference circuit at each defined threshold value, thereby generating histogram data of fail count versus threshold for the reference circuit; and providing, as a fourth input, a defined fail count metric, thereby calibrating the DfM tool for use with respect to a target circuit.
摘要翻译：一种用于制造设计（DfM）模拟工具的自动校准的方法包括为由工具模拟的一个或多个半导体器件级别中的每一个提供一个或多个限定规则作为第一输入，并且作为第二输入提供第二输入，多个定义的特征尺寸阈值范围和增量，用于相对于参考电路的多个故障的直方图生成; 提供参考电路作为第三输入; 执行要被模拟的半导体器件电平的限定规则，并在每个定义的阈值处输出参考电路的故障计数，由此产生参考电路的故障计数与阈值的直方图数据; 并且作为第四输入提供定义的故障计数度量，从而校准用于目标电路的DfM工具。

4. 发明授权

US07735042B2 Context aware sub-circuit layout modification 失效
标题翻译：上下文感知子电路布局修改
公开(公告)号：US07735042B2
公开(公告)日：2010-06-08
申请号：US11831998
申请日：2007-08-01
申请人： Michael S. Gray , Matthew T. Guzowski , Jason D. Hibbeler , Kevin W. McCullen , Robert F. Walker , Xin Yuan
发明人： Michael S. Gray , Matthew T. Guzowski , Jason D. Hibbeler , Kevin W. McCullen , Robert F. Walker , Xin Yuan
IPC分类号： G06F17/50
CPC分类号： G06F17/5068
摘要： A method, system and program product for context aware sub-circuit layout modification are disclosed. The method may include defining at least one context for the sub-circuit for each circuit that uses the sub-circuit; in the case that a plurality of contexts are defined, minimizing a number of contexts for the sub-circuit by combining contexts into at least one stage; placing each stage into a staged layout; and modifying the sub-circuit by modifying the staged layout.
摘要翻译：公开了一种用于上下文感知子电路布局修改的方法，系统和程序产品。该方法可以包括为使用子电路的每个电路定义用于子电路的至少一个上下文; 在定义多个上下文的情况下，通过将上下文合并到至少一个级中来最小化子电路的上下文数量; 将每个阶段放置在分阶段布局中; 并通过修改分段布局修改子电路。

5. 发明授权

US07721240B2 Systematic yield in semiconductor manufacture 失效
标题翻译：半导体制造系统产量
公开(公告)号：US07721240B2
公开(公告)日：2010-05-18
申请号：US11966135
申请日：2007-12-28
申请人： Paul H Bergeron , Jason D. Hibbeler , Gustavo E. Tellez
发明人： Paul H Bergeron , Jason D. Hibbeler , Gustavo E. Tellez
IPC分类号： G06F17/50
CPC分类号： G06F17/5068
摘要： Three-dimensional structures are provided which improve manufacturing yield for certain structures in semiconductor devices. The three-dimensional structures take into account the interaction between an upper layer and a lower layer where the lower layer has a tendency to form a non-planar surface due to its design. Accordingly, structures built on a layer above the lower layer are formed on a more planar surface and thus are more likely to function properly. The changes to improve manufacturing yield are made at the design stage rather than at the fabrication stage.
摘要翻译：提供三维结构，其提高半导体器件中某些结构的制造成品率。三维结构考虑到上层和下层之间的相互作用，其中下层由于其设计而具有形成非平面表面的倾向。因此，构建在下层上方的层上的结构形成在更平坦的表面上，因此更有可能正常地起作用。提高制造产量的变化是在设计阶段而不是在制造阶段进行的。

6. 发明申请

US20090158231A1 Design Structure for a Redundant Micro-Loop Structure for use in an Integrated Circuit Physical Design Process and Method of Forming the Same 有权
标题翻译：用于集成电路物理设计过程的冗余微环结构的设计结构及其形成方法
公开(公告)号：US20090158231A1
公开(公告)日：2009-06-18
申请号：US11955580
申请日：2007-12-13
申请人： Brent A. Anderson , Jeanne P. Bickford , Markus Buehler , Jason D. Hibbeler , Juergen Koehl , Edward J. Nowak
发明人： Brent A. Anderson , Jeanne P. Bickford , Markus Buehler , Jason D. Hibbeler , Juergen Koehl , Edward J. Nowak
IPC分类号： G06F17/50
CPC分类号： G06F17/5068 , G06F2217/12 , Y02P90/265
摘要： A design structure for an integrated circuit including a first wire of a first level of wiring tracks, a second wire of a second level of wiring tracks, a third wire of a third level of wiring tracks, and a fourth wire located a first distance from the second wire in the second level of wiring tracks. A first via connects the first and second wires at a first location of the second wire. A second via connects the second and third wires at the first location, the second via is substantially axially aligned with the first via. A third via connecting the third and fourth wires at a second location of the fourth wire. A fourth via connecting the first and fourth wires at the second location, the fourth via is substantially axially aligned with the third via. The second, third, and fourth vias, and the third and fourth wires form a path between the first and second wires redundant to the first via.
摘要翻译：一种用于集成电路的设计结构，该集成电路包括第一级布线轨道的第一线，第二级布线轨道的第二线，第三级布线轨道的第三线，以及位于第一距离处的第四线第二根电线在第二级线路上。第一通孔在第二导线的第一位置连接第一和第二导线。第二通孔在第一位置处连接第二和第三导线，第二通孔基本上与第一通孔轴向对准。第三通过在第四线的第二位置连接第三和第四导线。第四通孔在第二位置处连接第一和第四导线，第四通孔基本上与第三通孔轴向对准。第二，第三和第四通孔以及第三和第四导线形成第一和第二导线之间的路径，该路径对于第一通孔是冗余的。

7. 发明申请

US20090031263A1 METHOD AND SYSTEM FOR ANALYZING AN INTEGRATED CIRCUIT BASED ON SAMPLE WINDOWS SELECTED USING AN OPEN DETERMINISTIC SEQUENCING TECHNIQUE 有权
标题翻译：基于使用开放式确定性测序技术选择的样本窗口分析集成电路的方法和系统
公开(公告)号：US20090031263A1
公开(公告)日：2009-01-29
申请号：US11828728
申请日：2007-07-26
申请人： Sarah C. Braasch , Jason D. Hibbeler , Rouwaida N. Kanj , Daniel N. Maynard , Sani R. Nassif , Evanthia Papadopoulou
发明人： Sarah C. Braasch , Jason D. Hibbeler , Rouwaida N. Kanj , Daniel N. Maynard , Sani R. Nassif , Evanthia Papadopoulou
IPC分类号： G06F17/50
CPC分类号： G06F17/5081
摘要： Disclosed herein are embodiments of a system and an associated method for analyzing an integrated circuit to determine the value of a particular attribute (i.e., a physical or electrical property) in that integrated circuit. In the embodiments, an open deterministic sequencing technique is used to select a sequence of points representing centers of sample windows in an integrated circuit layout. Then, the value of the particular attribute is determined for each sample window and the results are accumulated in order to infer an overall value for that particular attribute for the entire integrated circuit layout. This sequencing technique has the advantage of allowing additional sample windows to be added and/or the sizes and shapes of the windows to be varied without hindering the quality of the sample.
摘要翻译：这里公开的是用于分析集成电路以确定该集成电路中的特定属性（即，物理或电气特性）的值的系统和相关方法的实施例。在实施例中，使用开放确定性测序技术来选择表示集成电路布局中的样本窗口中心的点序列。然后，为每个采样窗口确定特定属性的值，并累积结果，以推断整个集成电路布局的该特定属性的总体值。这种测序技术具有允许添加附加样品窗口和/或改变窗口的尺寸和形状而不妨碍样品质量的优点。

8. 发明申请

US20080195989A1 CONTENT BASED YIELD PREDICTION OF VLSI DESIGNS 失效
标题翻译：基于内容的VLSI设计预测
公开(公告)号：US20080195989A1
公开(公告)日：2008-08-14
申请号：US12101599
申请日：2008-04-11
申请人： Robert J. Allen , Daria R. Dooling , Jason D. Hibbeler , Daniel N. Maynard , Sarah C. Prue , Ralph J. Williams
发明人： Robert J. Allen , Daria R. Dooling , Jason D. Hibbeler , Daniel N. Maynard , Sarah C. Prue , Ralph J. Williams
IPC分类号： G06F9/45
CPC分类号： G06F17/5045
摘要： An integrated circuit and program product for predicting yield of a VLSI design. An integrated circuit is provided including a system for identifying and grouping sub-circuits contained within an integrated circuit design by circuit type; a critical area calculation system for determining critical area values for different regions, wherein each different region is associated with a circuit type; a tallying system for calculating a plurality of tallies of critical area values based on circuit type; and a plurality of modeling subsystems for separately modeling each of the plurality of tallies based on circuit type.
摘要翻译：一种用于预测VLSI设计产量的集成电路和程序产品。提供一种集成电路，包括用于通过电路类型识别和分组集成电路设计中包含的子电路的系统; 用于确定不同区域的临界面积值的关键区域计算系统，其中每个不同区域与电路类型相关联; 用于基于电路类型计算多个临界面积值的计数系统; 以及多个建模子系统，用于基于电路类型对所述多个提议中的每一个进行单独建模。

9. 发明申请

US20080155482A1 AUTOMATED OPTIMIZATION OF VLSI LAYOUTS FOR REGULARITY 审中-公开
标题翻译：自动优化VLSI LAYOUTS FOR REGULARITY
公开(公告)号：US20080155482A1
公开(公告)日：2008-06-26
申请号：US11614260
申请日：2006-12-21
申请人： Dureseti Chidambarrao , James A. Culp , Jason D. Hibbeler
发明人： Dureseti Chidambarrao , James A. Culp , Jason D. Hibbeler
IPC分类号： G06F17/50
CPC分类号： G06F17/5081 , G06F2217/12 , Y02P90/265
摘要： VLSI lithographic fidelity is improved via reducing the pattern space of difficult patterns or structures in a design layout for an integrated circuit design, and thereby increasing the regularity of the design, by converting patterns or structures that are similar but not identical to one another into a smaller set of canonical geometric configurations. By doing so, lithographic processing can be tuned to handle the smaller set of configurations more accurately and efficiently.
摘要翻译：通过在集成电路设计的设计布局中减少难图案或结构的图案空间来改进VLSI光刻保真度，从而通过将彼此相似但不完全相同的图案或结构转换为较小的规范几何配置。通过这样做，可以调整光刻处理以更准确和有效地处理较小的一组配置。

10. 发明授权

US07363601B2 Integrated circuit selective scaling 有权
标题翻译：集成电路选择性缩放
公开(公告)号：US07363601B2
公开(公告)日：2008-04-22
申请号：US10711959
申请日：2004-10-15
申请人： Fook-Luen Heng , Jason D. Hibbeler , Kevin W. McCullen , Rani R. Narayan , Stephen L. Runyon , Robert F. Walker
发明人： Fook-Luen Heng , Jason D. Hibbeler , Kevin W. McCullen , Rani R. Narayan , Stephen L. Runyon , Robert F. Walker
IPC分类号： G06F17/50
CPC分类号： G06F17/5068
摘要： Methods, systems and program products are disclosed for selectively scaling an integrated circuit (IC) design: by layer, by unit, or by ground rule, or a combination of these. The selective scaling technique can be applied in a feedback loop with the manufacturing system with process and yield feedback, during the life of a design, to increase yield in early processes in such a way that hierarchy is preserved. The invention removes the need to involve designers in improving yield where new technologies such as maskless fabrication are implemented.
摘要翻译：公开了用于选择性地缩放集成电路（IC）设计的方法，系统和程序产品：按层，单元或基本规则，或这些的组合。在设计寿命期间，选择性缩放技术可以应用于具有过程和产量反馈的制造系统的反馈回路中，以便以保持层次结构的方式增加早期过程中的产量。本发明消除了在实现诸如无掩模制造之类的新技术的情况下使设计人员改进产量的需要。

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