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1. 发明授权

US09557378B2 Method and structure for multi-core chip product test and selective voltage binning disposition 有权
标题翻译：多核芯片产品测试和选择性电压组合配置的方法和结构
公开(公告)号：US09557378B2
公开(公告)日：2017-01-31
申请号：US13553986
申请日：2012-07-20
申请人： Jeanne P. Bickford , Vikram Iyengar , Rahul K. Nadkarni , Pascal A. Nsame
发明人： Jeanne P. Bickford , Vikram Iyengar , Rahul K. Nadkarni , Pascal A. Nsame
IPC分类号： H01L21/66 , G01R31/02 , G06F19/00 , G01R31/317 , G06F1/32
CPC分类号： G01R31/31718 , G01R31/31725 , G06F1/32
摘要： Operating speeds of integrated circuit devices are tested to establish maximum and minimum frequency at maximum and minimum voltage. The devices are sorted into relatively-slow and relatively-fast devices to classify the devices into different voltage bins. A bin-specific voltage limit is established for each of the voltage bins needed for core performance at system use conditions. The bin-specific voltage limit is compared to core minimum chip-level functionality voltage at system maximum and minimum frequency specifications. The method correlates system design evaluation of design maximum and minimum frequency at design maximum and minimum voltage conditions with evaluation of tested maximum and minimum frequency at tested maximum and minimum voltage conditions. A chip-specific functionality voltage limit is established for the device. Initial system voltage for all devices from a voltage bin is set at a greater of the bin-specific voltage limit and the chip-specific functionality voltage limit consistent with the evaluation conditions.
摘要翻译：测试集成电路器件的工作速度，以在最大和最小电压下建立最大和最小频率。将器件分类为相对较慢且相对较快的器件，以将器件分类到不同的电压仓。对于在系统使用条件下核心性能所需的每个电压箱，建立了一个特定于特定电压限制。特定于箱体的电压限制与系统最大和最小频率规格下的核心最小芯片级功能电压进行比较。该方法在设计最大和最小电压条件下将设计最大和最小频率的系统设计评估与测试的最大和最小电压条件下的最大和最小频率进行了评估。为器件建立芯片专用功能电压限制。来自电压仓的所有器件的初始系统电压设置在特定于器件的电压限制和芯片专用功能电压限制的更大值与评估条件一致。

2. 发明授权

US09429619B2 Reliability test screen optimization 有权
标题翻译：可靠性测试屏幕优化
公开(公告)号：US09429619B2
公开(公告)日：2016-08-30
申请号：US13564337
申请日：2012-08-01
申请人： Theodoros E. Anemikos , Jeanne P. Bickford , Douglas S. Dewey , Ernest A. Viau, Jr.
发明人： Theodoros E. Anemikos , Jeanne P. Bickford , Douglas S. Dewey , Ernest A. Viau, Jr.
IPC分类号： G06F19/00 , G01R31/28 , G05B19/418 , G01R31/317
CPC分类号： G01R31/2894 , G01R31/2855 , G01R31/2868 , G01R31/287 , G01R31/2879 , G01R31/31718 , G05B19/41875 , Y02P90/14 , Y02P90/265
摘要： Methods and systems optimize power usage in an integrated circuit design by sorting the integrated circuit devices after manufacture into relatively slow integrated circuit devices and relatively fast integrated circuit devices to classify the integrated circuit devices into different voltage bins. The methods and systems establish a bin-specific reliability testing processes for each of the voltage bins and test the integrated circuit devices using a tester. This allows the methods and systems to identify as defective ones of the integrated circuit devices that fail the bin-specific integrated circuit reliability testing processes of a corresponding voltage bin. The methods and systems remove the defective ones of the integrated circuit devices to allow only non-defective integrated circuit devices to remain and supply the non-defective integrated circuit devices to a customer.
摘要翻译：方法和系统通过将制造后的集成电路器件分类为相对较慢的集成电路器件和相对较快的集成电路器件来将集成电路器件分类到不同的电压仓中来优化集成电路设计中的功率利用。方法和系统为每个电压仓建立一个二进制特定的可靠性测试过程，并使用测试仪测试集成电路器件。这允许方法和系统将不合格的集成电路设备中的缺陷识别为相应电压箱的专用集成电路可靠性测试过程。所述方法和系统移除集成电路器件中的有缺陷的集成电路器件，以便只允许无故障的集成电路器件保持并向客户提供无缺陷的集成电路器件。

3. 发明申请

US20130125076A1 DISPOSITION OF INTEGRATED CIRCUITS USING PERFORMANCE SORT RING OSCILLATOR AND PERFORMANCE PATH TESTING 有权
标题翻译：使用性能排序振荡器和性能路径测试处理集成电路
公开(公告)号：US20130125076A1
公开(公告)日：2013-05-16
申请号：US13294220
申请日：2011-11-11
申请人： Jeanne P. Bickford , Peter A. Habitz , Vikram Iyengar , David E. Lackey , Jinjun Xiong
发明人： Jeanne P. Bickford , Peter A. Habitz , Vikram Iyengar , David E. Lackey , Jinjun Xiong
IPC分类号： G06F17/50
CPC分类号： G01R31/3016 , G01R31/31725
摘要： A method and system for dispositioning integrated circuit chips. The method includes performing a performance path test on an integrated circuit chip having one or more clock domains, the performance path test based on applying test patterns to selected sensitizable data paths of the integrated circuit chip at different clock frequencies; and dispositioning the integrated circuit chip based on results of the performance path test.
摘要翻译：一种配置集成电路芯片的方法和系统。该方法包括对具有一个或多个时钟域的集成电路芯片执行性能路径测试，该性能路径测试基于将测试图案应用于集成电路芯片的不同时钟频率的选择的可敏化数据路径; 并且基于性能路径测试的结果来布置集成电路芯片。

4. 发明授权

US08234594B2 Redundant micro-loop structure for use in an integrated circuit physical design process and method of forming the same 有权
标题翻译：冗余微环结构用于集成电路物理设计过程及其形成方法
公开(公告)号：US08234594B2
公开(公告)日：2012-07-31
申请号：US11552225
申请日：2006-10-24
申请人： Brent A. Anderson , Jeanne P. Bickford , Markus Buehler , Jason D. Hibbeler , Juergen Koehl , Edward J. Nowak
发明人： Brent A. Anderson , Jeanne P. Bickford , Markus Buehler , Jason D. Hibbeler , Juergen Koehl , Edward J. Nowak
IPC分类号： G06F17/50 , H01L23/48 , H01L23/52 , H01L29/40
CPC分类号： H01L23/528 , H01L2924/0002 , H01L2924/00
摘要： An integrated circuit including a first wire of a first level of wiring tracks, a second wire of a second level of wiring tracks, a third wire of a third level of wiring tracks, and a fourth wire located at a first distance from the second wire in the second level of wiring tracks. A first via connects the first and second wires at a first location of the second wire. A second via connects the second and third wires at the first location, the second via is approximately axially aligned with the first via. A third via connecting the third and fourth wires at a second location of the fourth wire. A fourth via connecting the first and fourth wires at the second location, the fourth via is approximately axially aligned with the third via. The second, third, and fourth vias, and the third and fourth wires form a path between the first and second wires redundant to the first via.
摘要翻译：一种集成电路，包括第一级布线轨道的第一线，第二级布线轨道的第二线，第三级布线轨道的第三线和位于距离第二线的第一距离的第四线在第二级线路上。第一通孔在第二导线的第一位置连接第一和第二导线。第二通孔在第一位置处连接第二和第三导线，第二通孔大致轴向对准第一通孔。第三通过在第四线的第二位置连接第三和第四导线。在第二位置连接第一和第四导线的第四通孔，第四通孔与第三通孔大致轴向对齐。第二，第三和第四通孔以及第三和第四导线形成第一和第二导线之间的路径，该路径对于第一通孔是冗余的。

5. 发明申请

US20110289470A1 Methods and Systems to Meet Technology Pattern Density Requirements of Semiconductor Fabrication Processes 失效
标题翻译：满足半导体制造工艺的技术图案密度要求的方法和系统
公开(公告)号：US20110289470A1
公开(公告)日：2011-11-24
申请号：US12782337
申请日：2010-05-18
申请人： Jeanne P. BICKFORD , Allan O. CRUZ , Michelle GILL , Howard S. LANDIS , David V. MACDONNELL, II , Donald J. SAMUELS , Roger J. YERDON
发明人： Jeanne P. BICKFORD , Allan O. CRUZ , Michelle GILL , Howard S. LANDIS , David V. MACDONNELL, II , Donald J. SAMUELS , Roger J. YERDON
IPC分类号： G06F17/50
CPC分类号： G06F17/5081 , G06F2217/12 , Y02P90/265
摘要： Techniques, systems, and methods are provided for optimizing pattern density fill patterns for integrated circuits. The method includes adjusting an area of a scribe line and a density of dummy fill shapes in the adjusted scribe line, while maintaining an area of the die, to achieve a pattern density associated with technology ground rules for a particular design of the die.
摘要翻译：提供了技术，系统和方法来优化用于集成电路的图案密度填充图案。该方法包括在保持模具的面积的同时调节划线的面积和调整的划线中的虚拟填充形状的密度，以实现与针对模具的特定设计的技术基础规则相关联的图案密度。

6. 发明授权

US07984394B2 Design structure for a redundant micro-loop structure for use in an integrated circuit physical design process and method of forming the same 有权
标题翻译：用于集成电路物理设计过程中使用的冗余微环结构的设计结构及其形成方法
公开(公告)号：US07984394B2
公开(公告)日：2011-07-19
申请号：US11955580
申请日：2007-12-13
申请人： Brent A. Anderson , Jeanne P. Bickford , Markus Buehler , Jason D. Hibbeler , Juergen Koehl , Edward J. Nowak
发明人： Brent A. Anderson , Jeanne P. Bickford , Markus Buehler , Jason D. Hibbeler , Juergen Koehl , Edward J. Nowak
IPC分类号： G06F17/50
CPC分类号： G06F17/5068 , G06F2217/12 , Y02P90/265
摘要： A design structure for an integrated circuit including a first wire of a first level of wiring tracks, a second wire of a second level of wiring tracks, a third wire of a third level of wiring tracks, and a fourth wire located a first distance from the second wire in the second level of wiring tracks. A first via connects the first and second wires at a first location of the second wire. A second via connects the second and third wires at the first location, the second via is substantially axially aligned with the first via. A third via connecting the third and fourth wires at a second location of the fourth wire. A fourth via connecting the first and fourth wires at the second location, the fourth via is substantially axially aligned with the third via. The second, third, and fourth vias, and the third and fourth wires form a path between the first and second wires redundant to the first via.
摘要翻译：一种用于集成电路的设计结构，该集成电路包括第一级布线轨道的第一线，第二级布线轨道的第二线，第三级布线轨道的第三线，以及位于第一距离处的第四线第二根电线在第二级线路上。第一通孔在第二导线的第一位置连接第一和第二导线。第二通孔在第一位置处连接第二和第三导线，第二通孔基本上与第一通孔轴向对准。第三通过在第四线的第二位置连接第三和第四导线。第四通孔在第二位置处连接第一和第四导线，第四通孔基本上与第三通孔轴向对准。第二，第三和第四通孔以及第三和第四导线形成第一和第二导线之间的路径，该路径对于第一通孔是冗余的。

7. 发明授权

US07398485B2 Yield optimization in router for systematic defects 失效
标题翻译：路由器产生优化系统缺陷
公开(公告)号：US07398485B2
公开(公告)日：2008-07-08
申请号：US11279262
申请日：2006-04-11
申请人： Jeanne P. Bickford , Markus T. Buehler , Jason D. Hibbeler , Juergen Koehl , Daniel N. Maynard
发明人： Jeanne P. Bickford , Markus T. Buehler , Jason D. Hibbeler , Juergen Koehl , Daniel N. Maynard
IPC分类号： G06F17/50
CPC分类号： G06F17/5077
摘要： Embodiments herein provide a method and computer program product for optimizing router settings to increase IC yield. A method begins by reviewing yield data in an IC manufacturing line to identify structure-specific mechanisms that impact IC yield. Next, the method establishes a structural identifier for each structure-specific mechanism, wherein the structural identifiers include wire codes, tags, and/or unique identifiers. Different structural identifiers are established for wires having different widths. Furthermore, the method establishes a weighting factor for each structure-specific mechanism, wherein higher weighting factors are established for structure-specific mechanisms comprising thick wires proximate to multiple thick wires. The method establishes the structural identifiers and the weighting factors for incidence of spacing between single wide lines, double wide lines, and triple wide lines and for incidence of wires above large metal lands. Subsequently, the router settings are modified based on the structural identifiers and the weighting factors to minimize systematic defects.
摘要翻译：本文的实施例提供了一种用于优化路由器设置以增加IC产量的方法和计算机程序产品。一种方法开始于检查IC生产线中的产量数据，以确定影响IC产量的结构特异性机制。接下来，该方法为每个结构特定机制建立结构标识符，其中结构标识符包括有线代码，标签和/或唯一标识符。针对具有不同宽度的电线建立了不同的结构标识符。此外，该方法为每个结构特定机构建立加权因子，其中针对包括靠近多个粗线的粗线的结构特定机构建立较高的加权因子。该方法建立了单宽线，双宽线和三宽线之间的间距发生的结构标识符和加权因子，以及大金属土地上电线的入射。随后，路由器设置基于结构标识符和权重因子进行修改，以最大限度地减少系统缺陷。

8. 发明授权

US07380233B2 Method of facilitating integrated circuit design using manufactured property values 有权
标题翻译：使用制造的属性值促进集成电路设计的方法
公开(公告)号：US07380233B2
公开(公告)日：2008-05-27
申请号：US11162196
申请日：2005-08-31
申请人： Jeanne P. Bickford , Steven M. Fox , Donald J. Hathaway , Ian P. Stobert
发明人： Jeanne P. Bickford , Steven M. Fox , Donald J. Hathaway , Ian P. Stobert
IPC分类号： G06F17/50
CPC分类号： G06F17/5045
摘要： An integrated circuit (IC) design method for use as a design and/or manufacturing tool for designing and/or manufacturing integrated circuitry (110). The method utilizes one or more library element (150A-F) to provide a flexible modeling template. Each library element includes one or more module ports (160A-F) each for accepting any one of a plurality of device modules (170). The device modules are logical representations of corresponding respective portions of the integrated circuitry. For any given module port, the corresponding device modules may be interchanged essentially without additional integrated circuitry design changes.
摘要翻译：一种用作设计和/或制造集成电路（110）的设计和/或制造工具的集成电路（IC）设计方法。该方法利用一个或多个库元素（150A-F）来提供灵活的建模模板。每个库元素包括一个或多个模块端口（160A-F），每个模块端口用于接受多个设备模块（170）中的任何一个。设备模块是集成电路的对应的相应部分的逻辑表示。对于任何给定的模块端口，相应的设备模块可以基本上互换，而没有额外的集成电路设计更改。

9. 发明授权

US08839170B2 Power/performance optimization through temperature/voltage control 有权
标题翻译：通过温度/电压控制实现功率/性能优化
公开(公告)号：US08839170B2
公开(公告)日：2014-09-16
申请号：US13749851
申请日：2013-01-25
申请人： Jeanne P. Bickford , Eric A. Foreman , Mark W. Kuemerle , Susan K. Lichtensteiger
发明人： Jeanne P. Bickford , Eric A. Foreman , Mark W. Kuemerle , Susan K. Lichtensteiger
IPC分类号： G06F17/50 , G01R31/317
CPC分类号： G06F17/5045 , G01R31/31721 , G06F17/5031
摘要： A method of optimizing power and timing for an integrated circuit (IC) chip, identifies a plurality of valid temperature and voltage combinations that allow integrated circuit chips produced according to the integrated circuit chip design to operate within average power consumption goals and timing delay goals. Such a method selects temperature cut points from the valid temperature and voltage combinations for each of the integrated circuit chips, calculates a power consumption amount of each of the temperature cut points, and adjusts the temperature cut points based on the power consumption amount until the temperature cut points achieve the average power consumption goals. Next, this method tests each of the integrated circuit chips, and records the temperature cut points in the memory of the integrated circuit chips.
摘要翻译：一种优化集成电路（IC）芯片的功率和定时的方法，识别允许根据集成电路芯片设计产生的集成电路芯片在平均功耗目标和时序延迟目标内工作的多个有效的温度和电压组合。这种方法从每个集成电路芯片的有效温度和电压组合中选择温度切割点，计算每个温度切断点的功率消耗量，并且基于功耗量调节温度切断点直到温度切点实现了平均功耗目标。接下来，该方法测试每个集成电路芯片，并将温度切割点记录在集成电路芯片的存储器中。

10. 发明申请

US20140046466A1 INTEGRATED CIRCUIT PRODUCT YIELD OPTIMIZATION USING THE RESULTS OF PERFORMANCE PATH TESTING 有权
标题翻译：使用性能路径测试结果的集成电路产品线优化
公开(公告)号：US20140046466A1
公开(公告)日：2014-02-13
申请号：US13570285
申请日：2012-08-09
申请人： Jeanne P. Bickford , Peter A. Habitz , Vikram Iyengar , Jinjun Xiong
发明人： Jeanne P. Bickford , Peter A. Habitz , Vikram Iyengar , Jinjun Xiong
IPC分类号： G05B19/18
CPC分类号： G05B19/41875 , G05B2219/32182 , G05B2219/32187 , G05B2219/32208 , G05B2219/37224 , Y02P80/30 , Y02P90/22
摘要： Disclosed are embodiments of a method, system and computer program product for optimizing integrated circuit product yield by re-centering the manufacturing line and, optionally, adjusting wafer-level chip dispositioning rules based on the results of post-manufacture (e.g., wafer-level or module-level) performance path testing. In the embodiments, a correlation is made between in-line parameter measurements and performance measurements acquired during the post-manufacture performance path testing. Then, based on this correlation, the manufacturing line can be re-centered. Optionally, an additional correlation is made between performance measurements acquired during wafer-level performance testing and performance measurements acquired particularly during module-level performance path testing and, based on this additional correlation, adjustments can be made to the wafer-level chip dispositioning rules to further minimize yield loss.
摘要翻译：公开了用于通过使生产线重新对中来优化集成电路产品产量的方法，系统和计算机程序产品的实施例，并且可选地，基于后期制造的结果调整晶片级芯片布置规则（例如，晶片级或模块级）性能路径测试。在实施例中，在后续制造性能路径测试期间获得的在线参数测量和性能测量之间进行相关。然后，基于这种相关性，生产线可以重新居中。可选地，在晶片级性能测试期间获得的性能测量和特别在模块级性能路径测试期间获得的性能测量之间进行附加的相关性，并且基于该附加相关性，可以对晶片级芯片布置规则进行调整进一步降低产量损失。

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