专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明授权

US08090929B2 Generating clock signals for coupled ASIC chips in processor interface with X and Y logic operable in functional and scanning modes 有权
标题翻译：在处理器接口中为耦合ASIC芯片生成时钟信号，X和Y逻辑可在功能和扫描模式下运行
公开(公告)号：US08090929B2
公开(公告)日：2012-01-03
申请号：US12236551
申请日：2008-09-24
申请人： Jeffrey A. Magee , Timothy Gerard McNamara , Walter Niklaus , Scott Barnett Swaney , Tobias Webel
发明人： Jeffrey A. Magee , Timothy Gerard McNamara , Walter Niklaus , Scott Barnett Swaney , Tobias Webel
IPC分类号： G06F1/04
CPC分类号： G06F9/3869 , G01R31/318533 , G01R31/318558
摘要： A digital system and method of operating the same. The system comprises a processor chip including a first elastic interface domain, wherein the first elastic interface domain comprises a first processor X logic and a first processor Y logic, wherein the first processor X and Y logic comprise first X and Y latches, respectively; and a first ASIC chip electrically coupled to the processor chip, wherein the first processor X and Y logics are configured to be simultaneously in a functional mode, wherein the first processor X logic is configured to switch from the functional mode to a scanning mode while the first processor Y logic remains in the functional mode, and wherein in response to the first processor Y logic being in the functional mode, the first processor Y logic is configured to generate a first reference ASIC clock signal to the first ASIC chip.
摘要翻译：数字系统及其操作方法。该系统包括包括第一弹性接口域的处理器芯片，其中第一弹性接口域包括第一处理器X逻辑和第一处理器Y逻辑，其中第一处理器X和Y逻辑分别包括第一X和Y锁存器; 以及电耦合到所述处理器芯片的第一ASIC芯片，其中所述第一处理器X和Y逻辑被配置为同时处于功能模式，其中所述第一处理器X逻辑被配置为从所述功能模式切换到扫描模式，而第一处理器Y逻辑保持在功能模式中，并且其中响应于第一处理器Y逻辑处于功能模式，第一处理器Y逻辑被配置为产生到第一ASIC芯片的第一参考ASIC时钟信号。

2. 发明授权

US07734944B2 Mechanism for windaging of a double rate driver 有权
标题翻译：双速率驱动程序的机制
公开(公告)号：US07734944B2
公开(公告)日：2010-06-08
申请号：US11426648
申请日：2006-06-27
申请人： Jonathan Y. Chen , Jeffrey A. Magee , David A. Webber
发明人： Jonathan Y. Chen , Jeffrey A. Magee , David A. Webber
IPC分类号： G06F5/06 , G06F13/42 , H04L7/00
CPC分类号： G06F1/12
摘要： A double data rate launch system and method in which the two-to-one multiplexer select signal delay is programmable and can be adjusted individually for each system. This allows the amount of delay to be minimized based on the actual set up time required, not the worst-case set-up time. The select signal to the multiplexer is delayed sufficiently to compensate for non-uniformity of duty cycle of data at the inputs to the multiplexer. Compensation of the non-uniformity allows the data on the wire to have a uniform duty cycle for all data transferred regardless of which latch is sourcing the data. The multiplexer that selects data from the two latches which are launching data on the edge of different clocks has a select line that is delayed by a variable amount to tune the select such that the data is clean at the input to the multiplexer on all ports.
摘要翻译：双数据速率发射系统和方法，其中两对一多路复用器选择信号延迟是可编程的，并且可以针对每个系统单独调整。这允许根据所需的实际设置时间而不是最坏的设置时间来最小化延迟量。到复用器的选择信号被充分延迟以补偿多路复用器的输入处的数据的占空比的不均匀性。不均匀性的补偿允许导线上的数据对于所有传输的数据具有统一的占空比，而不考虑哪个锁存器来源数据。选择来自两个锁存器的数据的多路复用器，这些数据是在不同时钟边沿发射数据的，具有延迟一个可变量的选择线，以调整选择，使得数据在所有端口上的多路复用器的输入处是干净的。

3. 发明申请

US20070300098A1 Mechanism for Windaging of a Double Rate Driver 有权
标题翻译：双速率驱动程序的机制
公开(公告)号：US20070300098A1
公开(公告)日：2007-12-27
申请号：US11426648
申请日：2006-06-27
申请人： Jonathan Y. Chen , Jeffrey A. Magee , David A. Webber
发明人： Jonathan Y. Chen , Jeffrey A. Magee , David A. Webber
IPC分类号： G06F1/12
CPC分类号： G06F1/12
摘要： A double data rate launch system and method in which the two-to-one multiplexer select signal delay is programmable and can be adjusted individually for each system. This allows the amount of delay to be minimized based on the actual set up time required, not the worst-case set-up time. The select signal to the multiplexer is delayed sufficiently to compensate for non-uniformity of duty cycle of data at the inputs to the multiplexer. Compensation of the non-uniformity allows the data on the wire to have a uniform duty cycle for all data transferred regardless of which latch is sourcing the data. The multiplexer that selects data from the two latches which are launching data on the edge of different clocks has a select line that is delayed by a variable amount to tune the select such that the data is clean at the input to the multiplexer on all ports.
摘要翻译：双数据速率发射系统和方法，其中两对一多路复用器选择信号延迟是可编程的，并且可以针对每个系统单独调整。这允许根据所需的实际设置时间而不是最坏的设置时间来最小化延迟量。到复用器的选择信号被充分延迟以补偿多路复用器的输入处的数据的占空比的不均匀性。不均匀性的补偿允许导线上的数据对于所有传输的数据具有统一的占空比，而不考虑哪个锁存器来源数据。选择来自两个锁存器的数据的多路复用器，这些数据是在不同时钟边沿发射数据的，具有延迟一个可变量的选择线，以调整选择，使得数据在所有端口上的多路复用器的输入处是干净的。

4. 发明申请

US20090217000A1 CLOCK SIGNALS IN DIGITAL SYSTEMS 有权
标题翻译：数字系统中的时钟信号
公开(公告)号：US20090217000A1
公开(公告)日：2009-08-27
申请号：US12236551
申请日：2008-09-24
申请人： Jeffrey A. Magee , Timothy Gerard McNamara , Walter Niklaus , Scott Barnett Swaney , Tobias Webel
发明人： Jeffrey A. Magee , Timothy Gerard McNamara , Walter Niklaus , Scott Barnett Swaney , Tobias Webel
IPC分类号： G06F1/04 , G06F1/06 , G06F15/76 , G06F9/02
CPC分类号： G06F9/3869 , G01R31/318533 , G01R31/318558
摘要： A digital system and method of operating the same. The system comprises a processor chip including a first elastic interface domain, wherein the first elastic interface domain comprises a first processor X logic and a first processor Y logic, wherein the first processor X and Y logic comprise first X and Y latches, respectively; and a first ASIC chip electrically coupled to the processor chip, wherein the first processor X and Y logics are configured to be simultaneously in a functional mode, wherein the first processor X logic is configured to switch from the functional mode to a scanning mode while the first processor Y logic remains in the functional mode, and wherein in response to the first processor Y logic being in the functional mode, the first processor Y logic is configured to generate a first reference ASIC clock signal to the first ASIC chip.
摘要翻译：数字系统及其操作方法。该系统包括包括第一弹性接口域的处理器芯片，其中第一弹性接口域包括第一处理器X逻辑和第一处理器Y逻辑，其中第一处理器X和Y逻辑分别包括第一X和Y锁存器; 以及电耦合到所述处理器芯片的第一ASIC芯片，其中所述第一处理器X和Y逻辑被配置为同时处于功能模式，其中所述第一处理器X逻辑被配置为从所述功能模式切换到扫描模式，而第一处理器Y逻辑保持在功能模式中，并且其中响应于第一处理器Y逻辑处于功能模式，第一处理器Y逻辑被配置为产生到第一ASIC芯片的第一参考ASIC时钟信号。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式