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1. 发明授权

US07870406B2 Method and apparatus for frequency independent processor utilization recording register in a simultaneously multi-threaded processor 有权
标题翻译：用于频率独立处理器利用记录寄存器的同时多线程处理器的方法和装置
公开(公告)号：US07870406B2
公开(公告)日：2011-01-11
申请号：US11050325
申请日：2005-02-03
申请人： Richard Louis Arndt , Balaram Sinharoy , Scott Barnett Swaney , Kenneth Lundy Ward
发明人： Richard Louis Arndt , Balaram Sinharoy , Scott Barnett Swaney , Kenneth Lundy Ward
IPC分类号： G06F1/00
CPC分类号： G06F11/3442 , G06F1/206 , G06F1/3203 , G06F1/324 , G06F11/3471 , G06F2201/88 , G06F2201/885 , Y02D10/126
摘要： Mechanism for accurately measuring useful capacity of a processor allocated to each thread in a simultaneously multi-threading data processing system. Instructions dispatched from multiple threads are executed by the processor on a same clock cycle. A determination is made whether Time Base (TB) register bit (60) is changing. A dispatch charge value is determined for each thread, and added to the Processor Utilization Resource Register for each thread when TB bit (60) changes.
摘要翻译：用于准确测量在同时多线程数据处理系统中分配给每个线程的处理器的有用容量的机制。从多个线程调度的指令由处理器以相同的时钟周期执行。确定时基（TB）寄存器位（60）是否改变。为每个线程确定调度费用值，并在TB位（60）更改时将其添加到每个线程的处理器利用资源寄存器中。

2. 发明申请

US20090113212A1 Multiprocessor electronic circuit including a plurality of processors and electronic data processing system 有权
标题翻译：多处理器电子电路包括多个处理器和电子数据处理系统
公开(公告)号：US20090113212A1
公开(公告)日：2009-04-30
申请号：US12248549
申请日：2008-10-09
申请人： Thomas Koehler , Thomas Fuchs , Ulrich Mayer , Chung-Lung Kevin Shum , Scott Barnett Swaney
发明人： Thomas Koehler , Thomas Fuchs , Ulrich Mayer , Chung-Lung Kevin Shum , Scott Barnett Swaney
IPC分类号： G06F21/00
CPC分类号： G06F21/72
摘要： A multiprocessor electronic circuit and an electronic data processing system comprising such circuit are disclosed for reducing the power consumption and the chip area consumption of a multiprocessor system having cryptographic functionality. In one embodiment, the multiprocessor electronic circuit comprises a plurality of processors, a single cryptographic processing unit that comprises a plurality of input/output buffer pairs and two cryptographic engines, a cipher engine and a hash engine, and associated control logic.
摘要翻译：公开了一种包括这种电路的多处理器电子电路和电子数据处理系统，用于降低具有加密功能的多处理器系统的功耗和芯片面积消耗。在一个实施例中，多处理器电子电路包括多个处理器，包括多个输入/输出缓冲器对和两个加密引擎，密码引擎和哈希引擎以及相关控制逻辑的单个密码处理单元。

3. 发明申请

US20090063898A1 Processor Instruction Retry Recovery 失效
标题翻译：处理器指令重试恢复
公开(公告)号：US20090063898A1
公开(公告)日：2009-03-05
申请号：US12270300
申请日：2008-11-13
申请人： Susan Elizabeth Eisen , Hung Qui Le , Michael James Mack , Dung Quoc Nguyen , Jose Angel Paredes , Scott Barnett Swaney
发明人： Susan Elizabeth Eisen , Hung Qui Le , Michael James Mack , Dung Quoc Nguyen , Jose Angel Paredes , Scott Barnett Swaney
IPC分类号： G06F11/20
CPC分类号： G06F12/0888 , G06F9/30043 , G06F9/3851 , G06F9/3863 , G06F11/1407
摘要： Recovery circuits react to errors in a processor core by waiting for an error-free completion of any pending store-conditional instruction or a cache-inhibited load before ceasing to checkpoint or backup progress of a processor core. Recovery circuits remove the processor core from the logical configuration of the symmetric multiprocessor system, potentially reducing propagation of errors to other parts of the system. The processor core is reset and the checkpointed values may be restored to registers of the processor core. The core processor is allowed not just to resume execution just prior to the instructions that failed to execute correctly the first time, but is allowed to operate in a reduced execution mode for a preprogrammed number of groups. If the preprogrammed number of instruction groups execute without error, the processor core is allowed to resume normal execution.
摘要翻译：恢复电路通过在停止处理器核心的检查点或备份进程之前等待任何挂起的存储条件指令或高速缓存禁止负载的无差错完成来响应处理器内核中的错误。恢复电路将处理器核从对称多处理器系统的逻辑配置中移除，可能会将错误的传播减少到系统的其他部分。处理器内核被复位，检查点值可以恢复到处理器内核的寄存器。允许核心处理器不仅在第一次执行失败的指令之前恢复执行，而且允许以预编程的组数减少执行模式运行。如果指令组的预编程数量无错误地执行，则允许处理器内核恢复正常执行。

4. 发明授权

US07467325B2 Processor instruction retry recovery 有权
标题翻译：处理器指令重试恢复
公开(公告)号：US07467325B2
公开(公告)日：2008-12-16
申请号：US11055258
申请日：2005-02-10
申请人： Susan Elizabeth Eisen , Hung Qui Le , Michael James Mack , Dung Quoc Nguyen , Jose Angel Paredes , Scott Barnett Swaney
发明人： Susan Elizabeth Eisen , Hung Qui Le , Michael James Mack , Dung Quoc Nguyen , Jose Angel Paredes , Scott Barnett Swaney
IPC分类号： G06F11/00
CPC分类号： G06F12/0888 , G06F9/30043 , G06F9/3851 , G06F9/3863 , G06F11/1407
摘要： Recovery circuits react to errors in a processor core by waiting for an error-free completion of any pending store-conditional instruction or a cache-inhibited load before ceasing to checkpoint or backup progress of a processor core. Recovery circuits remove the processor core from the logical configuration of the symmetric multiprocessor system, potentially reducing propagation of errors to other parts of the system. The processor core is reset and the checkpointed values may be restored to registers of the processor core. The core processor is allowed not just to resume execution just prior to the instructions that failed to execute correctly the first time, but is allowed to operate in a reduced execution mode for a preprogrammed number of groups. If the preprogrammed number of instruction groups execute without error, the processor core is allowed to resume normal execution.
摘要翻译：恢复电路通过在停止处理器核心的检查点或备份进程之前等待任何挂起的存储条件指令或高速缓存禁止负载的无差错完成来响应处理器内核中的错误。恢复电路将处理器核从对称多处理器系统的逻辑配置中移除，可能会将错误的传播减少到系统的其他部分。处理器内核被复位，检查点值可以恢复到处理器内核的寄存器。允许核心处理器不仅在第一次执行失败的指令之前恢复执行，而且允许以预编程的组数减少执行模式运行。如果指令组的预编程数量无错误地执行，则允许处理器内核恢复正常执行。

5. 发明授权

US07418541B2 Method for indirect access to a support interface for memory-mapped resources to reduce system connectivity from out-of-band support processor 失效
标题翻译：用于间接访问内存映射资源的支持接口以减少带外支持处理器的系统连接的方法
公开(公告)号：US07418541B2
公开(公告)日：2008-08-26
申请号：US11055404
申请日：2005-02-10
申请人： James Stephen Fields, Jr. , Paul Frank Lecocq , Brian Chan Monwai , Thomas Pflueger , Kevin Franklin Reick , Timothy M. Skergan , Scott Barnett Swaney
发明人： James Stephen Fields, Jr. , Paul Frank Lecocq , Brian Chan Monwai , Thomas Pflueger , Kevin Franklin Reick , Timothy M. Skergan , Scott Barnett Swaney
IPC分类号： G06F12/00 , G05B13/02 , G06F15/00 , G06F15/76
CPC分类号： G06F15/7842
摘要： A method and apparatus are provided for a support interface for memory-mapped resources. A support processor sends a sequence of commands over and FSI interface to a memory-mapped support interface on a processor chip. The memory-mapped support interface updates memory, memory-mapped registers or memory-mapped resources. The interface uses fabric packet generation logic to generate a single command packet in a protocol for the coherency fabric which consists of an address, command and/or data. Fabric commands are converted to FSI protocol and forwarded to attached support chips to access the memory-mapped resource, and responses from the support chips are converted back to fabric response packets. Fabric snoop logic monitors the coherency fabric and decodes responses for packets previously sent by fabric packet generation logic. The fabric snoop logic updates status register and/or writes response data to a read data register. The system also reports any errors that are encountered.
摘要翻译：提供了一种用于存储器映射资源的支持接口的方法和装置。支持处理器将一系列命令和FSI接口发送到处理器芯片上的存储器映射支持接口。内存映射支持接口更新内存，内存映射寄存器或内存映射资源。该接口使用结构数据包生成逻辑在由地址，命令和/或数据组成的一致性结构的协议中生成单个命令分组。结构命令转换为FSI协议，并转发到附加的支持芯片以访问存储器映射的资源，并且来自支持芯片的响应被转换回到结构响应分组。 Fabric监听逻辑监视一致性结构，并解码先前由Fabric数据包生成逻辑发送的数据包的响应。织物窥探逻辑更新状态寄存器和/或将响应数据写入读取数据寄存器。系统还报告遇到的任何错误。

6. 发明授权

US08090929B2 Generating clock signals for coupled ASIC chips in processor interface with X and Y logic operable in functional and scanning modes 有权
标题翻译：在处理器接口中为耦合ASIC芯片生成时钟信号，X和Y逻辑可在功能和扫描模式下运行
公开(公告)号：US08090929B2
公开(公告)日：2012-01-03
申请号：US12236551
申请日：2008-09-24
申请人： Jeffrey A. Magee , Timothy Gerard McNamara , Walter Niklaus , Scott Barnett Swaney , Tobias Webel
发明人： Jeffrey A. Magee , Timothy Gerard McNamara , Walter Niklaus , Scott Barnett Swaney , Tobias Webel
IPC分类号： G06F1/04
CPC分类号： G06F9/3869 , G01R31/318533 , G01R31/318558
摘要： A digital system and method of operating the same. The system comprises a processor chip including a first elastic interface domain, wherein the first elastic interface domain comprises a first processor X logic and a first processor Y logic, wherein the first processor X and Y logic comprise first X and Y latches, respectively; and a first ASIC chip electrically coupled to the processor chip, wherein the first processor X and Y logics are configured to be simultaneously in a functional mode, wherein the first processor X logic is configured to switch from the functional mode to a scanning mode while the first processor Y logic remains in the functional mode, and wherein in response to the first processor Y logic being in the functional mode, the first processor Y logic is configured to generate a first reference ASIC clock signal to the first ASIC chip.
摘要翻译：数字系统及其操作方法。该系统包括包括第一弹性接口域的处理器芯片，其中第一弹性接口域包括第一处理器X逻辑和第一处理器Y逻辑，其中第一处理器X和Y逻辑分别包括第一X和Y锁存器; 以及电耦合到所述处理器芯片的第一ASIC芯片，其中所述第一处理器X和Y逻辑被配置为同时处于功能模式，其中所述第一处理器X逻辑被配置为从所述功能模式切换到扫描模式，而第一处理器Y逻辑保持在功能模式中，并且其中响应于第一处理器Y逻辑处于功能模式，第一处理器Y逻辑被配置为产生到第一ASIC芯片的第一参考ASIC时钟信号。

7. 发明授权

US07966536B2 Method and apparatus for automatic scan completion in the event of a system checkstop 失效
标题翻译：在系统检查停止的情况下自动扫描完成的方法和装置
公开(公告)号：US07966536B2
公开(公告)日：2011-06-21
申请号：US12101208
申请日：2008-04-11
申请人： Ralf Ludewig , Walter Niklaus , Dietmar Schmunkamp , Scott Barnett Swaney , Tobias Webel
发明人： Ralf Ludewig , Walter Niklaus , Dietmar Schmunkamp , Scott Barnett Swaney , Tobias Webel
IPC分类号： G01R31/28 , G06F11/00
CPC分类号： G06F11/0784 , G06F11/0706 , G06F11/0778 , G06F11/2236
摘要： A method for automatic scan completion in the event of a system checkstop in a processor. The processor includes: a processor register; a millicode interface connected between the processor register and a checkstop scan controller; a checkstop logic circuit connected between the checkstop scan controller and a checkstop scan engine; and a scan chain engine and a scan chain connected to the checkstop scan engine. The method includes (a) upon occurrence of a checkstop serially reading data from a processor register and serially writing the data to latches of a scan chain register; and (b) upon occurrence of a system checkstop during (a), stopping the reading and writing and moving data sent before the system checkstop from latches of the scan chain where the data was stored when the system checkstop occurred to latches where the data would have been stored if the system checkstop had not occurred.
摘要翻译：在处理器中系统检查停止时自动扫描完成的方法。处理器包括：处理器寄存器; 连接在处理器寄存器和检查站扫描控制器之间的millicode接口; 连接在止回扫描控制器和检查停止扫描引擎之间的止回逻辑电路; 以及连接到检查停止扫描引擎的扫描链引擎和扫描链。该方法包括（a）在发生从处理器寄存器串行读取数据的检查站并将数据串行写入扫描链寄存器的锁存器时; 和（b）在（a）期间发生系统检查停止时，停止在系统检查停止期间发送的读取和写入数据，并且在发生系统检查停止时存储数据的扫描链的锁存器中移动数据，以锁定数据将在哪里如果没有发生系统检查停止，则已存储。

8. 发明授权

US07707452B2 Recovering from errors in a data processing system 失效
标题翻译：从数据处理系统的错误中恢复
公开(公告)号：US07707452B2
公开(公告)日：2010-04-27
申请号：US12135839
申请日：2008-06-09
申请人： Edgar Rolando Cordero , James Stephen Fields, Jr. , Kevin Charles Gower , Eric Eugene Retter , Scott Barnett Swaney
发明人： Edgar Rolando Cordero , James Stephen Fields, Jr. , Kevin Charles Gower , Eric Eugene Retter , Scott Barnett Swaney
IPC分类号： G06F11/00
CPC分类号： G06F11/1441 , G06F11/2028
摘要： A system and method of recovering from errors in a data processing system. The data processing system includes one or more processor cores coupled to one or more memory controllers. The one or more memory controllers include at least a first memory interface coupled to a first memory and at least a second memory interface coupled to a second memory. In response to determining an error has been detected in the first memory, access to the first memory via the first memory interface is inhibited. Also, the first memory interface is locally restarted without restarting the second memory interface.
摘要翻译：一种从数据处理系统中的错误中恢复的系统和方法。数据处理系统包括耦合到一个或多个存储器控制器的一个或多个处理器核心。一个或多个存储器控制器至少包括耦合到第一存储器的第一存储器接口和耦合到第二存储器的至少第二存储器接口。响应于确定在第一存储器中检测到错误，禁止经由第一存储器接口访问第一存储器。此外，第一个存储器接口在本地重新启动，而不重新启动第二个存储器接口。

9. 发明授权

US07624318B2 Method and apparatus for automatically identifying multiple combinations of operational and non-operational components on integrated circuit chips with a single part number 失效
标题翻译：用于自动识别具有单个部件号的集成电路芯片上的操作和非操作部件的多个组合的方法和装置
公开(公告)号：US07624318B2
公开(公告)日：2009-11-24
申请号：US11236449
申请日：2005-09-27
申请人： Andreas Bieswanger , Herwig Elfering , James Stephen Fields, Jr. , Andrew J. Geissler , Alan Hlava , Scott Barnett Swaney
发明人： Andreas Bieswanger , Herwig Elfering , James Stephen Fields, Jr. , Andrew J. Geissler , Alan Hlava , Scott Barnett Swaney
IPC分类号： G11C29/00 , G06F11/00 , G01R31/28
CPC分类号： G01R31/2894
摘要： A computer implemented method, a data processing system, and a computer usable program code for automatically identifying multiple combinations of operational and non-operational components with a single part number. A non-volatile storage is provided on a part, wherein the part includes a plurality of sub-components. Unavailable sub-components in the plurality of sub-components are identified based on a series of testing to form identified unavailable sub-components. Information of the identified unavailable sub-components is stored into the non-volatile storage.
摘要翻译：计算机实现的方法，数据处理系统和用于使用单个部件号自动识别操作和非操作部件的多个组合的计算机可用程序代码。在部件上提供非易失性存储器，其中该部件包括多个子部件。基于一系列测试来识别多个子组件中不可用的子组件，以形成所识别的不可用子组件。所识别的不可用子组件的信息被存储到非易失性存储器中。

10. 发明授权

US07568138B2 Method to prevent firmware defects from disturbing logic clocks to improve system reliability 有权
标题翻译：防止固件缺陷干扰逻辑时钟以提高系统可靠性的方法
公开(公告)号：US07568138B2
公开(公告)日：2009-07-28
申请号：US11459942
申请日：2006-07-26
申请人： Adolf Martens , Walter Niklaus , Dietmar Schmunkamp , Scott Barnett Swaney , Ching-Lung L. Tong , Tobias Webel
发明人： Adolf Martens , Walter Niklaus , Dietmar Schmunkamp , Scott Barnett Swaney , Ching-Lung L. Tong , Tobias Webel
IPC分类号： G01R31/28
CPC分类号： G06F11/2236 , G01R31/318569
摘要： A computer implemented method and data processing system are provided for preventing firmware defects from disrupting logic clocks. In response to a firmware interface requesting a scan operation for a functional unit, protection logic allows a scan enable to activate to the functional unit only if the logic clocks are stopped to that functional unit, otherwise the scan enable is not activated, an error is indicated, and an interrupt is presented to firmware. Also, in response to a command from a firmware interface to stop the logic clocks to a functional unit, protection logic allows the clocks to be stopped to the functional unit only if the functional unit is already indicating a catastrophic error, otherwise the clocks are not stopped, an error is indicated, and an interrupt is presented to firmware.
摘要翻译：提供了一种计算机实现的方法和数据处理系统，用于防止固件缺陷中断逻辑时钟。响应于对功能单元请求扫描操作的固件接口，只有当逻辑时钟停止到该功能单元时，保护逻辑允许扫描使能才能激活到功能单元，否则扫描使能不被激活，错误是指示，并向固件呈现中断。另外，响应于来自固件界面的命令将逻辑时钟停止到功能单元，保护逻辑允许时钟停止到功能单元，只有当功能单元已经指示灾难性错误时，否则时钟不是停止，指示错误，并向固件提供中断。

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