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1. 发明申请

US20110131394A1 APPARATUS AND METHOD FOR USING BRANCH PREDICTION HEURISTICS FOR DETERMINATION OF TRACE FORMATION READINESS 失效
标题翻译：使用分支预测机制确定跟踪形成准备的装置和方法
公开(公告)号：US20110131394A1
公开(公告)日：2011-06-02
申请号：US13016144
申请日：2011-01-28
申请人： Gordon T. Davis , Richard W. Doing , John D. Jabusch , M V V Anil Krishna , Brett Olsson , Eric F. Robinson , Sumedh W. Sathaye , Jeffrey R. Summers
发明人： Gordon T. Davis , Richard W. Doing , John D. Jabusch , M V V Anil Krishna , Brett Olsson , Eric F. Robinson , Sumedh W. Sathaye , Jeffrey R. Summers
IPC分类号： G06F9/40 , G06F12/08
CPC分类号： G06F12/0862 , G06F12/0875 , G06F2212/6028
摘要： A single unified level one instruction(s) cache in which some lines may contain traces and other lines in the same congruence class may contain blocks of instruction(s) consistent with conventional cache lines. Formation of trace lines in the cache is delayed on initial operation of the system to assure quality of the trace lines stored.
摘要翻译：单个统一的一级指令高速缓存，其中一些行可以包含跟踪和同一同余类中的其他行可以包含与常规高速缓存行一致的指令块。缓存中的跟踪行的形成在系统的初始操作中被延迟，以确保存储的跟踪线的质量。

2. 发明申请

US20100262806A1 Tracking Effective Addresses in an Out-of-Order Processor 有权
标题翻译：跟踪无序处理器中的有效地址
公开(公告)号：US20100262806A1
公开(公告)日：2010-10-14
申请号：US12422595
申请日：2009-04-13
申请人： Richard W. Doing , Susan E. Eisen , David S. Levitan , Kevin N. Magill , Brian R. Mestan , Balaram Sinharoy , Benjamin W. Stolt , Jeffrey R. Summers , Albert J. Van Norstrand, JR.
发明人： Richard W. Doing , Susan E. Eisen , David S. Levitan , Kevin N. Magill , Brian R. Mestan , Balaram Sinharoy , Benjamin W. Stolt , Jeffrey R. Summers , Albert J. Van Norstrand, JR.
IPC分类号： G06F9/30
CPC分类号： G06F9/3802 , G06F9/322 , G06F9/3806 , G06F9/3853 , G06F9/3855 , G06F9/3861
摘要： Mechanisms, in a data processing system, are provided for tracking effective addresses through a processor pipeline of the data processing system. The mechanisms comprise logic for fetching an instruction from an instruction cache and associating, by an effective address table logic in the data processing system, an entry in an effective address table (EAT) data structure with the fetched instruction. The mechanisms further comprise logic for associating an effective address tag (eatag) with the fetched instruction, the eatag comprising a base eatag that points to the entry in the EAT and an eatag offset. Moreover, the mechanisms comprise logic for processing the instruction through the processor pipeline by processing the eatag.
摘要翻译：在数据处理系统中提供用于通过数据处理系统的处理器流水线跟踪有效地址的机制。这些机制包括用于从指令高速缓存取出指令的逻辑，并通过数据处理系统中的有效地址表逻辑将有效地址表（EAT）数据结构中的条目与获取的指令相关联。所述机制还包括用于将有效地址标签（eatag）与所述获取的指令相关联的逻辑，所述标签包括指向所述EAT中的条目的基本食品，以及食品标签偏移量。此外，这些机制包括通过处理eatag来处理通过处理器管线的指令的逻辑。

3. 发明申请

US20100257340A1 System and Method for Group Formation with Multiple Taken Branches Per Group 失效
标题翻译：每组多组分组形成的系统和方法
公开(公告)号：US20100257340A1
公开(公告)日：2010-10-07
申请号：US12417798
申请日：2009-04-03
申请人： Richard William Doing , Kevin Neal Magil , Balaram Sinharoy , Jeffrey R. Summers , James A. Van Norstrand, JR.
发明人： Richard William Doing , Kevin Neal Magil , Balaram Sinharoy , Jeffrey R. Summers , James A. Van Norstrand, JR.
IPC分类号： G06F9/30
CPC分类号： G06F9/30145 , G06F9/3802 , G06F9/3814 , G06F9/382 , G06F9/3853
摘要： Disclosed are a method and a system for grouping processor instructions for execution by a processor, where the group of processor instructions includes at least two branch processor instructions. In one or more embodiments, an instruction buffer can decouple an instruction fetch operation from an instruction decode operation by storing fetched processor instructions in the instruction buffer until the fetched processor instructions are ready to be decoded. Group formation can involve removing processor instructions from the instruction buffer and routing the processor instruction to latches that convey the processor instructions to decoders. Processor instructions that are removed from instruction buffer in a single clock cycle can be called a group of processor instructions. In one or more embodiments, the first instruction in the group must be the oldest instruction in the instruction buffer and instructions must be removed from the instruction buffer ordered from oldest to youngest.
摘要翻译：公开了一种用于将处理器指令分组以由处理器执行的方法和系统，其中处理器指令组包括至少两个分支处理器指令。在一个或多个实施例中，指令缓冲器可以通过在指令缓冲器中存储获取的处理器指令直到所读出的处理器指令准备解码，从而将指令提取操作与指令解码操作分离。组形成可以涉及从指令缓冲器中移除处理器指令并将处理器指令路由到将处理器指令传送给解码器的锁存器。在单个时钟周期内从指令缓冲区中删除的处理器指令可以称为一组处理器指令。在一个或多个实施例中，组中的第一指令必须是指令缓冲器中的最早的指令，并且必须从从最老到最小的指令缓冲器中移除指令。

4. 发明授权

US07779232B2 Method and apparatus for dynamically managing instruction buffer depths for non-predicted branches 失效
标题翻译：用于动态管理非预测分支的指令缓冲区深度的方法和装置
公开(公告)号：US07779232B2
公开(公告)日：2010-08-17
申请号：US11845838
申请日：2007-08-28
申请人： Richard W. Doing , Michael O. Klett , Kevin N. Magill , Brian R. Mestan , David Mui , Balaram Sinharoy , Jeffrey R. Summers
发明人： Richard W. Doing , Michael O. Klett , Kevin N. Magill , Brian R. Mestan , David Mui , Balaram Sinharoy , Jeffrey R. Summers
IPC分类号： G06F9/42 , G06F9/312
CPC分类号： G06F9/3804
摘要： A method and apparatus for dynamically managing instruction buffer depths for non-predicted branches reduces wasted energy and resources associated with low confidence branch prediction conditions. A portion of the instruction buffer for a instruction thread is allocated for storing predicted branch instruction streams and another portion, which may be zero-sized during high prediction confidence conditions, is allocated to the non-predicted branch instruction stream. The size of the buffers is adjusted dynamically in conformity with an on-going prediction confidence that provides a measure of how well branch prediction mechanisms are working for a given instruction thread. An alternate instruction fetch address table can be maintained and multiplexed with the main fetch address register for addressing the instruction cache, so that the instruction stream can be quickly shifted to the non-predicted path when a branch instruction is resolved to the non-predicted path.
摘要翻译：用于动态管理非预测分支的指令缓冲器深度的方法和装置减少与低置信度分支预测条件相关联的浪费的能量和资源。分配用于指令线程的指令缓冲器的一部分用于存储预测的分支指令流，并且在高预测置信度条件下可以为零大小的另一部分被分配给非预测分支指令流。缓冲区的大小根据正在进行的预测置信度动态调整，提供了分支预测机制对给定指令线程的工作原理的测量。替代指令提取地址表可以与主提取地址寄存器保持多路复用，用于对指令高速缓存进行寻址，使得当分支指令被解析为非预测路径时，可以将指令流快速移位到非预测路径。

5. 发明申请

US20090249349A1 Power-Efficient Thread Priority Enablement 有权
标题翻译：高效的线程优先级启用
公开(公告)号：US20090249349A1
公开(公告)日：2009-10-01
申请号：US12059576
申请日：2008-03-31
申请人： Pradip Bose , Alper Buyuktosunoglu , Richard James Eickemeyer , Susan Elizabeth Eisen , Michael Stephen Floyd , Hans Mikael Jacobson , Jeffrey R. Summers
发明人： Pradip Bose , Alper Buyuktosunoglu , Richard James Eickemeyer , Susan Elizabeth Eisen , Michael Stephen Floyd , Hans Mikael Jacobson , Jeffrey R. Summers
IPC分类号： G06F9/46
CPC分类号： G06F9/4893 , Y02D10/24
摘要： A mechanism for controlling instruction fetch and dispatch thread priority settings in a thread switch control register for reducing the occurrence of balance flushes and dispatch flushes for increased power performance of a simultaneous multi-threading data processing system. To achieve a target power efficiency mode of a processor, the illustrative embodiments receive an instruction or command from a higher-level system control to set a current power consumption of the processor. The illustrative embodiments determine a target power efficiency mode for the processor. Once the target power mode is determined, the illustrative embodiments update thread priority settings in a thread switch control register for an executing thread to control balance flush speculation and dispatch flush speculation to achieve the target power efficiency mode.
摘要翻译：一种用于控制在线程切换控制寄存器中的指令获取和调度线程优先级设置的机制，用于减少平衡刷新的发生和调度刷新以提高同时多线程数据处理系统的功率性能。为了实现处理器的目标功率效率模式，说明性实施例从较高级系统控制器接收指令或命令以设置处理器的当前功耗。说明性实施例确定了处理器的目标功率效率模式。一旦确定了目标功率模式，则说明性实施例更新用于执行线程的线程切换控制寄存器中的线程优先级设置，以控制平衡冲突推测和调度冲销推测以实现目标功率效率模式。

6. 发明授权

US07467366B2 Method for generating a timing path software monitor for identifying a critical timing path in hardware devices coupled between components 失效
标题翻译：用于生成用于识别耦合在组件之间的硬件设备中的关键定时路径的定时路径软件监视器的方法
公开(公告)号：US07467366B2
公开(公告)日：2008-12-16
申请号：US11535203
申请日：2006-09-26
申请人： John B. Blankenship , Kevin N. Magill , Jeffrey R. Summers , Anup Wadia
发明人： John B. Blankenship , Kevin N. Magill , Jeffrey R. Summers , Anup Wadia
IPC分类号： G06F9/45 , G06F17/50
CPC分类号： G06F17/5031
摘要： A method for generating a timing path software monitor for identifying a critical timing path in hardware devices coupled between first and second components is provided. The method includes generating a static timing report associated with the hardware devices. The static timing report has names of the hardware devices and wire names associated with wires coupled to the hardware devices. The method further includes automatically generating the timing path software monitor based on the static timing report that monitors binary values associated with the wire names at a first clock cycle and a transition of binary values associated with the wire names during a second clock cycle after the first clock cycle. The timing path software monitor indicates a critical timing path is identified when the transition of one of the binary values received by the second component occurs during the second clock cycle.
摘要翻译：提供了一种用于生成用于识别耦合在第一和第二组件之间的硬件设备中的关键定时路径的定时路径软件监视器的方法。该方法包括生成与硬件设备相关联的静态定时报告。静态定时报告具有与耦合到硬件设备的线路相关联的硬件设备和线名称。该方法还包括基于静态定时报告自动生成定时路径软件监视器，静态定时报告在第一时钟周期监视与线名称相关联的二进制值，以及在第一时钟周期之后的第二时钟周期期间与线名相关联的二进制值的转变时钟周期。定时路径软件监视器指示当在第二时钟周期期间发生由第二分量接收的二进制值之一的转换时，识别关键定时路径。

7. 发明申请

US20080159176A1 Structure for Preventing Starvation in a Slotted Ring Data Communications Network 失效
标题翻译：在一个开槽环数据通信网络中预防饥饿的结构
公开(公告)号：US20080159176A1
公开(公告)日：2008-07-03
申请号：US12042612
申请日：2008-03-05
申请人： Timothy Hume Heil , Michael Steven Siegel , Jeffrey R. Summers , Steven Paul VanderWiel
发明人： Timothy Hume Heil , Michael Steven Siegel , Jeffrey R. Summers , Steven Paul VanderWiel
IPC分类号： H04L12/28
CPC分类号： H04L12/4035 , H04L12/66
摘要： A design structure is provided for a slotted ring network, in which a node may transmit a non-renewable slot reservation with any unreserved slot. The reservation restricts other nodes from transmitting a new packet in the slot. When the slot returns around the ring to the reserving node, the slot will be available. Preferably, reservation is made responsive to a starvation condition in the reserving node, which may be detected in any of various ways. In an optional enhancement, a reservation identifies the reserving node, and another node on the ring is free to transmit a new packet in the reserved slot if the new packet will reach its destination at or before the reserving node, and thus will not interfere with the reservation.
摘要翻译：为时隙环网提供了一种设计结构，其中节点可以用任何未预留的时隙发送不可再生的时隙预留。该预约限制其他节点在时隙中发送新的分组。当插槽返回环到保留节点时，插槽将可用。优选地，响应于预留节点中的饥饿状况做出预约，其可以以各种方式中的任一种来检测。在可选增强中，预留识别预留节点，并且如果新分组将在保留节点处或之前到达其目的地，则环上的另一个节点可以自由地在保留时隙中发送新分组，并且因此不会干扰预订。

8. 发明申请

US20080077895A1 METHOD FOR GENERATING A TIMING PATH SOFTWARE MONITOR FOR IDENTIFYING A CRITICAL TIMING PATH IN HARDWARE DEVICES COUPLED BETWEEN COMPONENTS 失效
标题翻译：用于识别在组件之间耦合的硬件设备中的关键时序路径的定时路径软件监视器的方法
公开(公告)号：US20080077895A1
公开(公告)日：2008-03-27
申请号：US11535203
申请日：2006-09-26
申请人： John B. Blankenship , Kevin N. Magill , Jeffrey R. Summers , Anup Wadia
发明人： John B. Blankenship , Kevin N. Magill , Jeffrey R. Summers , Anup Wadia
IPC分类号： G06F17/50 , G06F9/45
CPC分类号： G06F17/5031
摘要： A method for generating a timing path software monitor for identifying a critical timing path in hardware devices coupled between first and second components is provided. The method includes generating a static timing report associated with the hardware devices. The static timing report has names of the hardware devices and wire names associated with wires coupled to the hardware devices. The method further includes automatically generating the timing path software monitor based on the static timing report that monitors binary values associated with the wire names at a first clock cycle and a transition of binary values associated with the wire names during a second clock cycle after the first clock cycle. The timing path software monitor indicates a critical timing path is identified when the transition of one of the binary values received by the second component occurs during the second clock cycle.
摘要翻译：提供了一种用于生成用于识别耦合在第一和第二组件之间的硬件设备中的关键定时路径的定时路径软件监视器的方法。该方法包括生成与硬件设备相关联的静态定时报告。静态定时报告具有与耦合到硬件设备的线路相关联的硬件设备和线名称。该方法还包括基于静态定时报告自动生成定时路径软件监视器，静态定时报告在第一时钟周期监视与线名称相关联的二进制值，以及在第一时钟周期之后的第二时钟周期期间与线名相关联的二进制值的转变时钟周期。定时路径软件监视器指示当在第二时钟周期期间发生由第二分量接收的二进制值之一的转换时，识别关键定时路径。

9. 发明授权

US07934081B2 Apparatus and method for using branch prediction heuristics for determination of trace formation readiness 失效
标题翻译：使用分支预测启发式方法确定痕量形成准备的装置和方法
公开(公告)号：US07934081B2
公开(公告)日：2011-04-26
申请号：US11538831
申请日：2006-10-05
申请人： Gordon T. Davis , Richard W. Doing , John D. Jabusch , M V V Anil Krishna , Brett Olsson , Eric F. Robinson , Sumedh W. Sathaye , Jeffrey R. Summers
发明人： Gordon T. Davis , Richard W. Doing , John D. Jabusch , M V V Anil Krishna , Brett Olsson , Eric F. Robinson , Sumedh W. Sathaye , Jeffrey R. Summers
IPC分类号： G06F9/40 , G06F12/08
CPC分类号： G06F12/0862 , G06F12/0875 , G06F2212/6028
摘要： A single unified level one instruction(s) cache in which some lines may contain traces and other lines in the same congruence class may contain blocks of instruction(s) consistent with conventional cache lines. Formation of trace lines in the cache is delayed on initial operation of the system to assure quality of the trace lines stored.
摘要翻译：单个统一的一级指令高速缓存，其中一些行可以包含跟踪和同一同余类中的其他行可以包含与常规高速缓存行一致的指令块。缓存中的跟踪行的形成在系统的初始操作中被延迟，以确保存储的跟踪线的质量。

10. 发明申请

US20100262813A1 Detecting and Handling Short Forward Branch Conversion Candidates 审中-公开
标题翻译：检测和处理短期分支转换候选人
公开(公告)号：US20100262813A1
公开(公告)日：2010-10-14
申请号：US12423608
申请日：2009-04-14
申请人： Mary D. Brown , Richard W. Doing , Kevin N. Magill , Brian R. Mestan , Wolfram M. Sauer , Balaram Sinharoy , Jeffrey R. Summers , Albert J. Van Norstrand, JR.
发明人： Mary D. Brown , Richard W. Doing , Kevin N. Magill , Brian R. Mestan , Wolfram M. Sauer , Balaram Sinharoy , Jeffrey R. Summers , Albert J. Van Norstrand, JR.
IPC分类号： G06F9/38
CPC分类号： G06F9/30003 , G06F8/433 , G06F9/30058 , G06F9/30072 , G06F9/3017 , G06F9/30174 , G06F9/3844 , G06F9/3846 , G06F9/3855
摘要： Mechanisms, in a processor, are provided for detecting and handling short forward branch conversion candidates. The mechanisms identify a conditional branch in the computer code and determine if the short forward conditional branch is to be converted to a non-branching conditional sequence of instructions. Moreover, the mechanisms convert the conditional branch to a non-branching conditional sequence of instructions comprising a resolve instruction and one or more conditional instructions dependent on the resolve instruction. In addition, the mechanisms execute the non-branching conditional sequence of instructions in place of the conditional branch in the computer code and generate an output of the computer code based on the execution of the non-branching conditional sequence of instructions.
摘要翻译：在处理器中提供用于检测和处理短前进分支转换候选的机制。机制识别计算机代码中的条件分支，并确定短向前向条件分支是否要转换为非分支条件指令序列。此外，机制将条件分支转换为包括解决指令和取决于解析指令的一个或多个条件指令的非分支条件指令序列。此外，这些机制代替计算机代码中的条件分支执行非分支条件指令序列，并且基于非分支条件指令序列的执行生成计算机代码的输出。

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