专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明授权

US09245082B2 High-speed shape-based router 有权
标题翻译：高速形状路由器
公开(公告)号：US09245082B2
公开(公告)日：2016-01-26
申请号：US11425504
申请日：2006-06-21
申请人： Jeremy Birch
发明人： Jeremy Birch
IPC分类号： G06F17/50
CPC分类号： G06F17/5077 , Y02A10/46
摘要： A high-speed shape-based router is applicable to standard-cell digital designs, chip-level-block assembly designs, and other styles of design. In a flow of the invention, the technique establishes an initial structure for each net to be routed. Nets or parts of them are ordered. Each part of the net may be routed using a spine routing search, depth first search, or a space flood search, or any combination of these. Where sections fail or an error occurs, conflicts are identified, and the technique tries routing again.
摘要翻译：基于高速形状的路由器适用于标准单元数字设计，芯片级块装配设计和其他设计风格。在本发明的流程中，该技术为要路由的每个网络建立初始结构。网或其中的一部分被订购。网络的每个部分可以使用脊线路由搜索，深度优先搜索或空间洪泛搜索或这些的任何组合来路由。在哪些部分出现故障或发生错误的情况下，会发现冲突，并且技术再次尝试路由。

2. 发明授权

US08332805B1 Automatically routing nets according to parasitic constraint rules 有权
标题翻译：根据寄生约束规则自动布线网络
公开(公告)号：US08332805B1
公开(公告)日：2012-12-11
申请号：US13180256
申请日：2011-07-11
申请人： Jeremy Birch , Mark Waller , Mark Williams , Graham Balsdon , Fumiaki Sato , Tim Parker
发明人： Jeremy Birch , Mark Waller , Mark Williams , Graham Balsdon , Fumiaki Sato , Tim Parker
IPC分类号： G06F17/50
CPC分类号： G06F17/5077
摘要： A system of automatically routing interconnect of a integrated circuit design while taking into consideration the parasitic issues of the wiring as it is created. The system will be able to select an appropriate wiring pattern so that signals meet their performance requirements.
摘要翻译：一种自动布线集成电路设计互连的系统，同时考虑到它所产生的布线的寄生问题。该系统将能够选择合适的布线图案，使信号满足其性能要求。

3. 发明授权

US08099700B1 Automatic integrated circuit routing using spines 有权
标题翻译：使用脊柱自动集成电路布线
公开(公告)号：US08099700B1
公开(公告)日：2012-01-17
申请号：US11838726
申请日：2007-08-14
申请人： Mark Waller , Tim Parker , Mark Williams , Jeremy Birch , Graham Balsdon , Fumiako Sato
发明人： Mark Waller , Tim Parker , Mark Williams , Jeremy Birch , Graham Balsdon , Fumiako Sato
IPC分类号： G06F17/50
CPC分类号： G06F17/5077
摘要： A method and technique of routing interconnects of an integrated circuit providing improved routing quality. In an embodiment of the invention, the technique provides linear spine interconnect routing. In memory array blocks, such as in DRAM and SRAM memory designs, connected pins are generally separated by large distances in a first direction and small distances in a second direction, or a spine or channel region. A route area is defined within the spine region. In one embodiment, obstacles in the route area are identified and corresponding forbidden areas are demarcated. The linear spine interconnect is routed in the first direction within the route area while avoiding the forbidden areas. Pins are connected to the spine interconnect by stitching interconnects. Stitching interconnects are generally routed in the second direction.
摘要翻译：提供提供改进的路由质量的集成电路的互连路由的方法和技术。在本发明的一个实施例中，该技术提供线性脊柱互连路由。在诸如DRAM和SRAM存储器设计的存储器阵列块中，连接的引脚通常在第一方向上分开大距离，在第二方向或脊柱或通道区域上分开小距离。在脊椎区域内定义路线区域。在一个实施例中，识别路线区域中的障碍物并且划定对应的禁止区域。线性脊线互连在路线区域内沿第一方向路由，同时避免禁止区域。引脚通过缝合互连连接到脊柱互连。缝合互连通常沿第二方向布线。

4. 发明授权

US08095903B2 Automatically routing nets with variable spacing 有权
标题翻译：自动路由具有可变间距的网络
公开(公告)号：US08095903B2
公开(公告)日：2012-01-10
申请号：US11555202
申请日：2006-10-31
申请人： Jeremy Birch , Mark Waller , Graham Balsdon
发明人： Jeremy Birch , Mark Waller , Graham Balsdon
IPC分类号： G06F17/50
CPC分类号： G06F17/5077
摘要： A technique will automatically route interconnect of an integrated circuit and adjust spacing between tracks or interconnect in order to improve performance or reduce electromigration effects. By increasing spacing between certain tracks or moving tracks, performance can improve because a track will be more noise immunity from nearby tracks on the same layer or on different layers. The automatic router will adjust spacing between tracks depending on one or more factors. These factors may include current associated with a track, width of a track, capacitance, inductance, and electromigration. In a specific implementation, the technique uses a shape-based approach where a grid is not used. The technique may further vary the width of the tracks.
摘要翻译：一种技术将自动路由集成电路的互连，并调整磁道或互连之间的间距，以提高性能或减少电迁移效应。通过增加某些轨道或移动轨道之间的间距，性能可以提高，因为轨道将在相同层或不同层上的附近轨道具有更高的抗噪声能力。自动路由器将根据一个或多个因素来调整轨道之间的间距。这些因素可以包括与轨道相关的电流，轨道的宽度，电容，电感和电迁移。在具体实现中，该技术使用基于形状的方法，其中不使用网格。该技术可以进一步改变轨道的宽度。

5. 发明授权

US08479141B1 Automation using spine routing 有权
标题翻译：自动化使用脊柱路由
公开(公告)号：US08479141B1
公开(公告)日：2013-07-02
申请号：US13352232
申请日：2012-01-17
申请人： Mark Waller , Tim Parker , Mark Williams , Jeremy Birch , Graham Balsdon , Fumiako Sato
发明人： Mark Waller , Tim Parker , Mark Williams , Jeremy Birch , Graham Balsdon , Fumiako Sato
IPC分类号： G06F17/50
CPC分类号： G06F17/5077
摘要： A method and technique of routing interconnects of an integrated circuit providing improved routing quality. In an embodiment of the invention, the technique provides linear spine interconnect routing. In memory array blocks, such as in DRAM and SRAM memory designs, connected pins are generally separated by large distances in a first direction and small distances in a second direction, or a spine or channel region. A route area is defined within the spine region. In one embodiment, obstacles in the route area are identified and corresponding forbidden areas are demarcated. The linear spine interconnect is routed in the first direction within the route area while avoiding the forbidden areas. Pins are connected to the spine interconnect by stitching interconnects. Stitching interconnects are generally routed in the second direction.
摘要翻译：提供提供改进的路由质量的集成电路的互连路由的方法和技术。在本发明的一个实施例中，该技术提供线性脊柱互连路由。在诸如DRAM和SRAM存储器设计的存储器阵列块中，连接的引脚通常在第一方向上分开大距离，在第二方向或脊柱或通道区域上分开小距离。在脊椎区域内定义路线区域。在一个实施例中，识别路线区域中的障碍物并且划定对应的禁止区域。线性脊线互连在路线区域内沿第一方向路由，同时避免禁止区域。引脚通过缝合互连连接到脊柱互连。缝合互连通常沿第二方向布线。

6. 发明授权

US08171447B1 Automatically routing nets according to current density rules 有权
标题翻译：根据当前密度规则自动布线网络
公开(公告)号：US08171447B1
公开(公告)日：2012-05-01
申请号：US12408211
申请日：2009-03-20
申请人： Graham Balsdon , Jeremy Birch , Mark Williams , Mark Waller , Tim Parker , Fumiaki Sato
发明人： Graham Balsdon , Jeremy Birch , Mark Williams , Mark Waller , Tim Parker , Fumiaki Sato
IPC分类号： G06F17/50
CPC分类号： G06F17/5077
摘要： A technique will automatically route interconnect of an integrated circuit while taking into consideration current density rules. In an implementation, the technique uses a shape-based approach where a grid is not used. Based on data input including current density and a frequency of each net, the technique will determine the current requirements for each net. In an implementation, the technique forms a Steiner tree for a net, and routs using the Steiner tree. The technique widens nets having greater current requirements; adjacent wiring may be pushed aside to create sufficient space for wider nets.
摘要翻译：一种技术将自动路由集成电路的互连，同时考虑电流密度规则。在实现中，该技术使用基于形状的方法，其中不使用网格。基于数据输入，包括电流密度和每个网络的频率，该技术将确定每个网络的当前要求。在实现中，该技术为网络形成Steiner树，并使用Steiner树进行路由。该技术扩大了具有更大电流要求的网络; 可以将相邻的布线推到一边以产生用于更宽的网的足够的空间。

7. 发明授权

US07373628B1 Method of automatically routing nets using a Steiner tree 有权
标题翻译：使用Steiner树自动路由网络的方法
公开(公告)号：US07373628B1
公开(公告)日：2008-05-13
申请号：US11383673
申请日：2006-05-16
申请人： Graham Balsdon , Jeremy Birch , Mark Williams , Mark Waller , Tim Parker , Fumiaki Sato
发明人： Graham Balsdon , Jeremy Birch , Mark Williams , Mark Waller , Tim Parker , Fumiaki Sato
IPC分类号： G06F17/50
CPC分类号： G06F17/509 , G06F2217/78 , G06F2217/80
摘要： A technique will automatically route interconnect of an integrated circuit. In an implementation, the technique operates on a gridless layout. The technique forms a Steiner tree for a net and routs using the Steiner tree. In a specific embodiment, the technique creates tracks having varying widths.
摘要翻译：一种技术将自动路由集成电路的互连。在一个实现中，该技术在无栅格布局上运行。该技术使用Steiner树形成了一个Steiner树，并使用了Steiner树。在具体实施例中，该技术创建具有不同宽度的轨道。

8. 发明申请

US20070106969A1 Method of Automatically Routing Nets According to Parasitic Constraint Rules 有权
标题翻译：根据寄生约束规则自动路由网络的方法
公开(公告)号：US20070106969A1
公开(公告)日：2007-05-10
申请号：US11164518
申请日：2005-11-28
申请人： Jeremy Birch , Mark Waller , Mark Williams , Graham Balsdon , Fumiaki Sato , Tim Parker
发明人： Jeremy Birch , Mark Waller , Mark Williams , Graham Balsdon , Fumiaki Sato , Tim Parker
IPC分类号： G06F17/50
CPC分类号： G06F17/5077
摘要： A system of automatically routing interconnect of a integrated circuit design while taking into consideration the parasitic issues of the wiring as it is created. The system will be able to select an appropriate wiring pattern so that signals meet their performance requirements.
摘要翻译：一种自动布线集成电路设计互连的系统，同时考虑到它所产生的布线的寄生问题。该系统将能够选择合适的布线图案，使信号满足其性能要求。

9. 发明申请

US20070001841A1 Computer interface system for tracking of radio frequency identification tags 审中-公开
标题翻译：用于跟踪射频识别标签的计算机接口系统
公开(公告)号：US20070001841A1
公开(公告)日：2007-01-04
申请号：US11515532
申请日：2006-09-05
申请人： Joseph Anders , Jeremy Birch , Bryan Wilson , Marty Logsdon
发明人： Joseph Anders , Jeremy Birch , Bryan Wilson , Marty Logsdon
IPC分类号： G08B1/08 , H04Q7/00
CPC分类号： G06Q10/08
摘要： A method for operating with multiple protocols for handling communications comprising the steps of obtaining information from sensors and related input devices utilizing specialized tamper resistant passive transceivers working with active pulse type transceivers to create historical maps of information on people or objects. This includes steps of: a) identifying recording information, b) sending and receiving prompts, c) associating the call with timers, d) monitoring passive transceivers with low level diagnostic information, e) monitoring the transceivers with voice recognition software, f) recording associated data, g) identifying the users, the key words or phrases within the recorded data, h) naming the recording and i) saving the data in a protected format.
摘要翻译：一种用于处理通信的多种协议的方法，包括以下步骤：利用与主动脉冲型收发器一起工作的专门的防篡改无源收发器从传感器和相关输入设备获取信息，以创建关于人或物体的信息的历史地图。这包括以下步骤：a）识别记录信息，b）发送和接收提示，c）将呼叫与定时器相关联，d）用低级诊断信息监视无源收发器，e）使用语音识别软件监视收发器，f）记录相关数据，g）识别用户，记录数据内的关键词或短语，h）命名记录，i）以受保护格式保存数据。

10. 发明申请

US20120110539A1 Automatically Routing Nets with Variable Spacing 有权
标题翻译：自动路由可变间距网络
公开(公告)号：US20120110539A1
公开(公告)日：2012-05-03
申请号：US13346491
申请日：2012-01-09
申请人： Jeremy Birch , Mark Waller , Graham Balsdon
发明人： Jeremy Birch , Mark Waller , Graham Balsdon
IPC分类号： G06F17/50
CPC分类号： G06F17/5077
摘要： A technique will automatically route interconnect of an integrated circuit and adjust spacing between tracks or interconnect in order to improve performance or reduce electromigration effects. By increasing spacing between certain tracks or moving tracks, performance can improve because a track will be more noise immunity from nearby tracks on the same layer or on different layers. The automatic router will adjust spacing between tracks depending on one or more factors. These factors may include current associated with a track, width of a track, capacitance, inductance, and electromigration. In a specific implementation, the technique uses a shape-based approach where a grid is not used. The technique may further vary the width of the tracks.
摘要翻译：一种技术将自动路由集成电路的互连，并调整磁道或互连之间的间距，以提高性能或减少电迁移效应。通过增加某些轨道或移动轨道之间的间距，性能可以提高，因为轨道将在相同层或不同层上的附近轨道具有更高的抗噪声能力。自动路由器将根据一个或多个因素来调整轨道之间的间距。这些因素可以包括与轨道相关的电流，轨道的宽度，电容，电感和电迁移。在具体实现中，该技术使用基于形状的方法，其中不使用网格。该技术可以进一步改变轨道的宽度。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式