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1. 发明申请

US20130094607A1 TRANSMITTER EMPLOYING PULLING MITIGATION MECHANISM AND RELATED METHOD THEREOF 有权
标题翻译：采用牵引式减速机构的发电机及其相关方法
公开(公告)号：US20130094607A1
公开(公告)日：2013-04-18
申请号：US13491614
申请日：2012-06-08
申请人： Jie-Wei Lai , Meng-Hsiung Hung , Robert Bogdan Staszewski
发明人： Jie-Wei Lai , Meng-Hsiung Hung , Robert Bogdan Staszewski
IPC分类号： H04B1/04 , H03G3/20
CPC分类号： H03F1/0211 , H03F1/0261 , H03F1/0277 , H03F1/223 , H03F3/2178 , H03F3/72 , H03F2200/405 , H03F2200/451 , H03F2200/516 , H03F2203/7206
摘要： A transmitter includes a power amplifier (PA) and a direct current (DC) voltage tuning circuit. The PA is arranged for receiving a radio-frequency (RF) clock derived from a clock source, and producing an output signal according to at least the RF clock. The DC voltage tuning circuit is arranged for tuning at least one DC voltage supplied to the PA for pulling mitigation of the clock source. A method of pulling mitigation of a source clock by a power amplifier (PA) includes adjusting a direct current (DC) voltage supplied to the PA.
摘要翻译：发射机包括功率放大器（PA）和直流（DC）电压调谐电路。 PA布置成用于接收从时钟源导出的射频（RF）时钟，并且根据至少RF时钟产生输出信号。直流电压调谐电路被布置用于调谐提供给PA的至少一个直流电压，以缓解时钟源。通过功率放大器（PA）来减轻源时钟的方法包括调整提供给PA的直流（DC）电压。

2. 发明申请

US20130094606A1 MULTI-STAGE DIGITALLY-CONTROLLED POWER AMPLIFIER 有权
标题翻译：多级数字控制功率放大器
公开(公告)号：US20130094606A1
公开(公告)日：2013-04-18
申请号：US13485941
申请日：2012-06-01
申请人： Jie-Wei Lai , Meng-Hsiung Hung , Robert Bogdan Staszewski
发明人： Jie-Wei Lai , Meng-Hsiung Hung , Robert Bogdan Staszewski
IPC分类号： H04B1/04
CPC分类号： H03F1/0211 , H03F1/0261 , H03F1/0277 , H03F1/223 , H03F3/2178 , H03F3/72 , H03F2200/405 , H03F2200/451 , H03F2200/516 , H03F2203/7206
摘要： A multi-stage digitally-controlled power amplifier (DPA) includes a radio-frequency (RF) clock input, an amplitude control word (ACW) input, a plurality of drivers, and an output stage. The RF clock input is arranged for receiving an RF clock. The ACW input is arranged for receiving a digital ACW signal. The drivers are coupled to the RF clock, and arranged for producing a plurality of intermediate signals, wherein at least one driver of the drivers is responsive to at least one bit of the digital ACW signal. The output stage is coupled to the intermediate signals, and arranged for producing an output signal.
摘要翻译：多级数字控制功率放大器（DPA）包括射频（RF）时钟输入，幅度控制字（ACW）输入，多个驱动器和输出级。 RF时钟输入被布置用于接收RF时钟。 ACW输入被安排用于接收数字ACW信号。驱动器耦合到RF时钟，并且被布置用于产生多个中间信号，其中驱动器的至少一个驱动器响应数字ACW信号的至少一个位。输出级耦合到中间信号，并且被布置用于产生输出信号。

3. 发明授权

US07777570B2 Transformer power combiner having secondary winding conductors magnetically coupled to primary winding conductors and configured in topology including series connection and parallel connection 有权
标题翻译：变压器功率组合器具有磁耦合到初级绕组导体的次级绕组导体并且被构造成包括串联和并联的拓扑结构
公开(公告)号：US07777570B2
公开(公告)日：2010-08-17
申请号：US12242892
申请日：2008-09-30
申请人： Jie-Wei Lai
发明人： Jie-Wei Lai
IPC分类号： H03F3/26 , H03F1/00 , H03F3/00
CPC分类号： H01F27/2804 , H03F3/602 , H03F2200/537 , H03F2200/541 , H03F2200/543 , H04B1/0483
摘要： A transformer power combiner having a plurality of input ports and an output port is provided. The transformer power combiner includes a plurality of primary winding conductors and a plurality of secondary winding conductors. The primary winding conductors are electrically connected to the input ports, respectively; in addition, each of the primary winding conductors is electrically connected between a positive terminal and a negative terminal of a corresponding input port. The secondary winding conductors are magnetically coupled to the primary winding conductors, respectively. The secondary winding conductors are configured in a topology including series connection and parallel connection between a positive terminal and a negative terminal of the output port.
摘要翻译：提供具有多个输入端口和输出端口的变压器功率组合器。变压器功率组合器包括多个初级绕组导体和多个次级绕组导体。初级绕组导体分别电连接到输入端口; 此外，每个初级绕组导体电连接在相应输入端口的正极端子和负极端子之间。次级绕组导体分别磁耦合到初级绕组导体。次级绕组导体被构造成包括串联连接和输出端口的正极和负极之间的并联连接的拓扑。

4. 发明授权

US07603096B2 Mixer with self-calibrating carrier leakage mechanism 有权
标题翻译：混合器具有自校准载体泄漏机制
公开(公告)号：US07603096B2
公开(公告)日：2009-10-13
申请号：US11675688
申请日：2007-02-16
申请人： Yuan-Hung Chung , Jie-Wei Lai
发明人： Yuan-Hung Chung , Jie-Wei Lai
IPC分类号： H04B1/06 , H04B7/00
CPC分类号： H03D7/1441 , H03D7/1458 , H03D2200/0033 , H03D2200/009
摘要： An embodiment of a mixer with carrier leakage self-calibrating is disclosed. The mixer comprises a double balanced mixer, a gm stage comprising a first processing unit and a second processing unit, a current duplicating circuit, a capacitor, a controller and a current compensation unit. The current duplicating circuit selects the first processing unit or the second processing unit and duplicates a duplicated current of the selected processing unit to charge the capacitor. The capacitor has a first terminal and a second terminal, wherein the second terminal is grounded and the first terminal receives the duplicated current. The controller determines a charge time of the capacitor to generate a compensation signal, wherein the charge time is the time that the voltage of the capacitor is charged to equal to a reference voltage. The current compensation unit receives the compensation signal to generate a compensation current to the mixer.
摘要翻译：公开了具有载波泄漏自校准的混频器的实施例。混频器包括双平衡混频器，包括第一处理单元和第二处理单元的gm级，电流复制电路，电容器，控制器和电流补偿单元。当前复制电路选择第一处理单元或第二处理单元，并复制所选择的处理单元的复制电流以对电容器充电。电容器具有第一端子和第二端子，其中第二端子接地，第一端子接收复制的电流。控制器确定电容器的充电时间以产生补偿信号，其中充电时间是将电容器的电压充电至等于参考电压的时间。电流补偿单元接收补偿信号以产生到混频器的补偿电流。

5. 发明申请

US20090189695A1 AMPLIFIER CIRCUIT HAVING STACKED MAIN AMPLIFIER AND PARALLEL SUB-AMPLIFIER 有权
标题翻译：具有堆叠主放大器和并联放大器的放大器电路
公开(公告)号：US20090189695A1
公开(公告)日：2009-07-30
申请号：US12022159
申请日：2008-01-30
申请人： Jie-Wei Lai , Min Chen
发明人： Jie-Wei Lai , Min Chen
IPC分类号： H03F3/68
CPC分类号： H03F1/223 , H03F1/26 , H03F1/3205 , H03F3/211 , H03F2200/294
摘要： An amplifier circuit for amplifying an input signal to generate an output signal is provided. The amplifier circuit has a stacked main amplifier, a parallel sub-amplifier, and a signal combiner. The stacked main amplifier includes a first amplifier unit for outputting a first amplified signal generated from processing the input signal; and a second amplifier unit for outputting a second amplified signal generated from processing the first amplified signal. The first amplifier unit and the second amplifier unit share bias current. The parallel sub-amplifier is coupled to the stacked main amplifier according to a parallel connection fashion, and outputs a third amplified signal generated from processing the input signal. The signal combiner combines the second amplified signal and the third amplified signal to generate the output signal.
摘要翻译：提供了用于放大输入信号以产生输出信号的放大器电路。放大器电路具有堆叠的主放大器，并联子放大器和信号组合器。堆叠的主放大器包括：第一放大器单元，用于输出从处理输入信号产生的第一放大信号; 以及第二放大器单元，用于输出从处理第一放大信号产生的第二放大信号。第一放大器单元和第二放大器单元共享偏置电流。并联子放大器根据并联连接方式耦合到堆叠的主放大器，并且输出从处理输入信号产生的第三放大信号。信号组合器组合第二放大信号和第三放大信号以产生输出信号。

6. 发明授权

US08994488B2 Transformer power splitter having primary winding conductors magnetically coupled to secondary winding conductors and configured in topology including series connection and parallel connection 有权
标题翻译：变压器功率分配器具有磁耦合到次级绕组导体的初级绕组导体并且被构造成包括串联和并联的拓扑结构
公开(公告)号：US08994488B2
公开(公告)日：2015-03-31
申请号：US12831270
申请日：2010-07-07
申请人： Jie-Wei Lai
发明人： Jie-Wei Lai
IPC分类号： H01F17/04 , H01F19/04 , H01F27/28 , H03F3/60 , H04B1/04
CPC分类号： H01F27/2804 , H01F19/04 , H03F3/602 , H03F2200/537 , H03F2200/541 , H03F2200/543 , H04B1/0483
摘要： A transformer power splitter has a plurality of output ports and an input port. The transformer power splitter includes a plurality of primary winding conductors and a plurality of secondary winding conductors. The secondary winding conductors are electrically connected to the output ports respectively. Each of the secondary winding conductors is electrically connected between a positive terminal and a negative terminal of a corresponding output port. The primary winding conductors are magnetically coupled to the secondary winding conductors respectively. The primary winding conductors are configured in a topology including series and parallel connections between a positive terminal and a negative terminal of the input port.
摘要翻译：变压器功率分配器具有多个输出端口和输入端口。变压器功率分配器包括多个初级绕组导体和多个次级绕组导体。次级绕组导体分别电连接到输出端口。每个次级绕组导体电连接在相应输出端口的正极端子和负极端子之间。初级绕组导体分别磁耦合到次级绕组导体。初级绕组导体被构造成包括输入端口的正极端子和负极端子之间的串联和并联连接的拓扑结构。

7. 发明授权

US08705657B2 Digital signal processing circuit for generating output signal according to non-overlapping clock signals and input bit streams and related wireless communication transmitters 有权
标题翻译：数字信号处理电路，用于根据不重叠的时钟信号和输入比特流以及相关的无线通信发射机产生输出信号
公开(公告)号：US08705657B2
公开(公告)日：2014-04-22
申请号：US13159385
申请日：2011-06-13
申请人： Jie-Wei Lai , Yang-Chuan Chen
发明人： Jie-Wei Lai , Yang-Chuan Chen
IPC分类号： H03C3/00
CPC分类号： H04L27/0008 , H04L27/12 , H04L27/3427
摘要： A digital signal processing circuit includes a combining stage and an output stage. The combining stage is arranged to receive a plurality of non-overlapping clock signals having a same frequency but different phases, receive a plurality of first input bit streams, and generate a first output bit stream by combining the first input bit streams according to the non-overlapping clock signals. The output stage is arranged to generate an output according to the first output bit stream. A digital signal processing method includes: receiving a plurality of non-overlapping clock signals having a same frequency but different phases; receiving a plurality of first input bit streams; generating a first output bit stream by combining the first input bit streams according to the non-overlapping clock signals; and generating an output according to the first output bit stream.
摘要翻译：数字信号处理电路包括组合级和输出级。组合级被布置为接收具有相同频率但不同相位的多个不重叠的时钟信号，接收多个第一输入比特流，并且通过根据非接收方式组合第一输入比特流来生成第一输出比特流， - 重叠的时钟信号。输出级被布置成根据第一输出位流产生输出。数字信号处理方法包括：接收具有相同频率但不同相位的多个非重叠时钟信号; 接收多个第一输入比特流; 通过根据所述非重叠时钟信号组合所述第一输入比特流来产生第一输出比特流; 以及根据第一输出比特流生成输出。

8. 发明授权

US08665052B2 Transformer-based circuit with compact and/or symmetrical layout design 有权
标题翻译：基于变压器的电路具有紧凑和/或对称的布局设计
公开(公告)号：US08665052B2
公开(公告)日：2014-03-04
申请号：US12540358
申请日：2009-08-12
申请人： Jie-Wei Lai
发明人： Jie-Wei Lai
IPC分类号： H01F5/00 , H01F27/28
CPC分类号： H01F27/2804 , H01F19/04
摘要： A transformer-based circuit has at least a first port and a plurality of second ports. The transformer-based circuit includes a first winding conductor and a plurality of second winding conductors. The first winding conductor is electrically connected to the first port, and has a plurality of sectors connected in series to thereby form a plurality of loops, where the loops are arranged in a concentric-like fashion. The second winding conductors are magnetically coupled to the first winding conductor; besides, the second winding conductors are electrically connected to the second ports, respectively. Overall layout patterns of the second winding conductors are identical to each other. The first winding conductor acts as one of a primary winding conductor and a secondary winding conductor, and each of the second winding conductors acts as the other of the primary winding conductor and the secondary winding conductor.
摘要翻译：基于变压器的电路至少具有第一端口和多个第二端口。基于变压器的电路包括第一绕组导体和多个第二绕组导体。第一绕组导体电连接到第一端口，并且具有串联连接的多个扇区，从而形成多个环，其中环以同心方式布置。第二绕组导体磁耦合到第一绕组导体; 此外，第二绕组导体分别电连接到第二端口。第二绕组导体的总布局图彼此相同。第一绕组导体用作初级绕组导体和次级绕组导体之一，并且每个第二绕组导体用作初级绕组导体和次级绕组导体中的另一个。

9. 发明授权

US08618983B2 Phased-array transceiver for millimeter-wave frequencies 有权
标题翻译：用于毫米波频率的相控阵收发器
公开(公告)号：US08618983B2
公开(公告)日：2013-12-31
申请号：US12750242
申请日：2010-03-30
申请人： Ping-Yu Chen , Brian A. Floyd , Jie-Wei Lai , Arun S. Natarajan , Sean T. Nicolson , Scott K. Reynolds , Ming-Dai Tsai , Alberto Valdes-Garcia , Jing-Hong C. Zhan
发明人： Ping-Yu Chen , Brian A. Floyd , Jie-Wei Lai , Arun S. Natarajan , Sean T. Nicolson , Scott K. Reynolds , Ming-Dai Tsai , Alberto Valdes-Garcia , Jing-Hong C. Zhan
IPC分类号： H01Q3/24 , H01Q3/36
CPC分类号： H01Q3/2694 , H01Q3/267
摘要： A phased-array transmitter and receiver that may be effectively implemented on a silicon substrate. The transmitter distributes to front-ends, and the receiver combines signals from front-ends, using a power distribution/combination tree that employs both passive and active elements. By monitoring the power inputs and outputs, a digital control is able to rapidly provide phase and gain correction information to the front-ends. Such a transmitter/receiver includes a plurality of radio frequency (RF) front-ends and a power splitting/combining network that includes active and passive components configured to distribute signals to/from the front-ends.
摘要翻译：可以有效地实现在硅衬底上的相控阵发射器和接收器。发射机分配到前端，并且接收器使用采用被动和有源元件的功率分配/组合树组合来自前端的信号。通过监控功率输入和输出，数字控制能够快速向前端提供相位和增益校正信息。这样的发射机/接收机包括多个射频（RF）前端和功率分配/组合网络，其包括配置成向/从前端分配信号的有源和无源组件。

10. 发明授权

US08618837B2 Multi-stage digitally-controlled power amplifier 有权
标题翻译：多级数字控制功率放大器
公开(公告)号：US08618837B2
公开(公告)日：2013-12-31
申请号：US13485941
申请日：2012-06-01
申请人： Jie-Wei Lai , Meng-Hsiung Hung , Robert Bogdan Staszewski
发明人： Jie-Wei Lai , Meng-Hsiung Hung , Robert Bogdan Staszewski
IPC分类号： H03K19/00
CPC分类号： H03F1/0211 , H03F1/0261 , H03F1/0277 , H03F1/223 , H03F3/2178 , H03F3/72 , H03F2200/405 , H03F2200/451 , H03F2200/516 , H03F2203/7206
摘要： A multi-stage digitally-controlled power amplifier (DPA) includes a radio-frequency (RF) clock input, an amplitude control word (ACW) input, a plurality of drivers, and an output stage. The RF clock input is arranged for receiving an RF clock. The ACW input is arranged for receiving a digital ACW signal. The drivers are coupled to the RF clock, and arranged for producing a plurality of intermediate signals, wherein at least one driver of the drivers is responsive to at least one bit of the digital ACW signal. The output stage is coupled to the intermediate signals, and arranged for producing an output signal.
摘要翻译：多级数字控制功率放大器（DPA）包括射频（RF）时钟输入，幅度控制字（ACW）输入，多个驱动器和输出级。 RF时钟输入被布置用于接收RF时钟。 ACW输入被安排用于接收数字ACW信号。驱动器耦合到RF时钟，并且被布置用于产生多个中间信号，其中驱动器的至少一个驱动器响应数字ACW信号的至少一个位。输出级耦合到中间信号，并且被布置用于产生输出信号。

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