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1. 发明授权

US09722537B2 Fractional-N frequency synthesizer incorporating cyclic digital-to-time and time-to-digital circuit pair 有权
公开(公告)号：US09722537B2
公开(公告)日：2017-08-01
申请号：US14831784
申请日：2015-08-20
申请人： Gerasimos S. Vlachogiannakis , Augusto Ronchini Ximenes , Robert Bogdan Staszewski
发明人： Gerasimos S. Vlachogiannakis , Augusto Ronchini Ximenes , Robert Bogdan Staszewski
IPC分类号： H03B1/00 , H03K3/015 , H03L7/093 , H03B5/12 , G04F10/00 , H03L7/08 , H03M1/00 , H03M1/20 , H03L7/089 , H03L7/197 , H03K3/03
CPC分类号： H03B5/1265 , G04F10/005 , H03B1/00 , H03B5/1215 , H03B5/1228 , H03B5/1296 , H03J2200/10 , H03K3/015 , H03K3/0315 , H03L7/0802 , H03L7/0893 , H03L7/093 , H03L7/1976 , H03L2207/50 , H03M1/002 , H03M1/201
摘要： A novel and useful look-ahead time to digital converter (TDC) that is applied to an all digital phase locked loop (ADPLL) as the fractional phase error detector. The deterministic nature of the phase error during frequency/phase lock is exploited to achieve a reduction in power consumption of the TDC. The look-ahead TDC circuit is used to construct a cyclic DTC-TDC pair which functions to reduce fractional spurs of the output spectrum in near-integer channels by randomly rotating the cyclic DTC-TDC structure so that it starts from a different point every reference clock thereby averaging out the mismatch of the elements. Associated rotation and dithering methods are also presented. The ADPLL is achieved using the look-ahead TDC and/or cyclic DTC-TDC pair circuit.

2. 发明申请

US20160099681A1 60 GHz Frequency Generator Incorporating Third Harmonic Boost And Extraction 有权
标题翻译： 60 GHz频率发生器结合三次谐波升压和提取
公开(公告)号：US20160099681A1
公开(公告)日：2016-04-07
申请号：US14874416
申请日：2015-10-03
申请人： Zhirui Zong , Masoud Babaie , Robert Bogdan Staszewski
发明人： Zhirui Zong , Masoud Babaie , Robert Bogdan Staszewski
IPC分类号： H03B5/12
CPC分类号： H03B5/1212 , H03B5/1215 , H03B5/1218 , H03B5/1228 , H03B5/124 , H03B5/1265 , H03B5/1281 , H03B5/1293 , H03B5/1296 , H03J2200/10 , H03L7/081 , H03L7/0991 , H03L7/1976
摘要： A novel and useful 60 GHz frequency generator based on a third harmonic extraction technique which improves system level efficiency and performance. The frequency generator employs a third harmonic boosting technique to increase the third harmonic at the output of the oscillator. The oscillator generates both ˜20 GHz fundamental and a significant amount of the third harmonic at ˜60 GHz and avoids the need for a frequency divider operating at 60 GHz. The undesired fundamental harmonic at ˜20 GHz is rejected by the good fundamental HRR inherent in the oscillator buffer stage while the ˜60 GHz component is amplified to the output. The fundamental harmonic is further suppressed by an active cancellation by properly combining the two outputs. The oscillator fabricated in 40 nm CMOS exhibits a phase noise of −100 dBc/Hz at 1 MHz offset from a 60 GHz carrier and have a tuning range of 25%.
摘要翻译：一种基于三次谐波提取技术的新颖有用的60 GHz频率发生器，可提高系统级效率和性能。频率发生器采用三次谐波增强技术来增加振荡器输出端的三次谐波。振荡器在〜60 GHz时产生〜20 GHz基波和大量三次谐波，避免了在60 GHz工作的分频器。在〜20 GHz的不希望的基波谐波被振荡器缓冲级固有的良好的基本HRR所抵消，而〜60 GHz分量被放大到输出。通过适当地组合两个输出，通过主动取消进一步抑制基波。以40nm CMOS制造的振荡器在距离60GHz载波的1MHz偏移处具有-100dBc / Hz的相位噪声，并且具有25％的调谐范围。

3. 发明申请

US20160056799A1 DC-Coupled Buffer Circuit For High Speed Oscillators 有权
标题翻译：用于高速振荡器的直流耦合缓冲电路
公开(公告)号：US20160056799A1
公开(公告)日：2016-02-25
申请号：US14831119
申请日：2015-08-20
申请人： Augusto Ronchini Ximenes , Robert Bogdan Staszewski
发明人： Augusto Ronchini Ximenes , Robert Bogdan Staszewski
IPC分类号： H03K3/015 , H03B1/00
CPC分类号： H03B5/1265 , G04F10/005 , H03B1/00 , H03B5/1215 , H03B5/1228 , H03B5/1296 , H03J2200/10 , H03K3/015 , H03K3/0315 , H03L7/0802 , H03L7/0893 , H03L7/093 , H03L7/1976 , H03L2207/50 , H03M1/002 , H03M1/201
摘要： A novel and useful LC-tank digitally controlled oscillator (DCO) incorporating a split transformer configuration. The LC-tank oscillator exhibits a significant reduction in area such that it is comparable in size to conventional ring oscillators (ROs) while still retaining its salient features of excellent phase noise and low sensitivity to supply variations. The oscillator incorporates an ultra-compact split transformer topology that is less susceptible to common-mode electromagnetic interference than regular high-Q LC tanks which is highly desirable in SoC environments. The oscillator, together with a novel dc-coupled buffer, can be incorporated within a wide range of circuit applications, including clock generators and an all-digital phase-locked loop (ADPLL) intended for wireline applications.
摘要翻译：一种新颖有用的LC-tank数字控制振荡器（DCO），其包含分离变压器配置。 LC-tank振荡器显示出显着的面积减小，使得它在尺寸上与常规的环形振荡器（RO）相当，同时仍然保持其显着的相位噪声特征以及对供应变化的低灵敏度。该振荡器包含一个超紧凑型分离式变压器拓扑，它比常规高Q液相色谱箱容易受到共模电磁干扰的影响，这在SoC环境中是非常需要的。该振荡器与一个新颖的直流耦合缓冲器可以并入广泛的电路应用中，包括时钟发生器和用于有线应用的全数字锁相环（ADPLL）。

4. 发明授权

US09037886B2 Time-to-digital system and associated frequency synthesizer 有权
标题翻译：时间到数字系统和相关的频率合成器
公开(公告)号：US09037886B2
公开(公告)日：2015-05-19
申请号：US13450242
申请日：2012-04-18
申请人： Yi-Hsien Cho , Robert Bogdan Staszewski
发明人： Yi-Hsien Cho , Robert Bogdan Staszewski
IPC分类号： G06F1/32 , H03L7/081
CPC分类号： H03L7/081 , G06F1/32 , H03L7/16 , H03L7/18 , H03L2207/50
摘要： A time-to-digital system, such as a frequency synthesizer, includes a power management circuit and a time-to-digital converter (TDC). Said power management circuit is coupled to a frequency reference clock and a variable clock, and arranged to output a delayed frequency reference clock and a single pulse of said variable clock ahead of a transition of said delayed frequency reference clock. Said TDC is coupled to said power management circuit and arranged to produce a digital TDC output.
摘要翻译：诸如频率合成器的时间 - 数字系统包括电源管理电路和时间 - 数字转换器（TDC）。所述功率管理电路耦合到频率参考时钟和可变时钟，并被布置成在所述延迟的频率参考时钟的转变之前输出延迟的频率参考时钟和所述可变时钟的单个脉冲。所述TDC耦合到所述功率管理电路并被布置成产生数字TDC输出。

5. 发明申请

US20130191061A1 METHOD AND APPARATUS OF ESTIMATING/CALIBRATING TDC GAIN 有权
标题翻译：估计/校准TDC增益的方法和装置
公开(公告)号：US20130191061A1
公开(公告)日：2013-07-25
申请号：US13610842
申请日：2012-09-11
申请人： Chi-Hsueh Wang , Robert Bogdan Staszewski , Yi-Hsien Cho
发明人： Chi-Hsueh Wang , Robert Bogdan Staszewski , Yi-Hsien Cho
IPC分类号： G06F19/00
CPC分类号： G04F10/005
摘要： A method of estimating gain of a time-to-digital converter (TDC) includes: capturing a TDC output sample; calculating a gradient in response to the TDC output sample; and adjusting a TDC normalizing gain based on the calculating step. Another method of calibrating gain of a TDC includes: capturing a phase error which is derived from a TDC output sample, a reference phase and a variable phase; calculating a gradient in response to the phase error; and adjusting a TDC normalizing gain based on the calculating step.
摘要翻译：一种估计时间 - 数字转换器（TDC）的增益的方法包括：捕获TDC输出样本; 计算响应于TDC输出样本的梯度; 以及基于所述计算步骤调整TDC归一化增益。校准TDC增益的另一种方法包括：捕获从TDC输出样本，参考相位和可变相位导出的相位误差; 计算响应于相位误差的梯度; 以及基于所述计算步骤调整TDC归一化增益。

6. 发明申请

US20130187688A1 POLAR TRANSMITTER HAVING FREQUENCY MODULATING PATH WITH INTERPOLATION IN COMPENSATING FEED INPUT AND RELATED METHOD THEREOF 有权
标题翻译：具有补偿进给输入的插补的频率调制路径的极性发射器及其相关方法
公开(公告)号：US20130187688A1
公开(公告)日：2013-07-25
申请号：US13612770
申请日：2012-09-12
申请人： Chi-Hsueh Wang , Kai-Peng Kao , Robert Bogdan Staszewski
发明人： Chi-Hsueh Wang , Kai-Peng Kao , Robert Bogdan Staszewski
IPC分类号： H03L7/08
CPC分类号： H03C5/00 , H04L7/002 , H04L7/0331
摘要： A frequency modulating path for generating a frequency modulated clock includes a direct feed input arranged for directly modulating frequency of an oscillator, and a compensating feed input arranged for compensating effects of frequency modulating on a phase error; wherein the compensating feed input is resampled by a down-divided clock that is an integer edge division of the oscillator. A reference phase generator for generating a reference phase output includes a resampling circuit, an accumulator and a sampler. The resampling circuit is for resampling a modulating frequency command word (FCW) input to produce a plurality of samples. The accumulator is for accumulating the samples to generate an accumulated result. The sampler is for sampling the accumulated result according to a frequency reference clock, and accordingly generating a sampled result, wherein the reference phase output is updated according to at least the sampled result.
摘要翻译：用于产生频率调制时钟的频率调制路径包括直接调制振荡器频率的直接馈送输入和用于补偿频率调制对相位误差的影响的补偿馈入输入; 其中所述补偿馈送输入由作为所述振荡器的整数边缘除法的下分频时钟再采样。用于产生参考相位输出的参考相位发生器包括重采样电路，累加器和采样器。重采样电路用于对调制频率指令字（FCW）进行重采样以产生多个采样。累加器用于累积样本以产生累积结果。采样器用于根据频率参考时钟对累积结果进行采样，并且因此产生采样结果，其中至少根据采样结果来更新参考相位输出。

7. 发明授权

US08493107B2 Clock generator for generating output clock having non-harmonic relationship with input clock and related clock generating method thereof 有权
标题翻译：时钟发生器，用于产生与输入时钟非谐波关系的输出时钟及其相关的时钟产生方法
公开(公告)号：US08493107B2
公开(公告)日：2013-07-23
申请号：US13170197
申请日：2011-06-28
申请人： Robert Bogdan Staszewski , Chi-Hsueh Wang
发明人： Robert Bogdan Staszewski , Chi-Hsueh Wang
IPC分类号： H03L7/00
CPC分类号： H03K5/131 , H03L7/0996
摘要： One clock generator includes an oscillator block, a delay circuit, and an output block. The oscillator block provides a first clock of multiple phases. The delay circuit delays at least one of said multiple phases of said first clock to generate a second clock of multiple phases. The output block generates a third clock by selecting signals from said multiple phases of said second clock, wherein said third clock has non-harmonic relationship with said first clock. Another exemplary clock generator includes an oscillator block and an output block. The oscillator block includes an oscillator arranged to provide a first clock, and a delay locked loop arranged to generate a second clock according to said first clock. The output block generates a third clock by selecting signals from said multiple phases, wherein said third clock has non-harmonic relationship with said first clock.
摘要翻译：一个时钟发生器包括一个振荡器模块，一个延迟电路和一个输出模块。振荡器模块提供多个阶段的第一个时钟。所述延迟电路延迟所述第一时钟的所述多个相位中的至少一个以产生多相的第二时钟。输出块通过从所述第二时钟的所述多个相位选择信号来产生第三时钟，其中所述第三时钟与所述第一时钟具有非谐波关系。另一示例性时钟发生器包括振荡器模块和输出模块。振荡器模块包括布置成提供第一时钟的振荡器和布置成根据所述第一时钟产生第二时钟的延迟锁定环。输出块通过从所述多个相位选择信号来产生第三时钟，其中所述第三时钟与所述第一时钟具有非谐波关系。

8. 发明申请

US20130093469A1 FREQUENCY SYNTHESIZER AND ASSOCIATED METHOD 有权
标题翻译：频率合成器及相关方法
公开(公告)号：US20130093469A1
公开(公告)日：2013-04-18
申请号：US13450208
申请日：2012-04-18
申请人： Ang-Sheng Lin , Robert Bogdan Staszewski , Yi-Hsien Cho
发明人： Ang-Sheng Lin , Robert Bogdan Staszewski , Yi-Hsien Cho
IPC分类号： H03B21/00
CPC分类号： H03L7/081 , G06F1/32 , H03L7/16 , H03L7/18 , H03L2207/50
摘要： A frequency synthesizer includes an oscillator for providing an RF clock, a phase shifter coupled to said oscillator for providing a shifted RF clock by changing phase of said RF clock, and a time-to-digital converter (TDC) coupled to said phase shifter for quantizing a time difference between a frequency reference clock and said shifted RF clock, wherein a range of said TDC covers significantly less than a full range of said RF clock period. An associated method is also provided.
摘要翻译：频率合成器包括用于提供RF时钟的振荡器，耦合到所述振荡器的移相器，用于通过改变所述RF时钟的相位来提供移位的RF时钟;以及耦合到所述移相器的时间 - 数字转换器（TDC），用于量化频率参考时钟和所述移位的RF时钟之间的时间差，其中所述TDC的范围明显小于所述RF时钟周期的整个范围。还提供了相关联的方法。

9. 发明授权

US08130040B2 Power amplifier with two transistors and traces forming two transformers 有权
标题翻译：功率放大器具有两个晶体管和迹线，形成两个变压器
公开(公告)号：US08130040B2
公开(公告)日：2012-03-06
申请号：US12830898
申请日：2010-07-06
申请人： Robert Bogdan Staszewski , See Taur Lee
发明人： Robert Bogdan Staszewski , See Taur Lee
IPC分类号： H03F3/68
CPC分类号： H03F3/189 , H03F3/211 , H03F3/602 , H03F2200/541
摘要： Methods to implement low cost, high efficiency, low loss power combiner with novel matching circuits are disclosed. A narrow band power combiner enables a high power and high efficiency radio frequency power amplifier to be realized using multiple low voltage CMOS transistors or micro power amplifiers. The power combiner may be printed on a package substrate and realized either using single layer substrate through edge coupling or multiple layers substrate through broadside coupling. The micro power amplifiers may be fabricated using low voltage CMOS technology and electrical connections between the outputs from the micro power amplifiers and the power combiner may be provided through stud bumps in a flip chip technology. With the tunable matching circuits, the present invention allows the narrow band power combiner to be tuned to different frequencies.
摘要翻译：公开了实现具有新型匹配电路的低成本，高效率，低损耗功率组合器的方法。窄带功率组合器使得能够使用多个低电压CMOS晶体管或微功率放大器实现高功率和高效率的射频功率放大器。功率组合器可以印刷在封装衬底上，并且通过边缘耦合使用单层衬底或通过宽边耦合实现多层衬底。微功率放大器可以使用低电压CMOS技术制造，并且来自微功率放大器的输出之间的电连接和功率组合器可以通过倒装芯片技术中的凸块凸块来提供。利用可调匹配电路，本发明允许将窄带功率组合器调谐到不同的频率。

10. 发明授权

US08126401B2 Transmitter PLL with bandwidth on demand 有权
标题翻译：发射器PLL，带宽需求
公开(公告)号：US08126401B2
公开(公告)日：2012-02-28
申请号：US12412790
申请日：2009-03-27
申请人： Robert Bogdan Staszewski , Khurram Waheed , Sudheer K. Vemulapalli , Manouchehr Entezari , Imran Bashir
发明人： Robert Bogdan Staszewski , Khurram Waheed , Sudheer K. Vemulapalli , Manouchehr Entezari , Imran Bashir
IPC分类号： H04B1/00
CPC分类号： H03L7/085 , H03L7/093 , H03L7/0991 , H03L2207/50 , H04L27/361
摘要： An embodiment of the present invention provides transmitter having a phase locked loop that has a dynamically controllable loop bandwidth. A transmit modulator is coupled to the PLL for performing vector modulation in response to transmission symbols. Each transmission symbol comprises an amplitude signal and a phase signal. A controller is coupled to the PLL and to the transmit modulator and is operable to detect when a criteria of the transmission symbols crosses a threshold and to adjust loop bandwidth in response to crossing the threshold. The criteria of the transmission symbols may be a function of the amplitude signal or a function of the phase signal, and may be the amplitude signal, a first derivative of the amplitude signal, a second derivative of the amplitude signal, a square of the amplitude signal, a derivative of the amplitude signal squared, the phase signal, or a derivative of the phase signal.
摘要翻译：本发明的一个实施例提供具有锁相环的发射机，其具有动态可控的环路带宽。发射调制器耦合到PLL以响应于发射符号执行矢量调制。每个发送符号包括振幅信号和相位信号。控制器耦合到PLL和发射调制器，并且可操作以检测发射符号的标准何时跨越阈值并响应于跨越阈值来调整环路带宽。传输符号的标准可以是振幅信号或相位信号的函数的函数，并且可以是振幅信号，振幅信号的一阶导数，振幅信号的二阶导数，幅度的平方信号，幅度信号平方的导数，相位信号或相位信号的导数。

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