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1. 发明申请

US20130083600A1 SEMICONDUCTOR DEVICE AND METHOD OF OPERATING THE SAME 审中-公开
标题翻译：半导体器件及其操作方法
公开(公告)号：US20130083600A1
公开(公告)日：2013-04-04
申请号：US13619122
申请日：2012-09-14
申请人： Jin Haeng Lee
发明人： Jin Haeng Lee
IPC分类号： G11C16/10 , G11C16/04
CPC分类号： G11C16/0483 , G11C8/04 , G11C8/12 , G11C16/26 , G11C16/3418 , G11C16/3454
摘要： A method of operating a semiconductor device includes selecting one of a plurality of memory cell blocks included in a memory cell array, programming even-numbered memory cells coupled to a selected word line among the word lines of the selected memory cell block, programming odd-numbered memory cells coupled to the selected word line, programming odd-numbered memory cells coupled to a next word line adjacent to the selected word line, and programming even-numbered memory cells coupled to the next word line, wherein the programming is repeated until programming on selected memory cells coupled to all the word lines of the selected memory cell block is completed.
摘要翻译：一种操作半导体器件的方法包括选择包括在存储单元阵列中的多个存储单元块中的一个，对所选择的存储单元块的字线中耦合到所选字线的偶数存储单元进行编程，耦合到所选字线的编号的存储器单元，编程耦合到与所选字线相邻的下一个字线的奇数编号的存储器单元，以及编程耦合到下一个字线的偶数存储单元，其中重复编程直到编程在与所选存储单元块的所有字线耦合的选定存储单元上完成。

2. 发明授权

US08189394B2 Page buffer circuit of nonvolatile memory device and method of operating the same 失效
标题翻译：非易失性存储器件的页缓冲电路及其操作方法
公开(公告)号：US08189394B2
公开(公告)日：2012-05-29
申请号：US12647725
申请日：2009-12-28
申请人： Hyun Jong Jin , Jin Haeng Lee
发明人： Hyun Jong Jin , Jin Haeng Lee
IPC分类号： G11C16/06
CPC分类号： G11C7/1033 , G11C7/065 , G11C11/5628 , G11C16/10 , G11C2211/5621 , G11C2211/5642 , G11C2216/14
摘要： The page buffer of a nonvolatile memory device utilizing a double verification method using first and second verification voltages when performing a program verification operation includes a first latch unit including a first latch configured to store input data and results of a program operation and a first verification operation using the first verification voltage, and a second latch unit including a second latch configured to have a higher latch trip point than the first latch and to store a result of a second verification operation using the second verification voltage, which is less than the first verification voltage, when the first verification operation is performed.
摘要翻译：当执行程序验证操作时，利用使用第一和第二验证电压的双重验证方法的非易失性存储器件的页面缓冲器包括第一锁存单元，其包括第一锁存器，其被配置为存储输入数据以及程序操作和第一验证操作的结果使用第一验证电压，以及包括配置为具有比第一锁存器更高的锁存跳变点的第二锁存器的第二锁存单元，并且使用小于第一验证电压的第二验证电压存储第二验证操作的结果当执行第一验证操作时。

3. 发明申请

US20120008406A1 NONVOLATILE MEMORY DEVICE AND METHOD OF OPERATING THE SAME 审中-公开
标题翻译：非易失性存储器件及其操作方法
公开(公告)号：US20120008406A1
公开(公告)日：2012-01-12
申请号：US13166194
申请日：2011-06-22
申请人： Jin Haeng LEE
发明人： Jin Haeng LEE
IPC分类号： G11C16/10 , G11C16/04
CPC分类号： G11C16/10 , G11C16/0483 , G11C16/3454
摘要： A method of operating a nonvolatile memory device includes programming first memory cells to make threshold voltages of the first memory cells to reach a verification voltage determined based on program data of second memory cells to be programmed, and programming the second memory cells.
摘要翻译：一种操作非易失性存储器件的方法包括：对第一存储器单元进行编程，使得第一存储器单元的阈值电压达到基于要编程的第二存储器单元的程序数据确定的验证电压，以及对第二存储器单元进行编程。

4. 发明申请

US20100238737A1 BIT LINE SELECT VOLTAGE GENERATOR AND NONVOLATILE MEMORY DEVICE USING THE SAME 有权
标题翻译：位线选择电压发生器和非易失性存储器件使用它
公开(公告)号：US20100238737A1
公开(公告)日：2010-09-23
申请号：US12790579
申请日：2010-05-28
申请人： Jin-Haeng LEE
发明人： Jin-Haeng LEE
IPC分类号： G11C16/04
CPC分类号： G11C7/12 , G11C16/24 , G11C16/30 , G11C2207/005
摘要： A bit line select voltage generator includes a first and second voltage generators and a voltage transmission unit. The first voltage generator operates to divide a reference voltage of a reference voltage generator to generate a first voltage and a second voltage, wherein the second voltage is lower than the first voltage. The second voltage generator operates to change the first voltage according to change of temperatures thereby generating a third voltage. The voltage transmission unit operates to transmit the second voltage or the third voltage to an output terminal according to a voltage level of a first voltage transmit control signal or a second voltage transmit control signal.
摘要翻译：位线选择电压发生器包括第一和第二电压发生器和电压传输单元。第一电压发生器用于分压参考电压发生器的参考电压以产生第一电压和第二电压，其中第二电压低于第一电压。第二电压发生器操作以根据温度变化来改变第一电压，从而产生第三电压。电压传输单元操作以根据第一电压发射控制信号或第二电压发射控制信号的电压电平将第二电压或第三电压传输到输出端。

5. 发明申请

US20080162851A1 NON-VOLATILE MEMORY DEVICE AND METHOD OF ENCRYPTING DATA IN THE SAME 有权
标题翻译：非易失性存储器件和加密数据的方法
公开(公告)号：US20080162851A1
公开(公告)日：2008-07-03
申请号：US11753359
申请日：2007-05-24
申请人： Jin Haeng Lee
发明人： Jin Haeng Lee
IPC分类号： G06F12/00
CPC分类号： G06F21/79
摘要： A non-volatile memory device includes an input/output terminal mixing section configured to couple data input/output terminals of the memory device to data input/output terminals of a page buffer in accordance with a user selection. A user data authenticating section is configured to transmit a control signal to the input/output terminal mixing section so that the input/output terminal mixing section couples the data input/output terminals of the memory device to the data input/output terminals of the page buffer in accordance with the user selection. A spare cell is configured to store the coupling configuration of the data input/output terminals of the memory device and the data input/output terminals of the page buffer in accordance with the user selection.
摘要翻译：非易失性存储器件包括：输入/输出端混合部分，被配置为根据用户选择将存储器件的数据输入/输出端子耦合到页缓冲器的数据输入/输出端。用户数据认证部被配置为将控制信号发送到输入/输出端混合部分，使得输入/输出端混合部分将存储器件的数据输入/输出端子耦合到页的数据输入/输出端子缓冲器根据用户选择。备用单元被配置为根据用户选择存储存储器件的数据输入/输出端子和页缓冲器的数据输入/输出端子的耦合配置。

6. 发明授权

US08335107B2 Semiconductor memory device and method of operating the same 有权
标题翻译：半导体存储器件及其操作方法
公开(公告)号：US08335107B2
公开(公告)日：2012-12-18
申请号：US12971208
申请日：2010-12-17
申请人： Jin Haeng Lee
发明人： Jin Haeng Lee
IPC分类号： G11C16/00
CPC分类号： G11C16/10 , G11C11/5628 , G11C16/3404
摘要： A semiconductor memory device comprises memory blocks having a plurality of memory cells coupled to a plurality of bit lines, a first latch group coupled to a sense node and configured to store data to be programmed into memory cells, where the memory cells are coupled to the bit lines and the sense node is coupled to at least one of the bit lines, a second latch group coupled to the sense node and configured to receive data of the first latch group, and a sense node voltage control circuit configured to control a voltage of the sense node according to data stored in the first latch group.
摘要翻译：半导体存储器件包括具有耦合到多个位线的多个存储器单元的存储器块，耦合到感测节点并被配置为存储要被编程到存储器单元中的数据的第一锁存器组，其中存储器单元耦合到位线，并且感测节点耦合到位线中的至少一个，耦合到感测节点并被配置为接收第一锁存器组的数据的第二锁存器组，以及感测节点电压控制电路，被配置为控制根据存储在第一锁存器组中的数据的感测节点。

7. 发明申请

US20110149652A1 SEMICONDUCTOR MEMORY DEVICE AND METHOD OF OPERATING THE SAME 有权
标题翻译：半导体存储器件及其操作方法
公开(公告)号：US20110149652A1
公开(公告)日：2011-06-23
申请号：US12971208
申请日：2010-12-17
申请人： Jin Haeng LEE
发明人： Jin Haeng LEE
IPC分类号： G11C16/04 , G11C16/10
CPC分类号： G11C16/10 , G11C11/5628 , G11C16/3404
摘要： A semiconductor memory device comprises memory blocks having a plurality of memory cells coupled to a plurality of bit lines, a first latch group coupled to a sense node and configured to store data to be programmed into memory cells, where the memory cells are coupled to the bit lines and the sense node is coupled to at least one of the bit lines, a second latch group coupled to the sense node and configured to receive data of the first latch group, and a sense node voltage control circuit configured to control a voltage of the sense node according to data stored in the first latch group.
摘要翻译：半导体存储器件包括具有耦合到多个位线的多个存储器单元的存储器块，耦合到感测节点并被配置为存储要被编程到存储器单元中的数据的第一锁存器组，其中存储器单元耦合到位线，并且感测节点耦合到位线中的至少一个，耦合到感测节点并被配置为接收第一锁存器组的数据的第二锁存器组，以及感测节点电压控制电路，被配置为控制根据存储在第一锁存器组中的数据的感测节点。

8. 发明授权

US07898870B2 Nonvolatile memory device having a bit line select voltage generator adapted to a temperature change 有权
标题翻译：具有适于温度变化的位线选择电压发生器的非易失性存储器件
公开(公告)号：US07898870B2
公开(公告)日：2011-03-01
申请号：US12790579
申请日：2010-05-28
申请人： Jin-Haeng Lee
发明人： Jin-Haeng Lee
IPC分类号： G11C16/26
CPC分类号： G11C7/12 , G11C16/24 , G11C16/30 , G11C2207/005
摘要： A bit line select voltage generator includes a first and second voltage generators and a voltage transmission unit. The first voltage generator operates to divide a reference voltage of a reference voltage generator to generate a first voltage and a second voltage, wherein the second voltage is lower than the first voltage. The second voltage generator operates to change the first voltage according to change of temperatures thereby generating a third voltage. The voltage transmission unit operates to transmit the second voltage or the third voltage to an output terminal according to a voltage level of a first voltage transmit control signal or a second voltage transmit control signal.
摘要翻译：位线选择电压发生器包括第一和第二电压发生器和电压传输单元。第一电压发生器用于分压参考电压发生器的参考电压以产生第一电压和第二电压，其中第二电压低于第一电压。第二电压发生器操作以根据温度变化来改变第一电压，从而产生第三电压。电压传输单元操作以根据第一电压发射控制信号或第二电压发射控制信号的电压电平将第二电压或第三电压传输到输出端。

9. 发明申请

US20100214849A1 PAGE BUFFER CIRCUIT OF NONVOLATILE MEMORY DEVICE AND METHOD OF OPERATING THE SAME 失效
标题翻译：非易失性存储器件的页缓冲电路及其操作方法
公开(公告)号：US20100214849A1
公开(公告)日：2010-08-26
申请号：US12647725
申请日：2009-12-28
申请人： Hyun Jong Jin , Jin Haeng Lee
发明人： Hyun Jong Jin , Jin Haeng Lee
IPC分类号： G11C16/06 , G11C7/10
CPC分类号： G11C7/1033 , G11C7/065 , G11C11/5628 , G11C16/10 , G11C2211/5621 , G11C2211/5642 , G11C2216/14
摘要： The page buffer of a nonvolatile memory device utilizing a double verification method using first and second verification voltages when performing a program verification operation includes a first latch unit including a first latch configured to store input data and results of a program operation and a first verification operation using the first verification voltage, and a second latch unit including a second latch configured to have a higher latch trip point than the first latch and to store a result of a second verification operation using the second verification voltage, which is less than the first verification voltage, when the first verification operation is performed.
摘要翻译：当执行程序验证操作时，利用使用第一和第二验证电压的双重验证方法的非易失性存储器件的页面缓冲器包括第一锁存单元，其包括第一锁存器，其被配置为存储输入数据以及程序操作和第一验证操作的结果使用第一验证电压，以及包括配置为具有比第一锁存器更高的锁存跳变点的第二锁存器的第二锁存单元，并且使用小于第一验证电压的第二验证电压存储第二验证操作的结果当执行第一验证操作时。

10. 发明申请

US20080192536A1 BIT LINE SELECT VOLTAGE GENERATOR AND NONVOLATILE MEMORY DEVICE USING THE SAME 有权
标题翻译：位线选择电压发生器和非易失性存储器件使用它
公开(公告)号：US20080192536A1
公开(公告)日：2008-08-14
申请号：US11949655
申请日：2007-12-03
申请人： Jin-Haeng LEE
发明人： Jin-Haeng LEE
IPC分类号： G11C7/00 , G11C16/06
CPC分类号： G11C7/12 , G11C16/24 , G11C16/30 , G11C2207/005
摘要： A bit line select voltage generator includes a first voltage generator, a second voltage generator, and a voltage transmission unit. The first voltage generator is configured to divide a reference voltage of a reference voltage generator, generate a control voltage, and generate a first voltage in response to the control voltage. In this case, the first voltage is raised according to an increase of a temperature and output. The second voltage generator is configured to divide the reference voltage and generate a second voltage of a level lower than that of the first voltage. The voltage transmission unit is configured to transmit the first voltage or the second voltage to an output terminal according to a voltage level of a first voltage transmit control signal or a second voltage transmit control signal.
摘要翻译：位线选择电压发生器包括第一电压发生器，第二电压发生器和电压传输单元。第一电压发生器被配置为分配参考电压发生器的参考电压，产生控制电压，并响应于控制电压产生第一电压。在这种情况下，第一电压根据温度和输出的增加而升高。第二电压发生器被配置为分压参考电压并产生低于第一电压的电平的第二电压。电压传输单元被配置为根据第一电压发射控制信号或第二电压发射控制信号的电压电平将第一电压或第二电压发送到输出端。

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