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1. 发明申请

US20170133219A1 MATERIAL LAYERS, SEMICONDUCTOR DEVICES INCLUDING THE SAME, AND METHODS OF FABRICATING MATERIAL LAYERS AND SEMICONDUCTOR DEVICES 审中-公开
公开(公告)号：US20170133219A1
公开(公告)日：2017-05-11
申请号：US15336901
申请日：2016-10-28
申请人： Yong-suk Tak , Gi-gwan Park , Jin-bum Kim , Bon-young Koo , Ki-yeon Park , Tae-jong Lee
发明人： Yong-suk Tak , Gi-gwan Park , Jin-bum Kim , Bon-young Koo , Ki-yeon Park , Tae-jong Lee
IPC分类号： H01L21/02 , H01L29/06 , H01L29/08 , H01L29/161 , H01L29/16 , C23C16/50 , H01L29/51 , H01L21/28 , H01L29/66 , H01L29/786 , H01L29/423 , C23C16/455 , H01L29/78 , H01L29/49
CPC分类号： H01L21/02126 , C23C16/30 , C23C16/36 , C23C16/45523 , C23C16/45529 , C23C16/45531 , C23C16/45542 , C23C16/50 , H01L21/02211 , H01L21/02219 , H01L21/02274 , H01L21/0228 , H01L21/28088 , H01L29/0653 , H01L29/0673 , H01L29/0847 , H01L29/16 , H01L29/1608 , H01L29/161 , H01L29/165 , H01L29/42392 , H01L29/4966 , H01L29/4983 , H01L29/517 , H01L29/66545 , H01L29/66795 , H01L29/7851 , H01L29/7854 , H01L29/78618 , H01L29/78651 , H01L29/78681 , H01L29/78684 , H01L29/78696
摘要： A material layer, a semiconductor device including the material layer, and methods of forming the material layer and the semiconductor device are provided herein. A method of forming a SiOCN material layer may include supplying a silicon source onto a substrate, supplying a carbon source onto the substrate, supplying an oxygen source onto the substrate, supplying a nitrogen source onto the substrate, and supplying hydrogen onto the substrate. When a material layer is formed according to a method of the present inventive concepts, a material layer having a high tolerance to wet etching and/or good electric characteristics may be formed, and may even be formed when the method is performed at a low temperature.

2. 发明授权

US08877583B2 Method of manufacturing a semiconductor device 有权
标题翻译：制造半导体器件的方法
公开(公告)号：US08877583B2
公开(公告)日：2014-11-04
申请号：US13728622
申请日：2012-12-27
申请人： Jin-Bum Kim , Young-Pil Kim , Kwan-Heum Lee , Sun-Ghil Lee
发明人： Jin-Bum Kim , Young-Pil Kim , Kwan-Heum Lee , Sun-Ghil Lee
IPC分类号： H01L21/8242 , H01L27/108 , H01L21/285 , H01L21/768 , H01L49/02
CPC分类号： H01L21/285 , H01L21/76843 , H01L21/76849 , H01L21/76889 , H01L27/10855 , H01L28/91
摘要： In a method of forming an ohmic layer of a DRAM device, the metal silicide layer between the storage node contact plug and the lower electrode of a capacitor is formed as the ohmic layer by a first heat treatment under a first temperature and an instantaneous second heat treatment under a second temperature higher than the first temperature. Thus, the metal silicide layer has a thermo-stable crystal structure and little or no agglomeration occurs on the metal silicide layer in the high temperature process. Accordingly, the sheet resistance of the ohmic layer may not increase in spite of the subsequent high temperature process.
摘要翻译：在形成DRAM器件的欧姆层的方法中，通过在第一温度和瞬时第二次加热下的第一次热处理将存储节点接触插塞和电容器的下部电极之间的金属硅化物层形成为欧姆层在比第一温度高的第二温度下进行处理。因此，金属硅化物层具有热稳定的晶体结构，并且在高温工艺中在金属硅化物层上几乎或不发生聚集。因此，尽管随后的高温处理，欧姆层的薄层电阻也可能不增加。

3. 发明授权

US08530303B2 Method of fabricating semiconductor device 有权
标题翻译：制造半导体器件的方法
公开(公告)号：US08530303B2
公开(公告)日：2013-09-10
申请号：US13243147
申请日：2011-09-23
申请人： Jin-Bum Kim , Chul-Sung Kim , Yu-Gyun Shin , Dae-Yong Kim , Joon-Gon Lee , Kwang-Young Lee
发明人： Jin-Bum Kim , Chul-Sung Kim , Yu-Gyun Shin , Dae-Yong Kim , Joon-Gon Lee , Kwang-Young Lee
IPC分类号： H01L21/8249
CPC分类号： H01L21/823807 , H01L21/823814
摘要： A method of fabricating a semiconductor includes providing a substrate having a first region and a second region defined therein, forming a first gate and a first source and drain region in the first region and forming a second gate and a second source and drain region in the second region, forming an epitaxial layer in the second source and drain region, forming a first metal silicide layer in the first source and drain region, forming an interlayer dielectric layer on the first region and the second region, forming a plurality of contact holes exposing the first metal silicide layer and the epitaxial layer while penetrating the interlayer dielectric layer, forming a second metal silicide layer in the exposed epitaxial layer, and forming a plurality of contacts contacting the first and second metal silicide layers by filling the plurality of contact holes.
摘要翻译：制造半导体的方法包括提供具有限定在其中的第一区域和第二区域的衬底，在第一区域中形成第一栅极和第一源极和漏极区域，并在第一区域中形成第二栅极和第二源极和漏极区域在所述第二源极和漏极区域中形成外延层，在所述第一源极和漏极区域中形成第一金属硅化物层，在所述第一区域和所述第二区域上形成层间电介质层，形成多个接触孔，第一金属硅化物层和外延层，同时穿透层间电介质层，在暴露的外延层中形成第二金属硅化物层，并且通过填充多个接触孔形成与第一和第二金属硅化物层接触的多个触点。

4. 发明申请

US20120003799A1 Methods of manufacturing semiconductor devices with Si and SiGe epitaxial layers 有权
标题翻译：制造具有Si和SiGe外延层的半导体器件的方法
公开(公告)号：US20120003799A1
公开(公告)日：2012-01-05
申请号：US13137733
申请日：2011-09-08
申请人： Jin-bum Kim , Si-young Choi , Hyung-Ik Lee , Ki-hong Kim , Yong-koo Kyoung
发明人： Jin-bum Kim , Si-young Choi , Hyung-Ik Lee , Ki-hong Kim , Yong-koo Kyoung
IPC分类号： H01L21/8238
CPC分类号： H01L21/823814 , H01L21/26506 , H01L21/28518 , H01L21/28525 , H01L21/76804 , H01L21/76814 , H01L21/76831 , H01L21/76855 , H01L21/823871 , H01L23/485 , H01L29/165 , H01L29/665 , H01L29/6659 , H01L29/66628 , H01L29/66636 , H01L29/7834 , H01L29/7848 , H01L2924/0002 , H01L2924/00
摘要： Methods of manufacturing semiconductor devices may include forming a first layer on a first active region (P-channel FET), forming a second layer on a second active region (N-channel FET), the first and second layers including a silicon germanium (SiGe) epitaxial layer sequentially stacked on a silicon (Si) epitaxial layer, forming a first contact hole in an interlayer insulating film including a first lower region exposing the SiGe epitaxial layer of the first layer, forming a second contact hole in the interlayer insulating film including a second lower region penetrating through the SiGe epitaxial layer of the second layer and exposing the Si epitaxial layer of the second layer, forming a first metal silicide film including germanium (Ge) in the first lower region, forming a second metal silicide film not including Ge in the second lower region simultaneously with the forming of the first metal silicide film.
摘要翻译：制造半导体器件的方法可以包括在第一有源区（P沟道FET）上形成第一层，在第二有源区（N沟道FET）上形成第二层，第一和第二层包括硅锗（SiGe ）外延层，其顺序堆叠在硅（Si）外延层上，在包括暴露第一层的SiGe外延层的第一下部区域的层间绝缘膜中形成第一接触孔，在层间绝缘膜中形成第二接触孔，所述第二接触孔包括穿过第二层的SiGe外延层并暴露第二层的Si外延层的第二下部区域，在第一下部区域中形成包括锗（Ge）的第一金属硅化物膜，形成不包括第二金属硅化物膜的第二金属硅化物膜 Ge在第二下部区域同时形成第一金属硅化物膜。

5. 发明申请

US20110306205A1 Semiconductor Device and Method of Fabricating the Same 有权
标题翻译：半导体器件及其制造方法
公开(公告)号：US20110306205A1
公开(公告)日：2011-12-15
申请号：US13105195
申请日：2011-05-11
申请人： Byung-Hak Lee , Yu-Gyun Shin , Sang-Woo Lee , Sun-Ghil Lee , Jin-Bum Kim , Joon-Gon Lee
发明人： Byung-Hak Lee , Yu-Gyun Shin , Sang-Woo Lee , Sun-Ghil Lee , Jin-Bum Kim , Joon-Gon Lee
IPC分类号： H01L21/3205
CPC分类号： H01L21/28518 , H01L21/823807 , H01L21/823814
摘要： Methods of forming a semiconductor device include providing a substrate having an area including a source and a drain region of a transistor. A nickel (Ni) metal film is formed on the substrate area including the source and the drain region. A first heat-treatment process is performed including heating the substrate including the metal film from a first temperature to a second temperature at a first ramping rate and holding the substrate including the metal film at the second temperature for a first period of time. A second heat-treatment process is then performed including heating the substrate including the metal film from a third temperature to a fourth temperature at a second ramping rate and holding the substrate at the fourth temperature for a second period of time. The fourth temperature is different from the second temperature and the second period of time is different from the first period of time. The sequentially performed first and second heat-treatment processes convert the Ni metal layer on the source and drain regions into a NiSi layer on the source and drain regions and a NiSi2 layer between the NiSi layer and the source and drain regions.
摘要翻译：形成半导体器件的方法包括提供具有包括晶体管的源极和漏极区域的区域的衬底。在包括源极和漏极区域的衬底区域上形成镍（Ni）金属膜。执行第一热处理工艺，包括以第一斜率从第一温度至第二温度加热包括金属膜的基板，并将包含金属膜的基板在第二温度下保持第一时间段。然后执行第二热处理工艺，包括以第二斜率从第三温度至第四温度加热包括金属膜的衬底，并将衬底保持在第四温度第二时间段。第四温度与第二温度不同，第二时间段与第一时间段不同。依次执行的第一和第二热处理工艺将源极和漏极区域上的Ni金属层转换成源极和漏极区域上的NiSi层以及NiSi层与源极和漏极区域之间的NiSi 2层。

6. 发明申请

US20100001349A1 SEMICONDUCTOR DEVICE 审中-公开
标题翻译：半导体器件
公开(公告)号：US20100001349A1
公开(公告)日：2010-01-07
申请号：US12495501
申请日：2009-06-30
申请人： Jin-Bum Kim , Kwan-Heum Lee , Seung-Hun Lee , Byeong-Chan Lee , Sun-Ghil Lee
发明人： Jin-Bum Kim , Kwan-Heum Lee , Seung-Hun Lee , Byeong-Chan Lee , Sun-Ghil Lee
IPC分类号： H01L27/088
CPC分类号： H01L21/823425 , H01L21/823418 , H01L27/11521 , H01L27/11524 , H01L29/40114 , H01L29/66825
摘要： A semiconductor device can include a first gate electrode including a gate insulating pattern, a gate conductive pattern and a capping pattern that are sequentially stacked on a semiconductor substrate, and a first spacer of a low dielectric constant disposed on a lower sidewall of the first gate electrode. A second spacer of a high dielectric constant, that is greater than the low dielectric constant, is disposed on an upper sidewall of the first gate electrode above the first spacer.
摘要翻译：半导体器件可以包括第一栅电极，其包括依次层叠在半导体衬底上的栅极绝缘图案，栅极导电图案和覆盖图案，以及布置在第一栅极的下侧壁上的低介电常数的第一间隔物电极。高介电常数的第二间隔物大于低介电常数，设置在第一间隔物上方的第一栅电极的上侧壁上。

7. 发明申请

US20090181301A1 LITHIUM SECONDARY BATTERY 有权
标题翻译：锂二次电池
公开(公告)号：US20090181301A1
公开(公告)日：2009-07-16
申请号：US12334337
申请日：2008-12-12
申请人： Yong-Shik Kim , Jin-Bum Kim , Jin-Sung Kim , Na-Rae Park
发明人： Yong-Shik Kim , Jin-Bum Kim , Jin-Sung Kim , Na-Rae Park
IPC分类号： H01M6/04
CPC分类号： H01M10/0525 , H01M4/364 , H01M4/38 , H01M4/386 , H01M4/387 , H01M4/405 , H01M4/587 , H01M4/624 , H01M10/0567 , H01M10/4235
摘要： A lithium secondary battery includes a positive electrode, a negative electrode, a separator separating the positive electrode and the negative electrode, and an electrolyte. The negative electrode active material of the negative electrode includes a material that is capable of reversibly intercalating and deintercalating lithium ions and a metallic material capable of alloying with lithium. The electrolyte includes a chemical compound containing a nitrile (—CN) radical.
摘要翻译：锂二次电池包括正极，负极，分离正极和负极的隔板和电解质。负极的负极活性物质包括能够可逆地插入和脱嵌锂离子的材料以及能够与锂合金化的金属材料。电解质包含含有腈（-CN）基团的化合物。

8. 发明申请

US20070134880A1 Field effect transistors having elevated source/drain regions and methods of manufacturing the same 有权
标题翻译：具有升高的源极/漏极区域的场效应晶体管及其制造方法
公开(公告)号：US20070134880A1
公开(公告)日：2007-06-14
申请号：US11636139
申请日：2006-12-08
申请人： Min-Gu Kang , Ki-Hong Kim , Jin-Bum Kim , Jung-Yun Won , In-Sun Jung
发明人： Min-Gu Kang , Ki-Hong Kim , Jin-Bum Kim , Jung-Yun Won , In-Sun Jung
IPC分类号： H01L21/336
CPC分类号： H01L29/66628 , H01L21/0242 , H01L21/02458 , H01L21/02491 , H01L21/0254 , H01L21/0262 , H01L21/02636 , H01L21/02642 , H01L21/02664 , H01L21/26513 , H01L27/10873 , H01L29/517
摘要： Methods of manufacturing a field effect transistor include forming a gate pattern on a substrate. A gate spacer is formed on a sidewall of the gate pattern. A first layer is formed from a surface of the substrate and contacting the gate spacer using a first selective epitaxial growth (SEG) process at a first temperature. A second layer is formed from a surface of the first layer and contacting the gate spacer using a second SEG process at a second temperature. The second temperature is lower than the first temperature. The first and second layers define elevated source/drain regions.
摘要翻译：制造场效应晶体管的方法包括在衬底上形成栅极图案。栅极间隔物形成在栅极图案的侧壁上。第一层由衬底的表面形成并且在第一温度下使用第一选择性外延生长（SEG）工艺与栅极间隔物接触。第二层由第一层的表面形成，并在第二温度下使用第二SEG工艺与栅极间隔物接触。第二个温度低于第一个温度。第一和第二层限定升高的源极/漏极区域。

9. 发明申请

US20070072399A1 Semiconductor Devices Having Epitaxial Layers with Suppressed Lateral Growth and Related Methods of Manufacturing Such Devices 审中-公开
标题翻译：具有抑制侧向生长的外延层的半导体器件及其相关制造方法
公开(公告)号：US20070072399A1
公开(公告)日：2007-03-29
申请号：US11530498
申请日：2006-09-11
申请人： Young-Pil Kim , Jin-Bum Kim , Jun-Ho Lee , Hyung-ik Lee , Hion-Suck Baik
发明人： Young-Pil Kim , Jin-Bum Kim , Jun-Ho Lee , Hyung-ik Lee , Hion-Suck Baik
IPC分类号： H01L21/20 , H01L21/00 , H01L21/36 , H01L31/20
CPC分类号： H01L21/02381 , H01L21/0245 , H01L21/0251 , H01L21/02532 , H01L21/02587 , H01L21/0262 , H01L21/02639 , H01L29/66628 , H01L31/0543 , Y02E10/52
摘要： Semiconductor devices are provided having a selective epitaxial growth layer that exhibits suppressed lateral growth. These semiconductor devices may include a semiconductor substrate having a silicon region, and an epitaxial growth layer formed on the silicon region. The epitaxial growth layer may comprise alternatively stacked silicon and silicon germanium epitaxial layers. The silicon germanium epitaxial layer may be thinner than the silicon epitaxial layers.
摘要翻译：提供具有显示抑制的横向生长的选择性外延生长层的半导体器件。这些半导体器件可以包括具有硅区域的半导体衬底和形成在硅区域上的外延生长层。外延生长层可以包括交替堆叠的硅和锗锗外延层。硅锗外延层可以比硅外延层薄。

10. 发明授权

US10381126B2 Positive electrode for rechargeable lithium battery and rechargeable lithium battery including same 有权
公开(公告)号：US10381126B2
公开(公告)日：2019-08-13
申请号：US12684868
申请日：2010-01-08
申请人： Jin-Bum Kim
发明人： Jin-Bum Kim
IPC分类号： H01M4/04 , H01M4/13 , H01M4/52 , H01M4/62 , H01B1/24 , H01M4/131 , H01M4/139 , H01M4/525 , H01M10/0525
摘要： A positive electrode for a rechargeable lithium battery and a rechargeable lithium battery including the same. The positive electrode includes a positive active material, a binder, and a conductive material, wherein a weight ratio of the binder and conductive material, and the positive active material, ranges from 3:97 to 5:95 wt %, and a weight ratio of the binder and the conductive material ranges from 1.5 to 3:1.

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