专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明授权

US07595246B2 Methods of manufacturing field effect transistors having elevated source/drain regions 有权
标题翻译：制造具有升高的源极/漏极区域的场效应晶体管的方法
公开(公告)号：US07595246B2
公开(公告)日：2009-09-29
申请号：US11636139
申请日：2006-12-08
申请人： Min-Gu Kang , Ki-Hong Kim , Jin-Bum Kim , Jung-Yun Won , In-Sun Jung
发明人： Min-Gu Kang , Ki-Hong Kim , Jin-Bum Kim , Jung-Yun Won , In-Sun Jung
IPC分类号： H01L21/336
CPC分类号： H01L29/66628 , H01L21/0242 , H01L21/02458 , H01L21/02491 , H01L21/0254 , H01L21/0262 , H01L21/02636 , H01L21/02642 , H01L21/02664 , H01L21/26513 , H01L27/10873 , H01L29/517
摘要： Methods of manufacturing a field effect transistor include forming a gate pattern on a substrate. A gate spacer is formed on a sidewall of the gate pattern. A first layer is formed from a surface of the substrate and contacting the gate spacer using a first selective epitaxial growth (SEG) process at a first temperature. A second layer is formed from a surface of the first layer and contacting the gate spacer using a second SEG process at a second temperature. The second temperature is lower than the first temperature. The first and second layers define elevated source/drain regions.
摘要翻译：制造场效应晶体管的方法包括在衬底上形成栅极图案。栅极间隔物形成在栅极图案的侧壁上。第一层由衬底的表面形成并且在第一温度下使用第一选择性外延生长（SEG）工艺与栅极间隔物接触。第二层由第一层的表面形成，并在第二温度下使用第二SEG工艺与栅极间隔物接触。第二个温度低于第一个温度。第一层和第二层限定升高的源/漏区。

2. 发明申请

US20070134880A1 Field effect transistors having elevated source/drain regions and methods of manufacturing the same 有权
标题翻译：具有升高的源极/漏极区域的场效应晶体管及其制造方法
公开(公告)号：US20070134880A1
公开(公告)日：2007-06-14
申请号：US11636139
申请日：2006-12-08
申请人： Min-Gu Kang , Ki-Hong Kim , Jin-Bum Kim , Jung-Yun Won , In-Sun Jung
发明人： Min-Gu Kang , Ki-Hong Kim , Jin-Bum Kim , Jung-Yun Won , In-Sun Jung
IPC分类号： H01L21/336
CPC分类号： H01L29/66628 , H01L21/0242 , H01L21/02458 , H01L21/02491 , H01L21/0254 , H01L21/0262 , H01L21/02636 , H01L21/02642 , H01L21/02664 , H01L21/26513 , H01L27/10873 , H01L29/517
摘要： Methods of manufacturing a field effect transistor include forming a gate pattern on a substrate. A gate spacer is formed on a sidewall of the gate pattern. A first layer is formed from a surface of the substrate and contacting the gate spacer using a first selective epitaxial growth (SEG) process at a first temperature. A second layer is formed from a surface of the first layer and contacting the gate spacer using a second SEG process at a second temperature. The second temperature is lower than the first temperature. The first and second layers define elevated source/drain regions.
摘要翻译：制造场效应晶体管的方法包括在衬底上形成栅极图案。栅极间隔物形成在栅极图案的侧壁上。第一层由衬底的表面形成并且在第一温度下使用第一选择性外延生长（SEG）工艺与栅极间隔物接触。第二层由第一层的表面形成，并在第二温度下使用第二SEG工艺与栅极间隔物接触。第二个温度低于第一个温度。第一和第二层限定升高的源极/漏极区域。

3. 发明申请

US20100031581A1 Door for washing machine 有权
标题翻译：洗衣机门
公开(公告)号：US20100031581A1
公开(公告)日：2010-02-11
申请号：US12385556
申请日：2009-04-10
申请人： Min-Gu Kang , Kyu-Chul Lee , Chang-Woo Son
发明人： Min-Gu Kang , Kyu-Chul Lee , Chang-Woo Son
IPC分类号： E06B5/00
CPC分类号： D06F39/14
摘要： A door for a washing machine is disclosed. A door for a washing machine includes an inner frame having an opening with a predetermined size, an outer frame provided at a front surface of the inner frame, having an opening in communication with the opening of the inner frame, a glass member fitted between the inner and outer frames, covering the openings of the inner and outer frames, a decorative member provided at a front surface of the outer frame, having an opening in communication with the openings, and a front cover fitted between the decorative member and the outer frame, covering the openings of the inner and outer frames and the decorative member, the front cover having a positioning portion determining a position of the front cover coupled to the outer frame.
摘要翻译：公开了一种用于洗衣机的门。一种用于洗衣机的门包括具有预定尺寸的开口的内框架，设置在内框架的前表面处的外框架，具有与内框架的开口连通的开口;玻璃构件，内框架和外框架，覆盖内框架和外框架的开口;设置在外框架的前表面处的装饰构件，具有与开口连通的开口，以及装配构件和外框架之间的前盖覆盖内框架和外框架和装饰构件的开口，前盖具有确定联接到外框架的前盖的位置的定位部分。

4. 发明授权

US08151603B2 Door for washing machine 有权
标题翻译：洗衣机门
公开(公告)号：US08151603B2
公开(公告)日：2012-04-10
申请号：US12385556
申请日：2009-04-10
申请人： Min-Gu Kang , Kyu-Chul Lee , Chang-Woo Son
发明人： Min-Gu Kang , Kyu-Chul Lee , Chang-Woo Son
IPC分类号： D06F37/28
CPC分类号： D06F39/14
摘要： A door for a washing machine is disclosed. A door for a washing machine includes an inner frame having an opening with a predetermined size, an outer frame provided at a front surface of the inner frame, having an opening in communication with the opening of the inner frame, a glass member fitted between the inner and outer frames, covering the openings of the inner and outer frames, a decorative member provided at a front surface of the outer frame, having an opening in communication with the openings, and a front cover fitted between the decorative member and the outer frame, covering the openings of the inner and outer frames and the decorative member, the front cover having a positioning portion determining a position of the front cover coupled to the outer frame.
摘要翻译：公开了一种用于洗衣机的门。一种用于洗衣机的门包括具有预定尺寸的开口的内框架，设置在内框架的前表面处的外框架，具有与内框架的开口连通的开口;玻璃构件，内框架和外框架，覆盖内框架和外框架的开口;设置在外框架的前表面处的装饰构件，具有与开口连通的开口，以及装配构件和外框架之间的前盖覆盖内框架和外框架和装饰构件的开口，前盖具有确定联接到外框架的前盖的位置的定位部分。

5. 发明申请

US20080093674A1 FIN FIELD EFFECT TRANSISTOR AND METHOD OF MANUFACTURING THE SAME 有权
标题翻译： FIN场效应晶体管及其制造方法
公开(公告)号：US20080093674A1
公开(公告)日：2008-04-24
申请号：US11952676
申请日：2007-12-07
申请人： Deok-Hyung Lee , Yu-Gyun Shin , Jong-Wook Lee , Min-Gu Kang
发明人： Deok-Hyung Lee , Yu-Gyun Shin , Jong-Wook Lee , Min-Gu Kang
IPC分类号： H01L29/78
CPC分类号： H01L29/7851 , H01L29/66795 , H01L29/7854
摘要： In a fin field effect transistor (FET), an active pattern protrudes in a vertical direction from a substrate and extends across the substrate in a first horizontal direction. A first silicon nitride pattern is formed on the active pattern, and a first oxide pattern and a second silicon nitride pattern are sequentially formed on the substrate and on a sidewall of a lower portion of the active pattern. A device isolation layer is formed on the second silicon nitride pattern, and a top surface of the device isolation layer is coplanar with top surfaces of the oxide pattern and the second silicon nitride pattern. A buffer pattern having an etching selectivity with respect to the second silicon nitride pattern is formed between the first oxide pattern and the second silicon nitride pattern. Internal stresses that can be generated in sidewalls of the active pattern are sufficiently released and an original shape of the first silicon nitride pattern remains unchanged, thereby improving electrical characteristics of the fin FET.
摘要翻译：在鳍状场效应晶体管（FET）中，有源图案在垂直方向上从基板突出，并且在第一水平方向上延伸穿过基板。第一氮化硅图案形成在有源图案上，并且第一氧化物图案和第二氮化硅图案依次形成在衬底上和活性图案的下部的侧壁上。在第二氮化硅图案上形成器件隔离层，器件隔离层的顶表面与氧化物图案和第二氮化硅图案的顶表面共面。在第一氧化物图案和第二氮化硅图案之间形成具有相对于第二氮化硅图案的蚀刻选择性的缓冲图案。可以在有源图案的侧壁中产生的内部应力被充分地释放，并且第一氮化硅图案的原始形状保持不变，从而改善了鳍式FET的电特性。

6. 发明授权

US09412159B2 Method for inspecting flat panel 有权
标题翻译：平板检查方法
公开(公告)号：US09412159B2
公开(公告)日：2016-08-09
申请号：US14343345
申请日：2012-09-13
申请人： Jai-Ho Son , Hyun-Min Lee , Min-Gu Kang , Sang-Yoon Lee , Ssang-Gun Lim
发明人： Jai-Ho Son , Hyun-Min Lee , Min-Gu Kang , Sang-Yoon Lee , Ssang-Gun Lim
IPC分类号： H04N7/18 , G06T7/00 , G01N21/95 , G02F1/13
CPC分类号： G06T7/0004 , G01N21/95 , G01N2021/9513 , G02F1/1309 , G06T2207/30121 , H04N7/18
摘要： Disclosed is a method for inspecting a flat panel. The method for inspecting the flat panel includes the steps of: arranging a camera at a measurement location of the flat panel by horizontally moving at least one of the flat panel and the camera; automatically focusing the camera with respect to a measuring target of the flat panel at the measurement location; acquiring a plurality of images for the measuring target by vertically moving the focused camera within a set region on the basis of the present location of the camera when focusing the camera; selecting the image having the most definition for the measuring target among the acquired images; processing the selected image; and determining whether the measuring target is defective or not.
摘要翻译：公开了一种用于检查平板的方法。用于检查平板的方法包括以下步骤：通过水平移动平板和相机中的至少一个来将相机布置在平板的测量位置; 在测量位置相对于平板测量对象自动聚焦相机; 在对照相机进行聚焦时，基于相机的当前位置垂直移动设定区域内的聚焦照相机，来获取测量对象的多个图像; 在所获取的图像中选择具有用于测量目标的最高定义的图像; 处理所选图像; 并且确定测量目标是否有缺陷。

7. 发明申请

US20090142892A1 Method of fabricating semiconductor device having thin strained relaxation buffer pattern and related device 审中-公开
标题翻译：制造具有薄应变松弛缓冲图案的半导体器件及其相关器件的方法
公开(公告)号：US20090142892A1
公开(公告)日：2009-06-04
申请号：US11984538
申请日：2007-11-19
申请人： Byeong-Chan Lee , Si-Young Choi , Yong-Hoon Son , In-Soo Jung , Min-Gu Kang , Pil-Kyu Kang
发明人： Byeong-Chan Lee , Si-Young Choi , Yong-Hoon Son , In-Soo Jung , Min-Gu Kang , Pil-Kyu Kang
IPC分类号： H01L21/336 , H01L21/20
CPC分类号： H01L21/823807 , H01L21/28052 , H01L21/823892 , H01L29/1054 , H01L29/4933 , H01L29/517
摘要： A method of fabricating a semiconductor device includes forming a buffer pattern on a substrate, the buffer pattern including germanium, recrystallizing the buffer pattern to form a strained relaxation buffer pattern, and forming a tensile silicon cap on the strained relaxation buffer pattern, the cap being under tensile strain.
摘要翻译：制造半导体器件的方法包括在衬底上形成缓冲图案，缓冲图案包括锗，使缓冲图案重结晶，形成应变弛豫缓冲图案，并在应变张弛缓冲图案上形成拉伸硅帽，在拉伸应变下。

8. 发明申请

US20060189058A1 Fin type field effect transistors and methods of manufacturing the same 有权
标题翻译：鳍式场效应晶体管及其制造方法
公开(公告)号：US20060189058A1
公开(公告)日：2006-08-24
申请号：US11359000
申请日：2006-02-22
申请人： Jong-Wook Lee , Deok-Hyung Lee , Min-Gu Kang , Yu-Gyun Shin
发明人： Jong-Wook Lee , Deok-Hyung Lee , Min-Gu Kang , Yu-Gyun Shin
IPC分类号： H01L21/8234 , H01L29/76
CPC分类号： H01L29/78618 , H01L29/66545 , H01L29/66795 , H01L29/785
摘要： A fin type field effect transistor includes a semiconductor substrate, an active fin, a first hard mask layer pattern, a gate insulation layer pattern, a first conductive layer pattern, and source/drain regions. The active fin includes a semiconductor material and is formed on the substrate and extends in a direction away from a major surface of the substrate. The first hard mask layer pattern is formed on a distal surface of the active fin from the substrate. The gate insulation layer is formed on a sidewall portion of the active fin. The first conductive layer pattern includes a metal silicide and is formed on surfaces of the substrate and the gate insulation layer pattern, and on a sidewall of the first hard mask pattern. The source/drain regions are formed in the active fin on opposite sides of the first conductive layer pattern.
摘要翻译：鳍型场效应晶体管包括半导体衬底，有源鳍，第一硬掩模层图案，栅极绝缘层图案，第一导电层图案和源极/漏极区域。活性鳍片包括半导体材料，并且形成在基底上并沿远离基底的主表面的方向延伸。第一硬掩模层图案形成在有源鳍片的远离表面上的基底上。栅极绝缘层形成在有源鳍片的侧壁部分上。第一导电层图案包括金属硅化物，并且形成在基板和栅极绝缘层图案的表面上，以及在第一硬掩模图案的侧壁上。源极/漏极区域形成在第一导电层图案的相对侧上的有源鳍片中。

9. 发明授权

US07652340B2 Fin field effect transistor and method of manufacturing the same 有权
标题翻译： Fin场效应晶体管及其制造方法
公开(公告)号：US07652340B2
公开(公告)日：2010-01-26
申请号：US11952676
申请日：2007-12-07
申请人： Deok-Hyung Lee , Yu-Gyun Shin , Jong-Wook Lee , Min-Gu Kang
发明人： Deok-Hyung Lee , Yu-Gyun Shin , Jong-Wook Lee , Min-Gu Kang
IPC分类号： H01L29/78
CPC分类号： H01L29/7851 , H01L29/66795 , H01L29/7854
摘要： In a fin field effect transistor (FET), an active pattern protrudes in a vertical direction from a substrate and extends across the substrate in a first horizontal direction. A first silicon nitride pattern is formed on the active pattern, and a first oxide pattern and a second silicon nitride pattern are sequentially formed on the substrate and on a sidewall of a lower portion of the active pattern. A device isolation layer is formed on the second silicon nitride pattern, and a top surface of the device isolation layer is coplanar with top surfaces of the oxide pattern and the second silicon nitride pattern. A buffer pattern having an etching selectivity with respect to the second silicon nitride pattern is formed between the first oxide pattern and the second silicon nitride pattern. Internal stresses that can be generated in sidewalls of the active pattern are sufficiently released and an original shape of the first silicon nitride pattern remains unchanged, thereby improving electrical characteristics of the fin FET.
摘要翻译：在鳍状场效应晶体管（FET）中，有源图案在垂直方向上从基板突出，并且在第一水平方向上延伸穿过基板。第一氮化硅图案形成在有源图案上，并且第一氧化物图案和第二氮化硅图案依次形成在衬底上和活性图案的下部的侧壁上。在第二氮化硅图案上形成器件隔离层，器件隔离层的顶表面与氧化物图案和第二氮化硅图案的顶表面共面。在第一氧化物图案和第二氮化硅图案之间形成具有相对于第二氮化硅图案的蚀刻选择性的缓冲图案。可以在有源图案的侧壁中产生的内部应力被充分地释放，并且第一氮化硅图案的原始形状保持不变，从而改善了鳍式FET的电特性。

10. 发明授权

US07501674B2 Semiconductor device having fin transistor and planar transistor and associated methods of manufacture 有权
标题翻译：具有鳍式晶体管和平面晶体管的半导体器件及其制造方法
公开(公告)号：US07501674B2
公开(公告)日：2009-03-10
申请号：US11244136
申请日：2005-10-06
申请人： Deok-Hyung Lee , Yu-Gyun Shin , Jong-Wook Lee , Min-Gu Kang
发明人： Deok-Hyung Lee , Yu-Gyun Shin , Jong-Wook Lee , Min-Gu Kang
IPC分类号： H01L21/00
CPC分类号： H01L29/7851 , H01L21/823431 , H01L21/84 , H01L27/1203 , H01L29/66795
摘要： Disclosed is a fin transistor and a planar transistor and a method of forming the same. The fin transistor and the planar transistor are formed to have gate electrodes with similar thicknesses by selectively recessing a semiconductor substrate in a planar region where the planar transistor is formed.
摘要翻译：公开了鳍式晶体管和平面晶体管及其形成方法。通过在形成平面晶体管的平面区域中选择性地凹入半导体衬底，将鳍状晶体管和平面晶体管形成为具有相似厚度的栅电极。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式