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1. 发明授权

US08760947B2 Apparatus protecting software of sentinel logic circuitry against unauthorized access 有权
标题翻译：保护哨兵逻辑电路的软件以防止未授权访问的装置
公开(公告)号：US08760947B2
公开(公告)日：2014-06-24
申请号：US13423353
申请日：2012-03-19
申请人： Johann Zipperer
发明人： Johann Zipperer
IPC分类号： G11C7/00
CPC分类号： G06F12/1425 , G06F21/53
摘要： A method of protecting software for embedded applications against unauthorized access. Software to be protected is loaded into a protected memory area. Access to the protected memory area is controlled by sentinel logic circuitry. The sentinel logic circuitry allows access to the protected memory area from only either within the protected memory area or from outside of the protected memory area but through a dedicated memory location within the protected memory area. The dedicated memory location then points to protected address locations within the protected memory area.
摘要翻译：一种保护嵌入式应用软件免受未经授权访问的方法。要保护的软件加载到受保护的内存区域。受保护的存储器区域的访问由哨兵逻辑电路控制。前哨逻辑电路仅允许在受保护的存储器区域内或从受保护的存储器区域的外部访问受保护的存储器区域，但是通过受保护的存储器区域内的专用存储器位置。然后，专用存储器位置指向受保护存储器区域内的受保护的地址位置。

2. 发明授权

US08140881B2 Circuitry and method for detection of network node aging in communication networks 有权
标题翻译：通信网络中网络节点老化检测的电路及方法
公开(公告)号：US08140881B2
公开(公告)日：2012-03-20
申请号：US12355286
申请日：2009-01-16
申请人： Johann Zipperer
发明人： Johann Zipperer
IPC分类号： G06F1/12
CPC分类号： H04L12/40 , G06F1/14 , H04J3/0652 , H04L7/0331
摘要： The network node includes a local crystal oscillator for providing a time reference derived from the clock signal produced by the local crystal oscillator, a reset stage for resetting the network node in response to a bus reset pulse received through the network and a control means for issuing a bus reset pulse of a predetermined length substantially greater than a clock period of the clock signal of the local crystal oscillator. Further the network node includes a bus reset detector for determining a length of the received bus reset pulse based on the local time reference. The bus reset detector in the network node is also adapted to adjust the local time reference based on the determined length of the received bus reset pulse.
摘要翻译：网络节点包括用于提供由本地晶体振荡器产生的时钟信号导出的时间参考的本地晶体振荡器，用于响应于通过网络接收的总线复位脉冲来复位网络节点的复位级，以及用于发出预定长度的总线复位脉冲基本上大于本地晶体振荡器的时钟信号的时钟周期。此外，网络节点包括总线复位检测器，用于基于本地时间基准来确定所接收的总线复位脉冲的长度。网络节点中的总线复位检测器还适于基于所确定的接收总线复位脉冲的长度来调整本地时间基准。

3. 发明申请

US20120191934A1 Apparatus Protecting Software of Sentinel Logic Circuitry Against Unauthorized Access 有权
标题翻译：设备保护哨兵逻辑电路免受未经授权访问的软件
公开(公告)号：US20120191934A1
公开(公告)日：2012-07-26
申请号：US13423353
申请日：2012-03-19
申请人： Johann Zipperer
发明人： Johann Zipperer
IPC分类号： G06F12/14
CPC分类号： G06F12/1425 , G06F21/53
摘要： A method of protecting software for embedded applications against unauthorized access. Software to be protected is loaded into a protected memory area. Access to the protected memory area is controlled by sentinel logic circuitry. The sentinel logic circuitry allows access to the protected memory area from only either within the protected memory area or from outside of the protected memory area but through a dedicated memory location within the protected memory area. The dedicated memory location then points to protected address locations within the protected memory area.
摘要翻译：一种保护嵌入式应用软件免受未经授权访问的方法。要保护的软件加载到受保护的内存区域。受保护的存储器区域的访问由哨兵逻辑电路控制。前哨逻辑电路仅允许在受保护的存储器区域内或从受保护的存储器区域的外部访问受保护的存储器区域，但是通过受保护的存储器区域内的专用存储器位置。然后，专用存储器位置指向受保护存储器区域内的受保护的地址位置。

4. 发明申请

US20100235698A1 JTAG Mailbox 有权
标题翻译： JTAG邮箱
公开(公告)号：US20100235698A1
公开(公告)日：2010-09-16
申请号：US12718274
申请日：2010-03-05
申请人： Horst Diewald , Volker Rzehak , Johann Zipperer
发明人： Horst Diewald , Volker Rzehak , Johann Zipperer
IPC分类号： G01R31/3177 , G06F11/25
CPC分类号： G01R31/318572 , G01R31/318555
摘要： An electronic device comprises a processing stage, a JTAG port including a test data input pin (TDI), a test data output pin (TDO), a test mode select pin (TMS), a test clock pin (TCK), and a test access port (TAP) controller having a data register (DR) shift state and an instruction register shift (IR) state. The electronic device operates in a scan event mode automatically mapped an incoming event to the TDO pin.
摘要翻译：电子设备包括处理级，JTAG端口，包括测试数据输入引脚（TDI），测试数据输出引脚（TDO），测试模式选择引脚（TMS），测试时钟引脚（TCK）和测试具有数据寄存器（DR）移位状态和指令寄存器移位（IR）状态的访问端口（TAP）控制器。电子设备以扫描事件模式运行，将传入事件自动映射到TDO引脚。

5. 发明授权

US09690718B2 Method for protecting software of embedded applications against unauthorized access 有权
公开(公告)号：US09690718B2
公开(公告)日：2017-06-27
申请号：US12563712
申请日：2009-09-21
申请人： Johann Zipperer
发明人： Johann Zipperer
IPC分类号： G06F12/14 , G06F21/53
CPC分类号： G06F12/1425 , G06F21/53
摘要： A method of protecting software for embedded applications against unauthorized access. Software to be protected is loaded into a protected memory area. Access to the protected memory area is controlled by sentinel logic circuitry. The sentinel logic circuitry allows access to the protected memory area from only either within the protected memory area or from outside of the protected memory area but through a dedicated memory location within the protected memory area. The dedicated memory location then points to protected address locations within the protected memory area.

6. 发明授权

US09489208B2 Operating a pipeline flattener in order to track instructions for complex breakpoints 有权
标题翻译：操作管道压平机，以便跟踪复杂断点的指令
公开(公告)号：US09489208B2
公开(公告)日：2016-11-08
申请号：US13473260
申请日：2012-05-16
申请人： Markus Koesler , Johann Zipperer , Christian Wiencke , Wolfgang Lutsch
发明人： Markus Koesler , Johann Zipperer , Christian Wiencke , Wolfgang Lutsch
IPC分类号： G06F11/36 , G06F9/38 , G06F11/267
CPC分类号： G06F9/3867 , G06F9/30098 , G06F9/3802 , G06F9/3869 , G06F11/267 , G06F11/3636 , G06F11/3648
摘要： A semiconductor device comprising a processor having a pipelined architecture and a pipeline flattener and a method for operating a pipeline flattener in a semiconductor device are provided. The processor comprises a pipeline having a plurality of pipeline stages and a plurality of pipeline registers that are coupled between the pipeline stages. The pipeline flattener comprises a plurality of trigger registers for storing a trigger, wherein the trigger registers are coupled between the pipeline stages.
摘要翻译：提供一种半导体器件，其包括具有流水线结构的处理器和管道平整器以及用于在半导体器件中操作管道平整器的方法。处理器包括具有多个流水线级的流水线和耦合在流水线级之间的多个流水线寄存器。管道压扁机包括多个用于存储触发器的触发寄存器，其中触发寄存器耦合在流水线级之间。

7. 发明授权

US08542047B2 Electronic device and method for low power reset 有权
标题翻译：用于低功耗复位的电子设备和方法
公开(公告)号：US08542047B2
公开(公告)日：2013-09-24
申请号：US13275862
申请日：2011-10-18
申请人： Volker Rzehak , Johann Zipperer
发明人： Volker Rzehak , Johann Zipperer
IPC分类号： H03K3/02
CPC分类号： H03K17/22 , G06F1/24
摘要： An electronic device and a method for operating an electronic device, wherein the electronic device comprises a reset stage which is configured to have a power down threshold and a power cycle threshold. The voltage level of the power cycle threshold is lower than the voltage level of the power down threshold. The two threshold levels define a first and second interval for a supply voltage of the electronic device. A first interval is between the power cycle threshold and the power down threshold. A second interval is above the power down threshold. The reset stage is further configured to provide the control signal having a defined first state in the first interval and a defined second state in the second interval. The electronic device is set to a low power reset mode if the control signal is in the first state and the electronic device is enabled to enter an active mode if the control signal is in the second state.
摘要翻译：一种用于操作电子设备的电子设备和方法，其中所述电子设备包括被配置为具有掉电阈值和功率周期阈值的复位阶段。功率周期阈值的电压电平低于掉电阈值的电压电平。两个阈值电平为电子设备的电源电压定义第一和第二间隔。第一个间隔在功率周期阈值和掉电阈值之间。第二个间隔高于掉电阈值。复位阶段还被配置为提供在第一间隔中具有定义的第一状态的控制信号和在第二间隔中的限定的第二状态。如果控制信号处于第一状态，并且如果控制信号处于第二状态，则电子设备能够进入活动模式，则将电子设备设置为低功率复位模式。

8. 发明申请

US20130093487A1 ELECTRONIC DEVICE AND METHOD FOR LOW POWER RESET 有权
标题翻译：用于低功率复位的电子设备和方法
公开(公告)号：US20130093487A1
公开(公告)日：2013-04-18
申请号：US13275862
申请日：2011-10-18
申请人： Volker Rzehak , Johann Zipperer
发明人： Volker Rzehak , Johann Zipperer
IPC分类号： H03K17/20
CPC分类号： H03K17/22 , G06F1/24
摘要： An electronic device and a method for operating an electronic device, wherein the electronic device comprises a reset stage which is configured to have a power down threshold and a power cycle threshold. The voltage level of the power cycle threshold is lower than the voltage level of the power down threshold. The two threshold levels define a first and second interval for a supply voltage of the electronic device. A first interval is between the power cycle threshold and the power down threshold. A second interval is above the power down threshold. The reset stage is further configured to provide the control signal having a defined first state in the first interval and a defined second state in the second interval. The electronic device is set to a low power reset mode if the control signal is in the first state and the electronic device is enabled to enter an active mode if the control signal is in the second state.
摘要翻译：一种用于操作电子设备的电子设备和方法，其中所述电子设备包括被配置为具有掉电阈值和功率周期阈值的复位阶段。功率周期阈值的电压电平低于掉电阈值的电压电平。两个阈值电平为电子设备的电源电压定义第一和第二间隔。第一个间隔在功率周期阈值和掉电阈值之间。第二个间隔高于掉电阈值。复位阶段还被配置为提供在第一间隔中具有定义的第一状态的控制信号和在第二间隔中的限定的第二状态。如果控制信号处于第一状态，并且如果控制信号处于第二状态，则电子设备能够进入活动模式，则将电子设备设置为低功率复位模式。

9. 发明申请

US20090207864A1 CIRCUITRY AND METHOD FOR DETECTION OF NETWORK NODE AGING IN COMMUNICATION NETWORKS 有权
标题翻译：用于检测通信网络中网络节点老化的电路和方法
公开(公告)号：US20090207864A1
公开(公告)日：2009-08-20
申请号：US12355286
申请日：2009-01-16
申请人： Johann Zipperer
发明人： Johann Zipperer
IPC分类号： H04J3/06
CPC分类号： H04L12/40 , G06F1/14 , H04J3/0652 , H04L7/0331
摘要： The network node includes a local crystal oscillator for providing a time reference derived from the clock signal produced by the local crystal oscillator, a reset stage for resetting the network node in response to a bus reset pulse received through the network and a control means for issuing a bus reset pulse of a predetermined length substantially greater than a clock period of the clock signal of the local crystal oscillator. Further the network node includes a bus reset detector for determining a length of the received bus reset pulse based on the local time reference. The bus reset detector in the network node is also adapted to adjust the local time reference based on the determined length of the received bus reset pulse.
摘要翻译：网络节点包括用于提供由本地晶体振荡器产生的时钟信号导出的时间参考的本地晶体振荡器，用于响应于通过网络接收的总线复位脉冲来复位网络节点的复位级，以及用于发出预定长度的总线复位脉冲基本上大于本地晶体振荡器的时钟信号的时钟周期。此外，网络节点包括总线复位检测器，用于基于本地时间基准来确定所接收的总线复位脉冲的长度。网络节点中的总线复位检测器还适于基于所确定的接收总线复位脉冲的长度来调整本地时间基准。

10. 发明申请

US20130154594A1 ELECTRONIC DEVICE AND METHOD FOR POWER MEASUREMENT 审中-公开
标题翻译：用于功率测量的电子设备和方法
公开(公告)号：US20130154594A1
公开(公告)日：2013-06-20
申请号：US13329073
申请日：2011-12-16
申请人： Johann Zipperer , Peter Weber
发明人： Johann Zipperer , Peter Weber
IPC分类号： G05F1/10
CPC分类号： H02M3/157
摘要： The invention relates to an electronic device comprising a switched mode power converter comprising a switched transistor, an inductor and an error amplifier. The switched transistor is configured to switch a current through the inductor. The error amplifier is configured to control the switching of the switched transistor to convert a primary voltage applied at the input into a secondary voltage at the output of the switched mode power converter. The electronic device further comprises an oscillator, a control logic stage and a digital counter. The control logic stage is coupled to receive a clock signal from the oscillator and to generate switching signals for the switched transistor in form of ON-time pulses with a constant ON-time according to a pulse density scheme. The counter is configured to count the number of ON-time pulses for determining the consumed power based on the number of ON-time pulses per time.
摘要翻译：本发明涉及包括开关晶体管，电感器和误差放大器的开关式功率转换器的电子设备。开关晶体管被配置为切换电流通过电感器。误差放大器被配置为控制开关晶体管的开关，以将在输入端施加的初级电压转换为开关模式功率转换器的输出端的次级电压。电子设备还包括振荡器，控制逻辑级和数字计数器。控制逻辑级被耦合以从振荡器接收时钟信号，并且根据脉冲密度方案以具有恒定导通时间的导通时间脉冲的形式产生开关晶体管的开关信号。计数器被配置为基于每次的接通时间脉冲数来计数用于确定消耗功率的导通时间脉冲数。

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