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1. 发明授权

US08665635B2 Memory cell 有权
标题翻译：存储单元
公开(公告)号：US08665635B2
公开(公告)日：2014-03-04
申请号：US13618109
申请日：2012-09-14
申请人： John D. Porter
发明人： John D. Porter
IPC分类号： G11C11/00
CPC分类号： G11C13/004 , G11C13/0004 , G11C2013/0054 , G11C2213/72 , G11C2213/79
摘要： Methods, and circuits, are disclosed for operating a programmable memory device. One method embodiment includes storing a value as a state in a first memory cell and as a complementary state in a second memory cell. Such a method further includes determining the state of the first memory cell using a first self-biased sensing circuit and the complementary state of the second memory cell using a second self-biased sensing circuit, and comparing in a differential manner an indication of the state of the first memory cell to a reference indication of the complementary state of the second memory cell to determine the value.
摘要翻译：公开了用于操作可编程存储器件的方法和电路。一个方法实施例包括将值作为状态存储在第一存储器单元中并作为互补状态存储在第二存储器单元中。这种方法还包括使用第一自偏置感测电路确定第一存储单元的状态和使用第二自偏置感测电路来确定第二存储单元的互补状态，并以差分方式比较状态指示的第一存储器单元的第二存储器单元的补充状态的参考指示以确定该值。

2. 发明申请

US20130010528A1 SENSING RESISTANCE VARIABLE MEMORY 有权
公开(公告)号：US20130010528A1
公开(公告)日：2013-01-10
申请号：US13619253
申请日：2012-09-14
申请人： Pradeep Ramani , John D. Porter
发明人： Pradeep Ramani , John D. Porter
IPC分类号： G11C11/00
CPC分类号： G11C13/0007 , G11C11/5678 , G11C11/5685 , G11C13/0004 , G11C13/0023 , G11C13/0028 , G11C13/004 , G11C13/0061 , G11C13/0069 , G11C2013/0054 , G11C2013/0088 , G11C2211/5622 , G11C2211/5634 , G11C2213/31 , G11C2213/32
摘要： The present disclosure includes devices and methods for operating resistance variable memory. One device embodiment includes an array of memory cells wherein a number of the cells are commonly coupled to a select line, the number cells including a number of data cells programmable within a number of target threshold resistance (Rt) ranges which correspond to a number of data states, and a number of reference cells interleaved with the data cells and programmable within the number of target Rt ranges. The aforementioned device embodiment also includes control circuitry coupled to the array and configured to sense a level associated with at least one data cell and at least one reference cell, and compare the sensed level associated with the at least one data cell with the sensed level associated with the at least one reference cell to determine a data state of the at least one data cell.

3. 发明申请

US20110205791A1 TEMPERATURE COMPENSATION IN MEMORY DEVICES AND SYSTEMS 有权
标题翻译：存储器件和系统中的温度补偿
公开(公告)号：US20110205791A1
公开(公告)日：2011-08-25
申请号：US13101307
申请日：2011-05-05
申请人： John D. Porter , Jennifer E. Taylor
发明人： John D. Porter , Jennifer E. Taylor
IPC分类号： G11C11/00 , G11C7/04
CPC分类号： G11C17/16 , G11C7/04 , G11C7/1006 , G11C17/18
摘要： The present disclosure includes devices, methods, and systems for temperature compensation in memory devices, such as resistance variable memory, among other types of memory. One or more embodiments can include a memory device including a table with an output that is used to create a multiplication factor for a current to compensate for temperature changes in the memory device, where the output depends on an operating temperature of the memory device and a difference in the current between a highest specified operating temperature and a lowest specified operating temperature of the memory device.
摘要翻译：本公开包括用于存储器件中的温度补偿的装置，方法和系统，诸如电阻变量存储器以及其它类型的存储器。一个或多个实施例可以包括存储器设备，其包括具有输出的表，该输出用于产生用于补偿存储器件中的温度变化的电流的乘法因子，其中输出取决于存储器件的工作温度和存储器件的最高规定工作温度和最低规定工作温度之间的电流差。

4. 发明申请

US20110085375A1 METHODS FOR DETERMINING RESISTANCE OF PHASE CHANGE MEMORY ELEMENTS 有权
标题翻译：确定相变记忆元件电阻的方法
公开(公告)号：US20110085375A1
公开(公告)日：2011-04-14
申请号：US12969364
申请日：2010-12-15
申请人： Jennifer Taylor , John D. Porter
发明人： Jennifer Taylor , John D. Porter
IPC分类号： G11C11/00
CPC分类号： G11C13/0004 , G11C11/56 , G11C11/5678 , G11C13/004 , G11C27/005 , G11C29/50 , G11C29/50008 , G11C2213/72 , G11C2213/79
摘要： Methods for measuring the resistance of multiple memory elements are disclosed. The memory elements may be multi-bit memory and through precise measurement of resistance of the multi-bit memory elements, determination of how many and which memory elements fall into specific memory ranges can be accomplished. Furthermore, storage and/or display of this information may allow for the creation of resistance distribution histograms for modeling of one or more memory arrays.
摘要翻译：公开了用于测量多个存储元件的电阻的方法。存储器元件可以是多位存储器，并且通过精确测量多位存储器元件的电阻，可以实现多少和哪些存储器元件落入特定存储器范围的确定。此外，该信息的存储和/或显示可以允许创建用于一个或多个存储器阵列的建模的电阻分布直方图。

5. 发明授权

US07813167B2 Memory cell 有权
标题翻译：存储单元
公开(公告)号：US07813167B2
公开(公告)日：2010-10-12
申请号：US12053236
申请日：2008-03-21
申请人： John D. Porter
发明人： John D. Porter
IPC分类号： G11C11/00
CPC分类号： G11C13/004 , G11C13/0004 , G11C2013/0054 , G11C2213/72 , G11C2213/79
摘要： Methods, and circuits, are disclosed for operating a programmable memory device. One method embodiment includes storing a value as a state in a first memory cell and as a complementary state in a second memory cell. Such a method further includes determining the state of the first memory cell using a first self-biased sensing circuit and the complementary state of the second memory cell using a second self-biased sensing circuit, and comparing in a differential manner an indication of the state of the first memory cell to a reference indication of the complementary state of the second memory cell to determine the value.
摘要翻译：公开了用于操作可编程存储器件的方法和电路。一个方法实施例包括将值作为状态存储在第一存储器单元中并作为互补状态存储在第二存储器单元中。这种方法还包括使用第一自偏置感测电路确定第一存储单元的状态和使用第二自偏置感测电路来确定第二存储单元的互补状态，并以差分方式比较状态指示的第一存储器单元的第二存储器单元的补充状态的参考指示以确定该值。

6. 发明申请

US20100214821A1 CAPACITIVE DIVIDER SENSING OF MEMORY CELLS 有权
标题翻译：记忆细胞的电容分辨率检测
公开(公告)号：US20100214821A1
公开(公告)日：2010-08-26
申请号：US12770362
申请日：2010-04-29
申请人： Jennifer E. Taylor , John D. Porter
发明人： Jennifer E. Taylor , John D. Porter
IPC分类号： G11C11/00 , G11C7/06 , G11C5/14
CPC分类号： G11C13/004 , G11C11/56 , G11C11/5678 , G11C13/0004 , G11C2013/0054 , G11C2211/5634
摘要： The present disclosure includes devices and methods for sensing resistance variable memory cells. One device embodiment includes at least one resistance variable memory cell, and a capacitive divider configured to generate multiple reference levels in association with the at least one resistance variable memory cell.
摘要翻译：本公开包括用于感测电阻可变存储单元的装置和方法。一个器件实施例包括至少一个电阻可变存储器单元和电容分压器，其被配置成与至少一个电阻变量存储单元相关联地产生多个参考电平。

7. 发明申请

US20090244961A1 PHASE CHANGE MEMORY 有权
标题翻译：相变记忆
公开(公告)号：US20090244961A1
公开(公告)日：2009-10-01
申请号：US12056045
申请日：2008-03-26
申请人： Pradeep Ramani , John D. Porter
发明人： Pradeep Ramani , John D. Porter
IPC分类号： G11C11/00
CPC分类号： G11C13/0004 , G11C13/0069 , G11C2013/0078 , G11C2013/0092 , G11C2213/79
摘要： The present disclosure includes devices and methods for operating phase change memory cells. One or more embodiments include applying a programming signal to a phase change material of a memory cell, and decreasing a magnitude of a trailing portion of the applied programming signal successively according to a number of particular decrements. The magnitude and the duration of the number of particular decrements correspond to particular programmed values.
摘要翻译：本公开包括用于操作相变存储器单元的装置和方法。一个或多个实施例包括将编程信号施加到存储器单元的相变材料，以及根据特定减量的数量连续减小所应用的编程信号的尾部的幅度。特定减量数量的大小和持续时间对应于特定的编程值。

8. 发明授权

US07405463B2 Gate dielectric antifuse circuit to protect a high-voltage transistor 有权
标题翻译：栅介质反熔丝电路保护高压晶体管
公开(公告)号：US07405463B2
公开(公告)日：2008-07-29
申请号：US11426523
申请日：2006-06-26
申请人： Kenneth W. Marr , John D. Porter
发明人： Kenneth W. Marr , John D. Porter
IPC分类号： H01L29/04 , H01L29/10 , H01L31/036
CPC分类号： G11C17/16 , G11C17/18 , H01L23/5252 , H01L27/0248 , H01L29/0847 , H01L29/1045 , H01L29/7835 , H01L2924/0002 , H01L2924/00
摘要： According to embodiments of the present invention, circuits have elements to protect a high-voltage transistor in a gate dielectric antifuse circuit. An antifuse has a layer of gate dielectric between a first terminal coupled to receive an elevated voltage and a second terminal, and a high-voltage transistor is coupled to the antifuse and has a gate terminal. An intermediate voltage between the supply voltage and the elevated voltage is coupled to the gate terminal of the high-voltage transistor to protect the high-voltage transistor.
摘要翻译：根据本发明的实施例，电路具有用于保护栅介质反熔丝电路中的高压晶体管的元件。反熔丝在耦合以接收升高电压的第一端子和第二端子之间具有栅极电介质层，并且高压晶体管耦合到反熔丝并具有栅极端子。电源电压和升高电压之间的中间电压耦合到高电压晶体管的栅极端子，以保护高压晶体管。

9. 发明授权

US07126871B2 Circuits and methods to protect a gate dielectric antifuse 有权
标题翻译：保护栅极电介质反熔丝的电路和方法
公开(公告)号：US07126871B2
公开(公告)日：2006-10-24
申请号：US10770800
申请日：2004-02-03
申请人： Kenneth W. Marr , John D. Porter
发明人： Kenneth W. Marr , John D. Porter
IPC分类号： G11C7/00
CPC分类号： G11C17/18 , H01L23/5252 , H01L2924/0002 , H01L2924/00
摘要： According to embodiments of the present invention, an antifuse circuit is operated by coupling an elevated voltage to a first terminal of an antifuse, controlling current in the antifuse with a program driver circuit coupled to a second terminal of the antifuse, and shunting current around the antifuse with a bypass circuit coupled between the first terminal of the antifuse and the program driver circuit to protect the antifuse. The antifuse includes a layer of gate dielectric between the first terminal and the second terminal. The embodiments of the present invention protect a gate dielectric antifuse.
摘要翻译：根据本发明的实施例，通过将提升的电压耦合到反熔丝的第一端子来操作反熔丝电路，通过耦合到反熔丝的第二端子的编程驱动器电路来控制反熔丝中的电流，反熔丝与耦合在反熔丝的第一端子和程序驱动电路之间的旁路电路以保护反熔丝。反熔丝包括在第一端子和第二端子之间的栅极电介质层。本发明的实施例保护栅极绝缘反熔丝。

10. 发明授权

US06949948B2 Digital logic devices with extremely skewed trip points and reset circuitry for rapidly propagating signal edges 有权
标题翻译：数字逻辑器件具有极度偏斜的跳变点和复位电路，用于快速传播信号边沿
公开(公告)号：US06949948B2
公开(公告)日：2005-09-27
申请号：US10336503
申请日：2003-01-03
申请人： John D. Porter , Dean D. Gans , Larren G. Weber
发明人： John D. Porter , Dean D. Gans , Larren G. Weber
IPC分类号： H03K19/017 , H03K19/0175
CPC分类号： H03K19/01721
摘要： The invention includes digital logic devices with extremely skewed trip points and reset circuitry for rapidly propagating signal edges. Embodiments of skewed logic devices in accordance with the present invention include inverters, buffers, NOR gates and NAND gates for rapidly propagating a selected “fast” edge of an input signal. Additional embodiments include pulse stretchers, memory devices, substrates, computer systems and methods incorporating the skewed logic devices of the present invention. Each embodiment of a skewed logic device of the present invention is configured to propagate either a fast rising edge or fast falling edge of an output signal, i.e., the “fast” edge, at rates comparable to those of domino logic. An advantage of the skewed logic devices of the present invention over conventional CMOS logic devices is rapid edge propagation. Additionally, virtually all of the input gate loading is devoted to the fast edge being propagated. Additionally, the reset networks, as disclosed herein, are buffered by at least two gates, thus reducing loading seen by the input or the output of the skewed logic device.
摘要翻译：本发明包括具有非常偏斜的跳变点的数字逻辑器件和用于快速传播信号边缘的复位电路。根据本发明的偏斜逻辑器件的实施例包括用于快速传播输入信号的所选择的“快速”边沿的反相器，缓冲器，或非门和“与非”门。另外的实施例包括脉冲展开器，存储器件，衬底，计算机系统和结合本发明的倾斜逻辑器件的方法。本发明的倾斜逻辑器件的每个实施例被配置为以与多米诺逻辑的速率相当的速率传播输出信号的快速上升沿或快速下降沿，即“快速”边沿。与传统CMOS逻辑器件相比，本发明的偏斜逻辑器件的优点是快速的边沿传播。此外，实际上所有的输入门加载都用于传播的快速边缘。此外，如本文所公开的复位网络由至少两个门缓冲，从而减少由倾斜逻辑器件的输入或输出所看到的负载。

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