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1. 发明授权

US06421053B1 Block rendering method for a graphics subsystem 有权
标题翻译：图形子系统的块渲染方法
公开(公告)号：US06421053B1
公开(公告)日：2002-07-16
申请号：US09316097
申请日：1999-05-24
申请人： Charles Ray Johns , John Samuel Liberty , Brad William Michael , John Fred Spannaus
发明人： Charles Ray Johns , John Samuel Liberty , Brad William Michael , John Fred Spannaus
IPC分类号： G06T1120
CPC分类号： G06T15/80
摘要： Primitives are divided into span groups of 2N spans, and then processed in M×N blocks of pixels, with the pixel blocks preferably being as close to square as possible and therefore optimized for small spans and texture mapping. Each span group is rendered block-by-block in a serpentine manner from an initial or entry block, first in a direction away from the long edge of the primitive and then in a direction towards the long edge. The interpolators include a one-deep stack onto which pixel and texel information for the initial or entry block are pushed before rendering any other blocks within the span group. Blocks or pairs of blocks within different span subgroups of the span group are then alternately rendered, such that rendering zig-zags between the span subgroups as it proceeds to the end of the span group. Once the first end of a span group is reached, the values for the initial or entry block are popped from the stack and rendering resumes from the initial or entry block in the opposite direction, but in the same serpentine or zig-zag manner, until the other end of the span group is reached. The next span group, if any, is rendered starting with a block adjacent to the last block rendered in the previous span group. Memory bandwidth utilization between the pixel and texel cache and the frame buffer is thus improved, together with texel reuse during texture mapping, to reduce the total number of pixel and texel fetches required to render the primitive.
摘要翻译：原子被分成2N个跨度的跨度组，然后在M×N个像素块中进行处理，其中像素块优选尽可能接近正方形，因此针对小跨度和纹理映射进行优化。每个跨度组以蛇形方式从初始或进入块逐块渲染，首先在远离原始长边的方向上，然后朝向长边的方向。插值器包括一个深层堆叠，在渲染跨度组内的任何其他块之前，将初始或进入块的像素和纹素信息推送到其上。然后交替地渲染跨度组的不同跨度子组内的块或块对，使得当它进行到跨度组的末尾时，在跨越子组之间渲染之字形。一旦达到跨度组的第一个结束，初始或进入块的值从堆栈中弹出，并且渲染从初始或进入块以相反方向恢复，但是以相同的蛇形或锯齿形方式恢复，直到到达跨度组的另一端。下一个范围组（如果有的话）从与前一个范围组中呈现的最后一个块相邻的块开始绘制。因此，像素和纹素高速缓存和帧缓冲器之间的存储器带宽利用率在纹理映射期间与纹素复用一起得到改善，以减少呈现原始图像所需的像素和纹素提取的总数。

2. 发明授权

US08615742B2 Autonomic hotspot profiling using paired performance sampling 失效
标题翻译：使用配对性能采样的自动热点分析
公开(公告)号：US08615742B2
公开(公告)日：2013-12-24
申请号：US12946959
申请日：2010-11-16
申请人： Venkat Rajeev Indukuru , Daniel Owen , Alexander Erik Mericas , John Fred Spannaus
发明人： Venkat Rajeev Indukuru , Daniel Owen , Alexander Erik Mericas , John Fred Spannaus
IPC分类号： G06F9/44 , G06F9/45
CPC分类号： G06F11/3466 , G06F8/443 , G06F8/4442 , G06F9/3861 , G06F11/34 , G06F11/3471 , G06F11/3476 , G06F2201/86 , G06F2201/88 , G06F2201/885
摘要： A processor performance profiler is enabled to for identify specific instructions causing performance issues within a program being executed by a microprocessor through random sampling to find the worst-case offenders of a particular event type such as a cache miss or a branch mis-prediction. Tracking all instructions causing a particular event generates large data logs, creates performance penalties, and makes code analysis more difficult. However, by identifying and tracking the worst offenders within a random sample of events without having to hash all events results in smaller memory requirements for the performance profiler, lower performance impact while profiling, and decreased complexity to analyze the program to identify major performance issues, which, in turn, enables better optimization of the program in shorter developer time.
摘要翻译：处理器性能分析器能够用于识别由微处理器通过随机采样来执行的程序中导致性能问题的特定指令，以找到诸如高速缓存未命中或分支误预测的特定事件类型的最坏情况的违规者。跟踪导致特定事件的所有指令会生成大量数据日志，创建性能损失，并使代码分析更加困难。然而，通过识别和跟踪随机事件样本中的最坏罪犯，而不必对所有事件进行散列，从而导致性能分析器的较小内存需求，降低性能影响，同时分析并降低分析程序以识别主要性能问题的复杂性，这反过来，可以在较短的开发人员时间内更好地优化程序。

3. 发明授权

US08407624B2 Mouse movement using multiple thresholds utilizing linear exponential acceleration and sub-pixel precision 失效
标题翻译：利用线性指数加速度和子像素精度，使用多个阈值的鼠标移动
公开(公告)号：US08407624B2
公开(公告)日：2013-03-26
申请号：US12244351
申请日：2008-10-02
申请人： George Francis Ramsay, III , John Fred Spannaus
发明人： George Francis Ramsay, III , John Fred Spannaus
IPC分类号： G06F3/048
CPC分类号： G06F3/0481 , G06F3/038
摘要： Moving a pointer in a graphical user interface environment is provided. An input comprising an initial delta value determined by a device driver is received from the device driver. The initial delta value is located in a data structure. A new delta value associated with the initial delta value is selected from the data structure. A new position of a pointer in the graphical user interface environment is calculated based on the new delta value. The new position of the pointer is sent to the graphical user interface environment for rendering.
摘要翻译：提供了在图形用户界面环境中移动指针。从设备驱动器接收包括由设备驱动器确定的初始增量值的输入。初始增量值位于数据结构中。从数据结构中选择与初始增量值相关联的新增量值。基于新的增量值计算图形用户界面环境中指针的新位置。指针的新位置被发送到用于渲染的图形用户界面环境。

4. 发明授权

US07844849B2 System and method for identifying and manipulating logic analyzer data from multiple clock domains 有权
标题翻译：用于识别和操纵来自多个时钟域的逻辑分析仪数据的系统和方法
公开(公告)号：US07844849B2
公开(公告)日：2010-11-30
申请号：US11757450
申请日：2007-06-04
申请人： Michael Joseph Genden , John Fred Spannaus
发明人： Michael Joseph Genden , John Fred Spannaus
IPC分类号： G06F1/04
CPC分类号： G01R31/3177
摘要： A system and method for identifying and manipulating logic analyzer data from multiple clock domains is presented. A logic analyzer receives debug data and determines whether the debug data is a full frequency data type, a half frequency data type, or a crossed data type. Once determined, the logic analyzer reconstructs the debug data such that debug condition-matching logic may process the reconstructed data in a full frequency domain. For half frequency data types, the logic analyzer adds masked data values to the data in order to reconstruct the data into to the full frequency domain before processing the data. For crossed data types, the logic analyzer reconstructs the data into its original format before processing the data in a full frequency domain.
摘要翻译：提出了一种从多个时钟域识别和操纵逻辑分析仪数据的系统和方法。逻辑分析仪接收调试数据并确定调试数据是全频数据类型，半频数据类型还是交叉数据类型。一旦确定，逻辑分析器重构调试数据，使得调试条件匹配逻辑可以处理全频域中的重构数据。对于半频数据类型，逻辑分析仪将掩码的数据值添加到数据中，以便在处理数据之前将数据重建为全频域。对于交叉数据类型，逻辑分析仪将数据重新构成其原始格式，然后在全频域处理数据。

5. 发明申请

US20140059334A1 Autonomic Hotspot Profiling Using Paired Performance Sampling 有权
标题翻译：使用配对性能采样的自动热点分析
公开(公告)号：US20140059334A1
公开(公告)日：2014-02-27
申请号：US14067212
申请日：2013-10-30
申请人： Venkat Rajeev Indukuru , Daniel Owen , Alexander Erik Mericas , John Fred Spannaus
发明人： Venkat Rajeev Indukuru , Daniel Owen , Alexander Erik Mericas , John Fred Spannaus
IPC分类号： G06F9/38
CPC分类号： G06F11/3466 , G06F8/443 , G06F8/4442 , G06F9/3861 , G06F11/34 , G06F11/3471 , G06F11/3476 , G06F2201/86 , G06F2201/88 , G06F2201/885
摘要： A processor performance profiler is enabled to for identify specific instructions causing performance issues within a program being executed by a microprocessor through random sampling to find the worst-case offenders of a particular event type such as a cache miss or a branch mis-prediction. Tracking all instructions causing a particular event generates large data logs, creates performance penalties, and makes code analysis more difficult. However, by identifying and tracking the worst offenders within a random sample of events without having to hash all events results in smaller memory requirements for the performance profiler, lower performance impact while profiling, and decreased complexity to analyze the program to identify major performance issues, which, in turn, enables better optimization of the program in shorter developer time.
摘要翻译：处理器性能分析器能够用于识别由微处理器通过随机采样来执行的程序中导致性能问题的特定指令，以找到诸如高速缓存未命中或分支误预测的特定事件类型的最坏情况的违规者。跟踪导致特定事件的所有指令会生成大量数据日志，创建性能损失，并使代码分析更加困难。然而，通过识别和跟踪随机事件样本中的最坏罪犯，而不必对所有事件进行散列，从而导致性能分析器的较小内存需求，降低性能影响，同时分析并降低分析程序以识别主要性能问题的复杂性，这反过来，可以在较短的开发人员时间内更好地优化程序。

6. 发明申请

US20120124560A1 Autonomic Hotspot Profiling Using Paired Performance Sampling 失效
标题翻译：使用配对性能采样的自动热点分析
公开(公告)号：US20120124560A1
公开(公告)日：2012-05-17
申请号：US12946959
申请日：2010-11-16
申请人： Venkat Rajeev Indukuru , Daniel Owen , Alexander Erik Mericas , John Fred Spannaus
发明人： Venkat Rajeev Indukuru , Daniel Owen , Alexander Erik Mericas , John Fred Spannaus
IPC分类号： G06F9/44
CPC分类号： G06F11/3466 , G06F8/443 , G06F8/4442 , G06F9/3861 , G06F11/34 , G06F11/3471 , G06F11/3476 , G06F2201/86 , G06F2201/88 , G06F2201/885
摘要： A processor performance profiler is enabled to for identify specific instructions causing performance issues within a program being executed by a microprocessor through random sampling to find the worst-case offenders of a particular event type such as a cache miss or a branch mis-prediction. Tracking all instructions causing a particular event generates large data logs, creates performance penalties, and makes code analysis more difficult. However, by identifying and tracking the worst offenders within a random sample of events without having to hash all events results in smaller memory requirements for the performance profiler, lower performance impact while profiling, and decreased complexity to analyze the program to identify major performance issues, which, in turn, enables better optimization of the program in shorter developer time.
摘要翻译：处理器性能分析器能够用于识别由微处理器通过随机采样来执行的程序中导致性能问题的特定指令，以找到诸如高速缓存未命中或分支误预测的特定事件类型的最坏情况的违规者。跟踪导致特定事件的所有指令会生成大量数据日志，创建性能损失，并使代码分析更加困难。然而，通过识别和跟踪随机事件样本中的最坏罪犯，而不必对所有事件进行散列，从而导致性能分析器的较小内存需求，降低性能影响，同时分析并降低分析程序以识别主要性能问题的复杂性，这反过来，可以在较短的开发人员时间内更好地优化程序。

7. 发明申请

US20080301500A1 System and Method for Identifying and Manipulating Logic Analyzer Data from Multiple Clock Domains 有权
标题翻译：用于从多个时钟域识别和操纵逻辑分析仪数据的系统和方法
公开(公告)号：US20080301500A1
公开(公告)日：2008-12-04
申请号：US11757450
申请日：2007-06-04
申请人： Michael Joseph Genden , John Fred Spannaus
发明人： Michael Joseph Genden , John Fred Spannaus
IPC分类号： G06F11/25
CPC分类号： G01R31/3177
摘要： A system and method for identifying and manipulating logic analyzer data from multiple clock domains is presented. A logic analyzer receives debug data and determines whether the debug data is a full frequency data type, a half frequency data type, or a crossed data type. Once determined, the logic analyzer reconstructs the debug data such that debug condition-matching logic may process the reconstructed data in a full frequency domain. For half frequency data types, the logic analyzer adds masked data values to the data in order to reconstruct the data into to the full frequency domain before processing the data. For crossed data types, the logic analyzer reconstructs the data into its original format before processing the data in a full frequency domain.
摘要翻译：提出了一种从多个时钟域识别和操纵逻辑分析仪数据的系统和方法。逻辑分析仪接收调试数据并确定调试数据是全频数据类型，半频数据类型还是交叉数据类型。一旦确定，逻辑分析器重构调试数据，使得调试条件匹配逻辑可以处理全频域中的重构数据。对于半频数据类型，逻辑分析仪将掩码的数据值添加到数据中，以便在处理数据之前将数据重建为全频域。对于交叉数据类型，逻辑分析仪将数据重新构成其原始格式，然后在全频域处理数据。

8. 发明授权

US5790125A System and method for use in a computerized imaging system to efficiently transfer graphics information to a graphics subsystem employing masked span 失效
标题翻译：用于计算机化成像系统中的系统和方法用于将图形信息有效地传送到使用掩蔽跨度的图形子系统
公开(公告)号：US5790125A
公开(公告)日：1998-08-04
申请号：US636093
申请日：1996-04-22
申请人： Thuy-Linh Tran Bui , Charles Ray Johns , John Thomas Roberson , John Fred Spannaus
发明人： Thuy-Linh Tran Bui , Charles Ray Johns , John Thomas Roberson , John Fred Spannaus
IPC分类号： G06F5/00 , G06F3/14 , G06T11/00 , G06T15/00
CPC分类号： G06F3/14
摘要： Graphics information is efficiently transferred from a host computer to a graphics subsystem in which rendering and pixel data is generated by the host system. A masked span operation provides an assist for 3D rendering performed by the system processor of the host and other system resources. Storage of depth, alpha, stencil, and other pixel data is in system memory including one or more ancillary graphics buffers. The main processor of the host system generates pixel data associated with an image. This data is checked against the buffers. As a result of such checking, a mask is generated by the host system. The mask is transferred in burst mode across the host-graphic subsystem PCI bus to the graphics subsystem in combination with span width, and in the case of interpolated color, color base and color increment data, and X,Y coordinate of the first pixel. In the graphics subsystem the mask is employed with the other data to load the frame buffer with the portion of pixel data defined by the mask.
摘要翻译：图形信息从主计算机有效地传送到图形子系统，其中渲染和像素数据由主机系统生成。屏蔽跨度操作提供了由主机的系统处理器和其他系统资源执行的3D渲染的辅助。深度，阿尔法，模板和其他像素数据的存储在系统存储器中，包括一个或多个辅助图形缓冲器。主机系统的主处理器生成与图像相关联的像素数据。此缓冲区检查此数据。作为这种检查的结果，主机系统产生掩码。掩模以突发模式通过主机图形子系统PCI总线传送到图形子系统，并结合跨度宽度，并且在内插颜色，色底和颜色增量数据以及第一像素的X，Y坐标的情况下。在图形子系统中，使用掩码与其他数据一起加载由该掩码定义的像素数据部分的帧缓冲器。

9. 发明申请

US20100088652A1 MOUSE MOVEMENT USING MULTIPLE THRESHOLDS UTILIZING LINEAR EXPONENTIAL ACCELERATION AND SUB-PIXEL PRECISION 失效
标题翻译：使用多个阈值的鼠标移动使用线性指数加速和子像素精度
公开(公告)号：US20100088652A1
公开(公告)日：2010-04-08
申请号：US12244351
申请日：2008-10-02
申请人： George Francis Ramsay, III , John Fred Spannaus
发明人： George Francis Ramsay, III , John Fred Spannaus
IPC分类号： G06F3/048 , G06F3/033
CPC分类号： G06F3/0481 , G06F3/038
摘要： Moving a pointer in a graphical user interface environment is provided. An input comprising an initial delta value determined by a device driver is received from the device driver. The initial delta value is located in a data structure. A new delta value associated with the initial delta value is selected from the data structure. A new position of a pointer in the graphical user interface environment is calculated based on the new delta value. The new position of the pointer is sent to the graphical user interface environment for rendering.
摘要翻译：提供了在图形用户界面环境中移动指针。从设备驱动器接收包括由设备驱动器确定的初始增量值的输入。初始增量值位于数据结构中。从数据结构中选择与初始增量值相关联的新增量值。基于新的增量值计算图形用户界面环境中指针的新位置。指针的新位置被发送到用于渲染的图形用户界面环境。

10. 发明授权

US06483503B1 Pixel data merging apparatus and method therefor 有权
标题翻译：像素数据合并装置及其方法
公开(公告)号：US06483503B1
公开(公告)日：2002-11-19
申请号：US09343447
申请日：1999-06-30
申请人： John Fred Spannaus , John Alvin Voltin
发明人： John Fred Spannaus , John Alvin Voltin
IPC分类号： G09G500
CPC分类号： G06F3/1438 , G06F3/1431 , G06T1/20 , G09G5/006 , G09G5/366 , G09G2340/12
摘要： A pixel merge apparatus and method has been implemented. Included is a configurable graphics device, which may serve as a standalone graphics engine, or as a master or slave in a master/slave configuration. In stand alone mode, the mechanism drives a display device with native pixel data. A device configured in master mode is operable for receiving pixel data from a corresponding slave device, and merging the slave pixel data with native pixel data generated by a rasterizer within the ASIC. Data is communicated between slave and master using a digital data link which may also serve to drive a flat panel display in standalone mode. A FIFO, active in the master, mediates the transfer of the slave pixel data and permits switching between native and slave pixel data with signal pixel resolution. Pixel data may be merged on a frame-by-frame basis, or in split frame mode wherein a first portion of the graphic shown on a display device constitutes native pixels generated in the rasterizer corresponding to the master device, and a second portion of the displayed graphic includes pixels generated by the rasterizer in the slave device.
摘要翻译：已经实现像素合并装置和方法。包括一个可配置的图形设备，可以用作独立的图形引擎，也可以作为主/从设备中的主设备或从设备。在独立模式下，机构驱动具有原始像素数据的显示设备。以主模式配置的设备可操作用于从相应的从设备接收像素数据，并且将从像素数据与由ASIC内的光栅化器产生的原始像素数据合并。使用数字数据链路在从机和主机之间传送数据，数字数据链路也可用于以独立模式驱动平板显示器。在主器件中有效的FIFO介导从像素数据的传输，并允许在信号像素分辨率之间切换本机和从属像素数据。像素数据可以逐帧合并，或者以分割帧模式合并，其中显示设备上显示的图形的第一部分构成在与主设备对应的光栅化器中生成的本机像素，并且第二部分显示的图形包括由从设备中的光栅化器生成的像素。

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