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1. 发明授权

US09983793B2 Memory resource optimization method and apparatus 有权
公开(公告)号：US09983793B2
公开(公告)日：2018-05-29
申请号：US15712296
申请日：2017-09-22
申请人： HUAWEI TECHNOLOGIES CO., LTD.
发明人： Lei Liu , Chengyong Wu , Xiaobing Feng
IPC分类号： G06F3/06 , G06F11/34 , G06F9/50 , G06F12/0811 , G06F12/0842 , G06F12/0897 , G06F12/084
CPC分类号： G06F3/0605 , G06F3/0631 , G06F3/0644 , G06F3/0653 , G06F3/0679 , G06F9/5016 , G06F11/3409 , G06F11/3433 , G06F11/3471 , G06F12/0811 , G06F12/084 , G06F12/0842 , G06F12/0897 , G06F2201/81 , G06F2212/1041 , G06F2212/282 , G06F2212/6042 , G06F2212/653
摘要： Embodiments of the present invention provide a memory resource optimization method and apparatus, relate to the computer field, solve a problem that existing multi-level memory resources affect each other, and optimize an existing single partitioning mechanism. A specific solution is: obtaining performance data of each program in a working set by using a page coloring technology, obtaining a category of each program in light of a memory access frequency, selecting, according to the category of each program, a page coloring-based partitioning policy corresponding to the working set, and writing the page coloring-based partitioning policy to an operating system kernel, to complete corresponding page coloring-based partitioning processing. The present invention is used to eliminate or reduce mutual interference of processes or threads on a memory resource in light of a feature of the working set, thereby improving overall performance of a computer.

2. 发明授权

US09910757B2 Semiconductor device, log acquisition method and electronic apparatus 有权
公开(公告)号：US09910757B2
公开(公告)日：2018-03-06
申请号：US14995686
申请日：2016-01-14
申请人： Naoyuki Yamada
发明人： Naoyuki Yamada
IPC分类号： G06F12/00 , G06F11/34 , G06F21/79
CPC分类号： G06F11/3471 , G06F11/3466 , G06F11/3476 , G06F21/79 , G06F2201/86
摘要： A semiconductor device includes a CPU access detection unit configured to detect a predetermined access among accesses from a CPU to the semiconductor device, based on an access detection condition; an internal signal detection unit configured to detect a predetermined internal signal among internal signals from a function module in the semiconductor device, based on an event detection condition, the predetermined access and the predetermined internal signal being subjects for the log acquisition; an internal memory unit configured to store at least one of log data for the predetermined access detected by the CPU access detection unit and log data for the predetermined internal signal detected by the internal signal detection unit; a setting input unit configured to receive an input of setting data; and a detection condition setting unit configured to set the access detection condition and the event detection condition based on the setting data.

3. 发明授权

US09692662B2 Predictive diagnosis of SLA violations in cloud services by seasonal trending and forecasting with thread intensity analytics 有权
公开(公告)号：US09692662B2
公开(公告)日：2017-06-27
申请号：US15275035
申请日：2016-09-23
申请人： ORACLE INTERNATIONAL CORPORATION
发明人： Eric S. Chan , Rafiul Ahad , Adel Ghoneimy , Adriano Covello Santos
IPC分类号： G06F9/46 , H04L12/24 , G06F17/30 , G06F9/48 , G06F11/00 , G06F11/07 , G06F11/34 , G06F11/30
CPC分类号： H04L41/5009 , G06F9/4881 , G06F11/008 , G06F11/0715 , G06F11/0718 , G06F11/0751 , G06F11/0778 , G06F11/079 , G06F11/3003 , G06F11/3037 , G06F11/34 , G06F11/3409 , G06F11/3419 , G06F11/3452 , G06F11/3471 , G06F17/30289 , G06F17/30598 , G06F2201/865 , G06F2201/88
摘要： Data can be categorized into facts, information, hypothesis, and directives. Activities that generate certain categories of data based on other categories of data through the application of knowledge which can be categorized into classifications, assessments, resolutions, and enactments. Activities can be driven by a Classification-Assessment-Resolution-Enactment (CARE) control engine. The CARE control and these categorizations can be used to enhance a multitude of systems, for example diagnostic system, such as through historical record keeping, machine learning, and automation. Such a diagnostic system can include a system that forecasts computing system failures based on the application of knowledge to system vital signs such as thread or stack segment intensity and memory heap usage. These vital signs are facts that can be classified to produce information such as memory leaks, convoy effects, or other problems. Classification can involve the automatic generation of classes, states, observations, predictions, norms, objectives, and the processing of sample intervals having irregular durations.

4. 发明授权

US09678883B2 System and method for detecting false sharing 有权
公开(公告)号：US09678883B2
公开(公告)日：2017-06-13
申请号：US14335621
申请日：2014-07-18
申请人： Futurewei Technologies, Inc.
发明人： Tongping Liu , Chen Tian , Ziang Hu
IPC分类号： G06F12/08 , G06F12/0891
CPC分类号： G06F11/3003 , G06F8/443 , G06F11/3037 , G06F11/3065 , G06F11/3089 , G06F11/3093 , G06F11/3428 , G06F11/3466 , G06F11/3471 , G06F12/0842 , G06F12/0844 , G06F12/0891 , G06F2201/865 , G06F2201/885 , G06F2212/1016 , G06F2212/507
摘要： In one embodiment, a method for detecting false sharing includes running code on a plurality of cores, where the code includes instrumentation and tracking cache invalidations in the code while running the code to produce tracked invalidations in accordance with the instrumentation, where tracking the cache invalidations includes tracking cache accesses to a plurality of cache lines by a plurality of tasks. The method also includes reporting false sharing in accordance with the tracked invalidations to produce a false sharing report.

5. 发明授权

US09626274B2 Instruction and logic for tracking access to monitored regions 有权
公开(公告)号：US09626274B2
公开(公告)日：2017-04-18
申请号：US14580676
申请日：2014-12-23
申请人： Ahmad Yasin , Rajshree A. Chabukswar , Ofer Levy , Michael W. Chynoweth , Charlie J. Hewett
发明人： Ahmad Yasin , Rajshree A. Chabukswar , Ofer Levy , Michael W. Chynoweth , Charlie J. Hewett
IPC分类号： G06F11/00 , G06F11/34 , G06F11/30 , G06F9/38
CPC分类号： G06F11/3471 , G06F9/30076 , G06F9/38 , G06F11/3024 , G06F11/3037 , G06F11/3466 , G06F11/348 , G06F2201/81 , G06F2201/88
摘要： A processor includes a front end, a decoder, a retirement unit, and a performance monitoring unit. The front end includes a decoder with logic to receive a tracking instruction to enable tracking of execution of a region of memory. The instruction is to define an address range of the region. The retirement includes logic to retire the tracking instruction and candidate instructions. The performance monitoring unit includes logic to determine that the candidate instructions are associated with an entrance and an exit to the address range, and to generate an alert based on the candidate instructions association with the entrance and the exit.

6. 发明申请

US20160140014A1 APPARATUS AND METHOD FOR DISTRIBUTED INSTRUCTION TRACE IN A PROCESSOR SYSTEM 有权
标题翻译：处理器系统中分布式指令跟踪的装置和方法
公开(公告)号：US20160140014A1
公开(公告)日：2016-05-19
申请号：US14541841
申请日：2014-11-14
申请人： Cavium, Inc.
发明人： Gerald Lampert , David Kravitz , Bryan W. Chin
IPC分类号： G06F11/34 , G06F11/07
CPC分类号： G06F11/3495 , G06F11/0751 , G06F11/0781 , G06F11/079 , G06F11/3024 , G06F11/3072 , G06F11/3452 , G06F11/3471 , G06F11/348
摘要： One disclosed embodiment provides an integrated circuit that has a plurality of processors and a plurality of processor trace collection logic units. Each processor trace collection logic unit corresponds with, and is operatively coupled to, one of the processors. A separate filtering logic unit is operatively coupled to the plurality of processor trace collection logic units. In some embodiments of the integrated circuit, each processor trace collection logic unit is operative to continuously collect processor trace information from a corresponding operatively coupled processor. Each filtering logic unit is operative to monitor the continuous processor trace information for occurrence of a predetermined condition, and to store some of the processor trace information to memory in response to occurrence of that condition.
摘要翻译：一个公开的实施例提供了具有多个处理器和多个处理器跟踪收集逻辑单元的集成电路。每个处理器跟踪收集逻辑单元对应于并且可操作地耦合到一个处理器。单独的过滤逻辑单元可操作地耦合到多个处理器跟踪收集逻辑单元。在集成电路的一些实施例中，每个处理器跟踪收集逻辑单元可操作以从相应的可操作耦合的处理器连续收集处理器跟踪信息。每个过滤逻辑单元可操作以监视用于发生预定条件的连续处理器跟踪信息，并且响应于该条件的发生将一些处理器跟踪信息存储到存储器。

7. 发明申请

US20160085657A1 Thread Dump Viewer 审中-公开
标题翻译：线程转储查看器
公开(公告)号：US20160085657A1
公开(公告)日：2016-03-24
申请号：US14490257
申请日：2014-09-18
申请人： Matthias Braun , Dietrich Mostowoj , Ralf Schmelter , Johannes Scheerer , Steffen Schreiber , Thomas Klink , Michael Wintergerst
发明人： Matthias Braun , Dietrich Mostowoj , Ralf Schmelter , Johannes Scheerer , Steffen Schreiber , Thomas Klink , Michael Wintergerst
IPC分类号： G06F11/34
CPC分类号： G06F11/36 , G06F11/0715 , G06F11/0778 , G06F11/3003 , G06F11/302 , G06F11/323 , G06F11/3419 , G06F11/3466 , G06F11/3471 , G06F11/366 , G06F2201/865
摘要： A thread dump viewer presents information for a plurality of threads. The information about the threads can be presented in a table view. The thread dump viewer can allow the user to expand a thread in the table view to see a stack trace for the thread. The stack trace may include information for objects that are associated with other threads. For example, the thread may be waiting on a lock object locked by another thread. The thread dump viewer can present information about the associated thread based on a user interaction. This process can be continued iteratively, allowing the stack traces of interrelated threads to be seen to arbitrary depths.
摘要翻译：线程转储查看器提供多个线程的信息。有关线程的信息可以在表视图中显示。线程转储查看器可以允许用户在表视图中展开线程，以查看线程的堆栈跟踪。堆栈跟踪可以包括与其他线程相关联的对象的信息。例如，线程可能正在等待另一个线程锁定的锁定对象。线程转储查看器可以基于用户交互提供有关相关线程的信息。该过程可以迭代地继续，允许相关线程的堆栈轨迹被看到任意深度。

8. 发明授权

US09292418B2 Determining the vulnerability of multi-threaded program code to soft errors 有权
标题翻译：确定多线程程序代码对软错误的脆弱性
公开(公告)号：US09292418B2
公开(公告)日：2016-03-22
申请号：US14266131
申请日：2014-04-30
申请人： Advanced Micro Devices, Inc.
发明人： Vilas Sridharan , Mark E. Wilkening , Sudhanva Gurumurthi
IPC分类号： G06F9/44 , G06F11/36 , G06F11/34 , G06F9/48
CPC分类号： G06F11/3672 , G06F9/4843 , G06F11/34 , G06F11/3419 , G06F11/3471 , G06F11/3612
摘要： The described embodiments include a program code testing system that determines the vulnerability of multi-threaded program code to soft errors. For multi-threaded program code, two to more threads from the program code may access shared architectural structures while the program code is being executed. The program code testing system determines accesses of architectural structures made by the two or more threads of the multi-threaded program code and uses the determined accesses to determine a time for which the program code is exposed to soft errors. From this time, the program code testing system determines a vulnerability of the program code to soft errors.
摘要翻译：所描述的实施例包括程序代码测试系统，其确定多线程程序代码对软错误的脆弱性。对于多线程程序代码，程序代码中的两个到更多的线程可以在执行程序代码时访问共享架构结构。程序代码测试系统确定由多线程程序代码的两个或多个线程进行的架构结构的访问，并使用所确定的访问来确定程序代码暴露于软错误的时间。从这时起，程序代码测试系统将程序代码的漏洞确定为软错误。

9. 发明申请

US20150269054A1 Multiple Core Execution Trace Buffer 审中-公开
标题翻译：多个核心执行跟踪缓冲区
公开(公告)号：US20150269054A1
公开(公告)日：2015-09-24
申请号：US14217475
申请日：2014-03-18
申请人： LSI Corporation
发明人： Srinivasa Rao Kothamasu , Romeshkumar Bharatkumar Mehta
IPC分类号： G06F11/34
CPC分类号： G06F11/3476 , G06F11/006 , G06F11/3471 , G06F11/348 , G06F11/3636 , Y02D10/34
摘要： A data processing system includes a number of processor cores each having a trace interface with an address signal carrying program addresses being executed, a processor core identification circuit connected to the trace interfaces and operable to replace a portion of some of the program addresses with a processor core identification that identifies which of the processor cores provided the program addresses, and an execution trace buffer operable to store the program addresses associated with non-sequential execution in the processor cores. At least some of the program addresses include the processor core identification along with address bits.
摘要翻译：数据处理系统包括多个处理器核心，每个处理器核心具有与承载执行程序地址的地址信号的跟踪接口，处理器核心识别电路连接到跟踪接口并可操作以用处理器替换一部分程序地址核心标识，其识别提供程序地址的哪个处理器核心;以及执行跟踪缓冲器，其可操作以将与非顺序执行相关联的程序地址存储在处理器核心中。至少一些程序地址包括处理器核心标识以及地址位。

10. 发明授权

US09122786B2 Systems and/or methods for statistical online analysis of large and potentially heterogeneous data sets 有权
标题翻译：统计在线分析大型和潜在异质数据集的系统和/或方法
公开(公告)号：US09122786B2
公开(公告)日：2015-09-01
申请号：US13616952
申请日：2012-09-14
申请人： Michael Cammert , Christoph Heinz , Jürgen Krämer , Tobias Riemenschneider
发明人： Michael Cammert , Christoph Heinz , Jürgen Krämer , Tobias Riemenschneider
IPC分类号： G06F11/34 , G06F17/30
CPC分类号： G06F11/3471 , G06F17/30516 , G06F2201/86 , G06F2201/885
摘要： Certain example embodiments relate to using Complex Event Processing (CEP) techniques for statistical analysis of cache behavior and parameters, e.g., in connection with large, potentially heterogeneous data sets (e.g., “Big Data”). A dedicated stream mining operator registers a listener to a cache and receives notifications on cache operations. For selected element attributes, a first model estimates the probability density functions of the attribute values, delivering well-defined estimates of the attribute value distributions. A second model analyzes the time elements stay in the cache (“validity”). Validity is combined with the attribute value distribution. A meaningful analysis model (Cache Element Model) can be derived by combining additional summary statistics for the validity with the attribute value distribution, describing how long elements stay in the cache for attribute values of a specific region, and how the values are distributed. It may be used to inform administrative tasks such as, optimization of cache parameters.
摘要翻译：某些示例性实施例涉及使用复杂事件处理（CEP）技术来对高速缓存行为和参数进行统计分析，例如结合大的潜在异质数据集（例如，“大数据”）。一个专用的流挖掘操作员将一个监听器注册到缓存并接收高速缓存操作的通知。对于所选择的元素属性，第一模型估计属性值的概率密度函数，提供对属性值分布的明确定义的估计。第二个模型分析缓存中的时间元素（“有效性”）。有效性与属性值分布相结合。可以通过将有效性的附加摘要统计信息与属性值分布相结合来描述有意义的分析模型（Cache Element Model），描述元素在特定区域的属性值中停留在缓存中的时间以及值的分布情况。它可以用于通知管理任务，如优化缓存参数。

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