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    • 1. 发明授权
    • Normalizing and amplifying RNA
    • 归一化和扩增RNA
    • US06982143B1
    • 2006-01-03
    • US09597608
    • 2000-06-20
    • John NgaiDavid Lin
    • John NgaiDavid Lin
    • C12Q1/68C12Q1/48C12P19/34C07H21/04
    • C12N15/1096
    • The invention provides methods and compositions for normalizing and amplifying RNA populations. The methods generally comprise the steps of copying message RNA (mRNA) to form first single-stranded (ss) cDNA; converting the first ss-cDNA to first double-stranded (ds) cDNA; linearly amplifying the first ds-cDNA to form first amplified RNA (aRNA); tagging the 3′ end of the first aRNA with a known sequence to form 3′-tagged first aRNA; copying the 3′-tagged first aRNA to form second ss-cDNA; and normalizing the mRNA and/or the first aRNA.
    • 本发明提供了用于使RNA群体正常化和扩增的方法和组合物。 所述方法通常包括复制消息RNA(mRNA)以形成第一单链(ss)cDNA的步骤; 将第一个ss-cDNA转化为第一个双链(ds)cDNA; 线性扩增第一个ds-cDNA以形成第一个扩增的RNA(aRNA); 用已知序列标记第一个aRNA的3'末端以形成3'-标记的第一个aRNA; 复制3'标记的第一个aRNA以形成第二个ss-cDNA; 并使mRNA和/或第一个aRNA正常化。
    • 4. 发明授权
    • Odorant receptors
    • 气味受体
    • US06410249B1
    • 2002-06-25
    • US09619353
    • 2000-07-19
    • John NgaiDavid J. SpecaDavid M. LinEhud Y. IsacoffAndrew H. DittmanJinhong Fan
    • John NgaiDavid J. SpecaDavid M. LinEhud Y. IsacoffAndrew H. DittmanJinhong Fan
    • G01N33566
    • C07K14/705A61K38/00G01N2333/726
    • The invention provides methods and compositions relating to odorant receptors, including a general expression cloning methodology which is useful for identifying novel G protein-coupled receptors and a novel family of odorant receptors and related nucleic acids, ligands, agonists and antagonists. These compositions provide a wide variety of applications such as screening for related receptors, and by modulating the function of the disclosed receptors by modulating their expression or contacting them with agonists, antagonist or ligands modulating reproductive/sexual and non-sexual social behaviors mediated via the olfactory system, reproductive physiologies and olfactory system regulated feeding behaviors, migratory behaviors and events such as conception, implantation, estrous and menstruation.
    • 本发明提供了与加味剂受体相关的方法和组合物,包括一般表达克隆方法,其可用于鉴定新型G蛋白偶联受体和新颖的加味剂受体和相关核酸家族,配体,激动剂和拮抗剂。 这些组合物提供了各种各样的应用,例如筛选相关受体,并通过调节其所表达的受体的功能或通过调节其表达或与激动剂,拮抗剂或调节生殖/性和非性社交行为调节的配体 嗅觉系统,生殖生理和嗅觉系统调节饲养行为,迁移行为和受孕,植入,发情和月经等事件。
    • 5. 发明授权
    • Pass gate shadow latch
    • 通过门阴影锁
    • US08497721B1
    • 2013-07-30
    • US13160569
    • 2011-06-15
    • Hamid PartoviAlfred YeungJohn NgaiRonen Cohen
    • Hamid PartoviAlfred YeungJohn NgaiRonen Cohen
    • H03K3/289
    • H03K3/356156
    • A latch device is provided with a relay and a shadow latch. The relay has an input to accept a binary relay input signal, an input to accept a clock signal, an input to accept a shadow-Q signal, and an output to supply a binary Q signal value equal to the relay input signal value. The relay output is supplied in response to the relay input signal, the shadow-Q signal, and the clock signal. The shadow latch has an input to accept the relay input signal, an input to accept the clock signal, and an output to supply the shadow-Q signal with a value equal to an inverted Q signal value. The shadow latch output is supplied in response to the relay input signal and clock signal.
    • 闩锁装置设置有继电器和阴影闩锁。 继电器具有接受二进制继电器输入信号的输入端,接收时钟信号的输入端,接收阴影Q信号的输入端和提供等于继电器输入信号值的二进制Q信号值的输出端。 响应于继电器输入信号,阴影-Q信号和时钟信号提供继电器输出。 阴影锁存器具有用于接受继电器输入信号的输入端,用于接受时钟信号的输入端,以及用于向shadow-Q信号提供等于反相Q信号值的值的输出端。 响应于继电器输入信号和时钟信号提供阴影锁存输出。
    • 6. 发明授权
    • Hazard-free minimal-latency flip-flop (HFML-FF)
    • 无危险的最小延迟触发器(HFML-FF)
    • US08421514B1
    • 2013-04-16
    • US13225044
    • 2011-09-02
    • Alfred YeungHamid PartoviLuca RavezziJohn Ngai
    • Alfred YeungHamid PartoviLuca RavezziJohn Ngai
    • H03K3/289
    • H03K3/013H03K3/356156H03K3/35625
    • A hazard-free minimal-latency flip-flop (HFML-FF) is provided. A master latch includes an input to accept a D1 signal, an input to accept a clock signal, an input to accept an inverted shadow-D2 signal, and an output to supply a D2 signal. The master latch has an input to accept a shadow-D1 signal, an input to accept the clock signal, and an output to supply a shadow-D2 signal and the inverted shadow-D2 signal. The slave latch has an input to accept the D2 signal, an input to accept the clock signal, an input to accept an inverted shadow-Q signal, and an output to supply a Q signal. The slave latch has an input to accept either the D2 signal or the shadow-D2 signal, an input to accept the clock signal, and an output to supply a shadow-Q signal and the inverted shadow-Q signal. The design may use clocked inverters or pass gates.
    • 提供无危险的最小延迟触发器(HFML-FF)。 主锁存器包括接收D1信号的输入端,接受时钟信号的输入端,接收反相阴影D2信号的输入端和提供D2信号的输出端。 主锁存器具有接受阴影D1信号的输入端,接受时钟信号的输入端,以及提供阴影D2信号和反相阴影D2信号的输出端。 从锁存器具有接收D2信号的输入端,接受时钟信号的输入端,接收反相阴影Q信号的输入端和提供Q信号的输出端。 从锁存器具有接收D2信号或阴影D2信号的输入端,用于接受时钟信号的输入端和用于提供阴影Q信号和反相阴影Q信号的输出。 该设计可以使用时钟反相器或通过门。
    • 7. 发明授权
    • Methods for making nucleic acids
    • 制备核酸的方法
    • US6114152A
    • 2000-09-05
    • US49806
    • 1998-03-27
    • Tito SerafiniPercy LuuJohn NgaiDavid Lin
    • Tito SerafiniPercy LuuJohn NgaiDavid Lin
    • C12N15/09C12N15/10C12P19/34C12Q1/68
    • C12Q1/6809C12N15/1096C12Q1/6853
    • Nucleic acids are made by adding a known nucleotide sequence to the 3' end of a first RNA having a known sequence at the 5' end to form a second RNA and reverse transcribing the second RNA to form a cDNA. In one embodiment, the first RNA is an amplified mRNA, the known sequence at the 5' end comprises a poly(T) sequence, the adding step comprises using a polyadenyltransferase to add a poly(A) sequence to the 3' end, the reverse transcribing step is initiated at a duplex region comprising the poly(T) sequence hybridized to the poly(A) sequence, the cDNA is converted to double-stranded cDNA by a polymerase initiating from a noncovalently joined duplex region, and the double-stranded cDNA is transcribed to form one or more third RNAs.
    • 通过向5'末端具有已知序列的第一个RNA的3'末端添加已知的核苷酸序列以形成第二个RNA并逆转录录第二个RNA以形成cDNA来制备核酸。 在一个实施方案中,第一RNA是扩增的mRNA,5'末端的已知序列包含poly(T)序列,所述添加步骤包括使用聚腺苷酸转移酶向3'端添加聚(A)序列, 在包含与poly(A)序列杂交的poly(T)序列的双链体区域开始逆转录步骤,通过从非共价连接的双链体区域起始的聚合酶将cDNA转化为双链cDNA,双链 cDNA被转录以形成一个或多个第三RNA。
    • 8. 发明授权
    • Pseudo single-phase flip-flop (PSP-FF)
    • 伪单相触发器(PSP-FF)
    • US08604854B1
    • 2013-12-10
    • US13412679
    • 2012-03-06
    • Hamid PartoviAlfred YeungLuca RavezziJohn Ngai
    • Hamid PartoviAlfred YeungLuca RavezziJohn Ngai
    • H03K3/289H03K3/356
    • H03K3/356113
    • Disclosed herein is a pseudo single-phase flip-flop. The master section includes a pre-dissipation stage and a first keeper. The pre-dissipation stage discharges the first keeper to the mDb second binary value, and selectively charges the first keeper with the mDb first binary value in the master pass mode. The pre-dissipation stage selectively prevents the first keeper from charging to the mDb first binary value in response to one of the clock phases. The slave section includes a pre-charge stage, a second keeper, a post-dissipation stage, and a third keeper. The second keeper maintains a first binary value in a slave pass mode when the mDb signal has a second binary value. The second keeper supports the second binary value in the slave pass mode when the mDb signal has the first binary value. The third keeper maintains the Q signal binary value during the slave hold mode.
    • 这里公开了伪单相触发器。 主部分包括预耗散阶段和第一保持器。 预耗散级将第一保持器放电到mDb第二二进制值,并且在主通过模式中以mDb第一二进制值选择性地对第一保持器充电。 响应于时钟相位之一,预耗散级选择性地防止第一保持器充电到mDb第一二进制值。 从部分包括预充电阶段,第二保持器,后消耗阶段和第三保持器。 当mDb信号具有第二二进制值时,第二保持器保持从通模式中的第一二进制值。 当mDb信号具有第一二进制值时,第二保持器支持从通模式中的第二二进制值。 第三保持器在从机保持模式期间保持Q信号二进制值。
    • 10. 发明授权
    • Shadow latch
    • 阴影闩锁
    • US08618856B1
    • 2013-12-31
    • US13077949
    • 2011-03-31
    • Alfred YeungHamid PartoviJohn NgaiRonen Cohen
    • Alfred YeungHamid PartoviJohn NgaiRonen Cohen
    • H03K3/289
    • H03K3/013H03K3/356121
    • A latch device is provided with a driver and a shadow latch. The driver has an input to accept a binary driver input signal, an input to accept a clock signal, and an input to accept a shadow-Q signal. The driver has an output to supply a binary Q signal equal to the inverse of the driver input signal, in response to the driver input signal, the shadow-Q signal, and the clock signal. The shadow latch has an input to accept the driver input signal, and an input to accept the clock signal. The shadow latch has an output to supply the shadow-Q signal equal to the inverted Q signal, in response to the driver input signal and clock signal.
    • 闩锁装置设置有驱动器和阴影闩锁。 驱动器具有接受二进制驱动器输入信号的输入端,接受时钟信号的输入端和接收阴影Q信号的输入端。 驱动器具有响应于驱动器输入信号,阴影-Q信号和时钟信号而提供等于驱动器输入信号的倒数的二进制Q信号的输出。 阴影锁存器具有接受驱动器输入信号的输入端和接受时钟信号的输入端。 阴影锁存器具有响应于驱动器输入信号和时钟信号而提供等于反相Q信号的阴影Q信号的输出。